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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Driver for Realtek PCI-Express card reader4 *5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.6 *7 * Author:8 * Wei WANG (wei_wang@realsil.com.cn)9 * Micky Ching (micky_ching@realsil.com.cn)10 */11 12#ifndef __REALTEK_RTSX_XD_H13#define __REALTEK_RTSX_XD_H14 15#define XD_DELAY_WRITE16 17/* Error Codes */18#define XD_NO_ERROR 0x0019#define XD_NO_MEMORY 0x8020#define XD_PRG_ERROR 0x4021#define XD_NO_CARD 0x2022#define XD_READ_FAIL 0x1023#define XD_ERASE_FAIL 0x0824#define XD_WRITE_FAIL 0x0425#define XD_ECC_ERROR 0x0226#define XD_TO_ERROR 0x0127 28/* XD Commands */29#define READ1_1 0x0030#define READ1_2 0x0131#define READ2 0x5032#define READ_ID 0x9033#define RESET 0xff34#define PAGE_PRG_1 0x8035#define PAGE_PRG_2 0x1036#define BLK_ERASE_1 0x6037#define BLK_ERASE_2 0xD038#define READ_STS 0x7039#define READ_XD_ID 0x9A40#define COPY_BACK_512 0x8A41#define COPY_BACK_2K 0x8542#define READ1_1_2 0x3043#define READ1_1_3 0x3544#define CHG_DAT_OUT_1 0x0545#define RDM_DAT_OUT_1 0x0546#define CHG_DAT_OUT_2 0xE047#define RDM_DAT_OUT_2 0xE048#define CHG_DAT_OUT_2 0xE049#define CHG_DAT_IN_1 0x8550#define CACHE_PRG 0x1551 52/* Redundant Area Related */53#define XD_EXTRA_SIZE 0x1054#define XD_2K_EXTRA_SIZE 0x4055 56#define NOT_WRITE_PROTECTED 0x8057#define READY_STATE 0x4058#define PROGRAM_ERROR 0x0159#define PROGRAM_ERROR_N_1 0x0260#define INTERNAL_READY 0x2061#define READY_FLAG 0x5F62 63#define XD_8M_X8_512 0xE664#define XD_16M_X8_512 0x7365#define XD_32M_X8_512 0x7566#define XD_64M_X8_512 0x7667#define XD_128M_X8_512 0x7968#define XD_256M_X8_512 0x7169#define XD_128M_X8_2048 0xF170#define XD_256M_X8_2048 0xDA71#define XD_512M_X8 0xDC72#define XD_128M_X16_2048 0xC173#define XD_4M_X8_512_1 0xE374#define XD_4M_X8_512_2 0xE575#define XD_1G_X8_512 0xD376#define XD_2G_X8_512 0xD577 78#define XD_ID_CODE 0xB579 80#define VENDOR_BLOCK 0xEFFF81#define CIS_BLOCK 0xDFFF82 83#define BLK_NOT_FOUND 0xFFFFFFFF84 85#define NO_NEW_BLK 0xFFFFFFFF86 87#define PAGE_CORRECTABLE 0x088#define PAGE_NOTCORRECTABLE 0x189 90#define NO_OFFSET 0x091#define WITH_OFFSET 0x192 93#define SECT_PER_PAGE 494#define XD_ADDR_MODE_2C XD_ADDR_MODE_2A95 96#define ZONE0_BAD_BLOCK 2397#define NOT_ZONE0_BAD_BLOCK 2498 99#define XD_RW_ADDR 0x01100#define XD_ERASE_ADDR 0x02101 102#define XD_PAGE_512(xd_card) \103do { \104 (xd_card)->block_shift = 5; \105 (xd_card)->page_off = 0x1F; \106} while (0)107 108#define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01)109#define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01)110#define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01)111 112#define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02)113#define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02)114#define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02)115 116#define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04)117#define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04)118#define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04)119 120#define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08)121#define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08)122#define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08)123 124#define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10)125#define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10)126#define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10)127 128#define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40)129#define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40)130#define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40)131 132#define PAGE_STATUS 0133#define BLOCK_STATUS 1134#define BLOCK_ADDR1_L 2135#define BLOCK_ADDR1_H 3136#define BLOCK_ADDR2_L 4137#define BLOCK_ADDR2_H 5138#define RESERVED0 6139#define RESERVED1 7140#define RESERVED2 8141#define RESERVED3 9142#define PARITY 10143 144#define CIS0_0 0145#define CIS0_1 1146#define CIS0_2 2147#define CIS0_3 3148#define CIS0_4 4149#define CIS0_5 5150#define CIS0_6 6151#define CIS0_7 7152#define CIS0_8 8153#define CIS0_9 9154#define CIS1_0 256155#define CIS1_1 (256 + 1)156#define CIS1_2 (256 + 2)157#define CIS1_3 (256 + 3)158#define CIS1_4 (256 + 4)159#define CIS1_5 (256 + 5)160#define CIS1_6 (256 + 6)161#define CIS1_7 (256 + 7)162#define CIS1_8 (256 + 8)163#define CIS1_9 (256 + 9)164 165int reset_xd_card(struct rtsx_chip *chip);166#ifdef XD_DELAY_WRITE167int xd_delay_write(struct rtsx_chip *chip);168#endif169int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,170 u32 start_sector, u16 sector_cnt);171void xd_free_l2p_tbl(struct rtsx_chip *chip);172void xd_cleanup_work(struct rtsx_chip *chip);173int xd_power_off_card3v3(struct rtsx_chip *chip);174int release_xd_card(struct rtsx_chip *chip);175 176#endif /* __REALTEK_RTSX_XD_H */177