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1# SPDX-License-Identifier: GPL-2.0-only2config INTEL_POWERCLAMP3 tristate "Intel PowerClamp idle injection driver"4 depends on X865 depends on CPU_SUP_INTEL6 depends on CPU_IDLE7 select POWERCAP8 select IDLE_INJECT9 help10 Enable this to enable Intel PowerClamp idle injection driver. This11 enforce idle time which results in more package C-state residency. The12 user interface is exposed via generic thermal framework.13 14config X86_THERMAL_VECTOR15 def_bool y16 depends on X86 && CPU_SUP_INTEL && X86_LOCAL_APIC17 18config INTEL_TCC19 bool20 depends on X8621 22config X86_PKG_TEMP_THERMAL23 tristate "X86 package temperature thermal driver"24 depends on X86_THERMAL_VECTOR25 select THERMAL_GOV_USER_SPACE26 select INTEL_TCC27 default m28 help29 Enable this to register CPU digital sensor for package temperature as30 thermal zone. Each package will have its own thermal zone. There are31 two trip points which can be set by user to get notifications via thermal32 notification methods.33 34config INTEL_SOC_DTS_IOSF_CORE35 tristate36 depends on X86 && PCI37 select IOSF_MBI38 select INTEL_TCC39 help40 This is becoming a common feature for Intel SoCs to expose the additional41 digital temperature sensors (DTSs) using side band interface (IOSF). This42 implements the common set of helper functions to register, get temperature43 and get/set thresholds on DTSs.44 45config INTEL_SOC_DTS_THERMAL46 tristate "Intel SoCs DTS thermal driver"47 depends on X86 && PCI && ACPI48 select INTEL_SOC_DTS_IOSF_CORE49 help50 Enable this to register Intel SoCs (e.g. Bay Trail) platform digital51 temperature sensor (DTS). These SoCs have two additional DTSs in52 addition to DTSs on CPU cores. Each DTS will be registered as a53 thermal zone. There are two trip points. One of the trip point can54 be set by user mode programs to get notifications via Linux thermal55 notification methods.The other trip is a critical trip point, which56 was set by the driver based on the TJ MAX temperature.57 58config INTEL_QUARK_DTS_THERMAL59 tristate "Intel Quark DTS thermal driver"60 depends on X86_INTEL_QUARK61 help62 Enable this to register Intel Quark SoC (e.g. X1000) platform digital63 temperature sensor (DTS). For X1000 SoC, it has one on-die DTS.64 The DTS will be registered as a thermal zone. There are two trip points:65 hot & critical. The critical trip point default value is set by66 underlying BIOS/Firmware.67 68menu "ACPI INT340X thermal drivers"69source "drivers/thermal/intel/int340x_thermal/Kconfig"70endmenu71 72config INTEL_BXT_PMIC_THERMAL73 tristate "Intel Broxton PMIC thermal driver"74 depends on X86 && INTEL_SOC_PMIC_BXTWC75 select REGMAP76 help77 Select this driver for Intel Broxton PMIC with ADC channels monitoring78 system temperature measurements and alerts.79 This driver is used for monitoring the ADC channels of PMIC and handles80 the alert trip point interrupts and notifies the thermal framework with81 the trip point and temperature details of the zone.82 83config INTEL_PCH_THERMAL84 tristate "Intel PCH Thermal Reporting Driver"85 depends on X86 && PCI86 select ACPI_THERMAL_LIB if ACPI87 help88 Enable this to support thermal reporting on certain intel PCHs.89 Thermal reporting device will provide temperature reading,90 programmable trip points and other information.91 92config INTEL_TCC_COOLING93 tristate "Intel TCC offset cooling Driver"94 depends on X8695 select INTEL_TCC96 help97 Enable this to support system cooling by adjusting the effective TCC98 activation temperature via the TCC Offset register, which is widely99 supported on modern Intel platforms.100 Note that, on different platforms, the behavior might be different101 on how fast the setting takes effect, and how much the CPU frequency102 is reduced.103 104config INTEL_HFI_THERMAL105 bool "Intel Hardware Feedback Interface"106 depends on NET107 depends on CPU_SUP_INTEL108 depends on X86_THERMAL_VECTOR109 select THERMAL_NETLINK110 help111 Select this option to enable the Hardware Feedback Interface. If112 selected, hardware provides guidance to the operating system on113 the performance and energy efficiency capabilities of each CPU.114 These capabilities may change as a result of changes in the operating115 conditions of the system such power and thermal limits. If selected,116 the kernel relays updates in CPUs' capabilities to userspace.117