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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.4 */5 6#ifndef __QCOM_TSENS_H__7#define __QCOM_TSENS_H__8 9#define NO_PT_CALIB 0x010#define ONE_PT_CALIB 0x111#define ONE_PT_CALIB2 0x212#define TWO_PT_CALIB 0x313#define ONE_PT_CALIB2_NO_OFFSET 0x614#define TWO_PT_CALIB_NO_OFFSET 0x715#define CAL_DEGC_PT1 3016#define CAL_DEGC_PT2 12017#define SLOPE_FACTOR 100018#define SLOPE_DEFAULT 320019#define TIMEOUT_US 10020#define THRESHOLD_MAX_ADC_CODE 0x3ff21#define THRESHOLD_MIN_ADC_CODE 0x022 23#define MAX_SENSORS 1624 25#include <linux/interrupt.h>26#include <linux/thermal.h>27#include <linux/regmap.h>28#include <linux/slab.h>29 30struct tsens_priv;31 32/* IP version numbers in ascending order */33enum tsens_ver {34 VER_0 = 0,35 VER_0_1,36 VER_1_X,37 VER_2_X,38};39 40enum tsens_irq_type {41 LOWER,42 UPPER,43 CRITICAL,44};45 46/**47 * struct tsens_sensor - data for each sensor connected to the tsens device48 * @priv: tsens device instance that this sensor is connected to49 * @tzd: pointer to the thermal zone that this sensor is in50 * @offset: offset of temperature adjustment curve51 * @hw_id: HW ID can be used in case of platform-specific IDs52 * @slope: slope of temperature adjustment curve53 * @status: 8960-specific variable to track 8960 and 8660 status register offset54 */55struct tsens_sensor {56 struct tsens_priv *priv;57 struct thermal_zone_device *tzd;58 int offset;59 unsigned int hw_id;60 int slope;61 u32 status;62 int p1_calib_offset;63 int p2_calib_offset;64};65 66/**67 * struct tsens_ops - operations as supported by the tsens device68 * @init: Function to initialize the tsens device69 * @calibrate: Function to calibrate the tsens device70 * @get_temp: Function which returns the temp in millidegC71 * @enable: Function to enable (clocks/power) tsens device72 * @disable: Function to disable the tsens device73 * @suspend: Function to suspend the tsens device74 * @resume: Function to resume the tsens device75 */76struct tsens_ops {77 /* mandatory callbacks */78 int (*init)(struct tsens_priv *priv);79 int (*calibrate)(struct tsens_priv *priv);80 int (*get_temp)(const struct tsens_sensor *s, int *temp);81 /* optional callbacks */82 int (*enable)(struct tsens_priv *priv, int i);83 void (*disable)(struct tsens_priv *priv);84 int (*suspend)(struct tsens_priv *priv);85 int (*resume)(struct tsens_priv *priv);86};87 88#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \89 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \90 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \91 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \92 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \93 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \94 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \95 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \96 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \97 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \98 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \99 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)100 101#define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \102 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \103 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \104 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \105 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \106 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \107 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \108 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \109 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \110 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \111 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \112 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \113 [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \114 [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \115 [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \116 [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \117 [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)118 119#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \120 [_name##_##0] = REG_FIELD(_offset, 0, 0), \121 [_name##_##1] = REG_FIELD(_offset, 1, 1), \122 [_name##_##2] = REG_FIELD(_offset, 2, 2), \123 [_name##_##3] = REG_FIELD(_offset, 3, 3), \124 [_name##_##4] = REG_FIELD(_offset, 4, 4), \125 [_name##_##5] = REG_FIELD(_offset, 5, 5), \126 [_name##_##6] = REG_FIELD(_offset, 6, 6), \127 [_name##_##7] = REG_FIELD(_offset, 7, 7), \128 [_name##_##8] = REG_FIELD(_offset, 8, 8), \129 [_name##_##9] = REG_FIELD(_offset, 9, 9), \130 [_name##_##10] = REG_FIELD(_offset, 10, 10), \131 [_name##_##11] = REG_FIELD(_offset, 11, 11), \132 [_name##_##12] = REG_FIELD(_offset, 12, 12), \133 [_name##_##13] = REG_FIELD(_offset, 13, 13), \134 [_name##_##14] = REG_FIELD(_offset, 14, 14), \135 [_name##_##15] = REG_FIELD(_offset, 15, 15)136 137#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \138 [_name##_##0] = REG_FIELD(_offset, 16, 16), \139 [_name##_##1] = REG_FIELD(_offset, 17, 17), \140 [_name##_##2] = REG_FIELD(_offset, 18, 18), \141 [_name##_##3] = REG_FIELD(_offset, 19, 19), \142 [_name##_##4] = REG_FIELD(_offset, 20, 20), \143 [_name##_##5] = REG_FIELD(_offset, 21, 21), \144 [_name##_##6] = REG_FIELD(_offset, 22, 22), \145 [_name##_##7] = REG_FIELD(_offset, 23, 23), \146 [_name##_##8] = REG_FIELD(_offset, 24, 24), \147 [_name##_##9] = REG_FIELD(_offset, 25, 25), \148 [_name##_##10] = REG_FIELD(_offset, 26, 26), \149 [_name##_##11] = REG_FIELD(_offset, 27, 27), \150 [_name##_##12] = REG_FIELD(_offset, 28, 28), \151 [_name##_##13] = REG_FIELD(_offset, 29, 29), \152 [_name##_##14] = REG_FIELD(_offset, 30, 30), \153 [_name##_##15] = REG_FIELD(_offset, 31, 31)154 155/*156 * reg_field IDs to use as an index into an array157 * If you change the order of the entries, check the devm_regmap_field_alloc()158 * calls in init_common()159 */160enum regfield_ids {161 /* ----- SROT ------ */162 /* HW_VER */163 VER_MAJOR,164 VER_MINOR,165 VER_STEP,166 /* CTRL_OFFSET */167 TSENS_EN,168 TSENS_SW_RST,169 SENSOR_EN,170 CODE_OR_TEMP,171 172 /* ----- TM ------ */173 /* TRDY */174 TRDY,175 /* INTERRUPT ENABLE */176 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */177 /* STATUS */178 LAST_TEMP_0, /* Last temperature reading */179 LAST_TEMP_1,180 LAST_TEMP_2,181 LAST_TEMP_3,182 LAST_TEMP_4,183 LAST_TEMP_5,184 LAST_TEMP_6,185 LAST_TEMP_7,186 LAST_TEMP_8,187 LAST_TEMP_9,188 LAST_TEMP_10,189 LAST_TEMP_11,190 LAST_TEMP_12,191 LAST_TEMP_13,192 LAST_TEMP_14,193 LAST_TEMP_15,194 VALID_0, /* VALID reading or not */195 VALID_1,196 VALID_2,197 VALID_3,198 VALID_4,199 VALID_5,200 VALID_6,201 VALID_7,202 VALID_8,203 VALID_9,204 VALID_10,205 VALID_11,206 VALID_12,207 VALID_13,208 VALID_14,209 VALID_15,210 LOWER_STATUS_0, /* LOWER threshold violated */211 LOWER_STATUS_1,212 LOWER_STATUS_2,213 LOWER_STATUS_3,214 LOWER_STATUS_4,215 LOWER_STATUS_5,216 LOWER_STATUS_6,217 LOWER_STATUS_7,218 LOWER_STATUS_8,219 LOWER_STATUS_9,220 LOWER_STATUS_10,221 LOWER_STATUS_11,222 LOWER_STATUS_12,223 LOWER_STATUS_13,224 LOWER_STATUS_14,225 LOWER_STATUS_15,226 LOW_INT_STATUS_0, /* LOWER interrupt status */227 LOW_INT_STATUS_1,228 LOW_INT_STATUS_2,229 LOW_INT_STATUS_3,230 LOW_INT_STATUS_4,231 LOW_INT_STATUS_5,232 LOW_INT_STATUS_6,233 LOW_INT_STATUS_7,234 LOW_INT_STATUS_8,235 LOW_INT_STATUS_9,236 LOW_INT_STATUS_10,237 LOW_INT_STATUS_11,238 LOW_INT_STATUS_12,239 LOW_INT_STATUS_13,240 LOW_INT_STATUS_14,241 LOW_INT_STATUS_15,242 LOW_INT_CLEAR_0, /* LOWER interrupt clear */243 LOW_INT_CLEAR_1,244 LOW_INT_CLEAR_2,245 LOW_INT_CLEAR_3,246 LOW_INT_CLEAR_4,247 LOW_INT_CLEAR_5,248 LOW_INT_CLEAR_6,249 LOW_INT_CLEAR_7,250 LOW_INT_CLEAR_8,251 LOW_INT_CLEAR_9,252 LOW_INT_CLEAR_10,253 LOW_INT_CLEAR_11,254 LOW_INT_CLEAR_12,255 LOW_INT_CLEAR_13,256 LOW_INT_CLEAR_14,257 LOW_INT_CLEAR_15,258 LOW_INT_MASK_0, /* LOWER interrupt mask */259 LOW_INT_MASK_1,260 LOW_INT_MASK_2,261 LOW_INT_MASK_3,262 LOW_INT_MASK_4,263 LOW_INT_MASK_5,264 LOW_INT_MASK_6,265 LOW_INT_MASK_7,266 LOW_INT_MASK_8,267 LOW_INT_MASK_9,268 LOW_INT_MASK_10,269 LOW_INT_MASK_11,270 LOW_INT_MASK_12,271 LOW_INT_MASK_13,272 LOW_INT_MASK_14,273 LOW_INT_MASK_15,274 LOW_THRESH_0, /* LOWER threshold values */275 LOW_THRESH_1,276 LOW_THRESH_2,277 LOW_THRESH_3,278 LOW_THRESH_4,279 LOW_THRESH_5,280 LOW_THRESH_6,281 LOW_THRESH_7,282 LOW_THRESH_8,283 LOW_THRESH_9,284 LOW_THRESH_10,285 LOW_THRESH_11,286 LOW_THRESH_12,287 LOW_THRESH_13,288 LOW_THRESH_14,289 LOW_THRESH_15,290 UPPER_STATUS_0, /* UPPER threshold violated */291 UPPER_STATUS_1,292 UPPER_STATUS_2,293 UPPER_STATUS_3,294 UPPER_STATUS_4,295 UPPER_STATUS_5,296 UPPER_STATUS_6,297 UPPER_STATUS_7,298 UPPER_STATUS_8,299 UPPER_STATUS_9,300 UPPER_STATUS_10,301 UPPER_STATUS_11,302 UPPER_STATUS_12,303 UPPER_STATUS_13,304 UPPER_STATUS_14,305 UPPER_STATUS_15,306 UP_INT_STATUS_0, /* UPPER interrupt status */307 UP_INT_STATUS_1,308 UP_INT_STATUS_2,309 UP_INT_STATUS_3,310 UP_INT_STATUS_4,311 UP_INT_STATUS_5,312 UP_INT_STATUS_6,313 UP_INT_STATUS_7,314 UP_INT_STATUS_8,315 UP_INT_STATUS_9,316 UP_INT_STATUS_10,317 UP_INT_STATUS_11,318 UP_INT_STATUS_12,319 UP_INT_STATUS_13,320 UP_INT_STATUS_14,321 UP_INT_STATUS_15,322 UP_INT_CLEAR_0, /* UPPER interrupt clear */323 UP_INT_CLEAR_1,324 UP_INT_CLEAR_2,325 UP_INT_CLEAR_3,326 UP_INT_CLEAR_4,327 UP_INT_CLEAR_5,328 UP_INT_CLEAR_6,329 UP_INT_CLEAR_7,330 UP_INT_CLEAR_8,331 UP_INT_CLEAR_9,332 UP_INT_CLEAR_10,333 UP_INT_CLEAR_11,334 UP_INT_CLEAR_12,335 UP_INT_CLEAR_13,336 UP_INT_CLEAR_14,337 UP_INT_CLEAR_15,338 UP_INT_MASK_0, /* UPPER interrupt mask */339 UP_INT_MASK_1,340 UP_INT_MASK_2,341 UP_INT_MASK_3,342 UP_INT_MASK_4,343 UP_INT_MASK_5,344 UP_INT_MASK_6,345 UP_INT_MASK_7,346 UP_INT_MASK_8,347 UP_INT_MASK_9,348 UP_INT_MASK_10,349 UP_INT_MASK_11,350 UP_INT_MASK_12,351 UP_INT_MASK_13,352 UP_INT_MASK_14,353 UP_INT_MASK_15,354 UP_THRESH_0, /* UPPER threshold values */355 UP_THRESH_1,356 UP_THRESH_2,357 UP_THRESH_3,358 UP_THRESH_4,359 UP_THRESH_5,360 UP_THRESH_6,361 UP_THRESH_7,362 UP_THRESH_8,363 UP_THRESH_9,364 UP_THRESH_10,365 UP_THRESH_11,366 UP_THRESH_12,367 UP_THRESH_13,368 UP_THRESH_14,369 UP_THRESH_15,370 CRITICAL_STATUS_0, /* CRITICAL threshold violated */371 CRITICAL_STATUS_1,372 CRITICAL_STATUS_2,373 CRITICAL_STATUS_3,374 CRITICAL_STATUS_4,375 CRITICAL_STATUS_5,376 CRITICAL_STATUS_6,377 CRITICAL_STATUS_7,378 CRITICAL_STATUS_8,379 CRITICAL_STATUS_9,380 CRITICAL_STATUS_10,381 CRITICAL_STATUS_11,382 CRITICAL_STATUS_12,383 CRITICAL_STATUS_13,384 CRITICAL_STATUS_14,385 CRITICAL_STATUS_15,386 CRIT_INT_STATUS_0, /* CRITICAL interrupt status */387 CRIT_INT_STATUS_1,388 CRIT_INT_STATUS_2,389 CRIT_INT_STATUS_3,390 CRIT_INT_STATUS_4,391 CRIT_INT_STATUS_5,392 CRIT_INT_STATUS_6,393 CRIT_INT_STATUS_7,394 CRIT_INT_STATUS_8,395 CRIT_INT_STATUS_9,396 CRIT_INT_STATUS_10,397 CRIT_INT_STATUS_11,398 CRIT_INT_STATUS_12,399 CRIT_INT_STATUS_13,400 CRIT_INT_STATUS_14,401 CRIT_INT_STATUS_15,402 CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */403 CRIT_INT_CLEAR_1,404 CRIT_INT_CLEAR_2,405 CRIT_INT_CLEAR_3,406 CRIT_INT_CLEAR_4,407 CRIT_INT_CLEAR_5,408 CRIT_INT_CLEAR_6,409 CRIT_INT_CLEAR_7,410 CRIT_INT_CLEAR_8,411 CRIT_INT_CLEAR_9,412 CRIT_INT_CLEAR_10,413 CRIT_INT_CLEAR_11,414 CRIT_INT_CLEAR_12,415 CRIT_INT_CLEAR_13,416 CRIT_INT_CLEAR_14,417 CRIT_INT_CLEAR_15,418 CRIT_INT_MASK_0, /* CRITICAL interrupt mask */419 CRIT_INT_MASK_1,420 CRIT_INT_MASK_2,421 CRIT_INT_MASK_3,422 CRIT_INT_MASK_4,423 CRIT_INT_MASK_5,424 CRIT_INT_MASK_6,425 CRIT_INT_MASK_7,426 CRIT_INT_MASK_8,427 CRIT_INT_MASK_9,428 CRIT_INT_MASK_10,429 CRIT_INT_MASK_11,430 CRIT_INT_MASK_12,431 CRIT_INT_MASK_13,432 CRIT_INT_MASK_14,433 CRIT_INT_MASK_15,434 CRIT_THRESH_0, /* CRITICAL threshold values */435 CRIT_THRESH_1,436 CRIT_THRESH_2,437 CRIT_THRESH_3,438 CRIT_THRESH_4,439 CRIT_THRESH_5,440 CRIT_THRESH_6,441 CRIT_THRESH_7,442 CRIT_THRESH_8,443 CRIT_THRESH_9,444 CRIT_THRESH_10,445 CRIT_THRESH_11,446 CRIT_THRESH_12,447 CRIT_THRESH_13,448 CRIT_THRESH_14,449 CRIT_THRESH_15,450 451 /* WATCHDOG */452 WDOG_BARK_STATUS,453 WDOG_BARK_CLEAR,454 WDOG_BARK_MASK,455 WDOG_BARK_COUNT,456 457 /* CYCLE COMPLETION MONITOR */458 CC_MON_STATUS,459 CC_MON_CLEAR,460 CC_MON_MASK,461 462 MIN_STATUS_0, /* MIN threshold violated */463 MIN_STATUS_1,464 MIN_STATUS_2,465 MIN_STATUS_3,466 MIN_STATUS_4,467 MIN_STATUS_5,468 MIN_STATUS_6,469 MIN_STATUS_7,470 MIN_STATUS_8,471 MIN_STATUS_9,472 MIN_STATUS_10,473 MIN_STATUS_11,474 MIN_STATUS_12,475 MIN_STATUS_13,476 MIN_STATUS_14,477 MIN_STATUS_15,478 MAX_STATUS_0, /* MAX threshold violated */479 MAX_STATUS_1,480 MAX_STATUS_2,481 MAX_STATUS_3,482 MAX_STATUS_4,483 MAX_STATUS_5,484 MAX_STATUS_6,485 MAX_STATUS_7,486 MAX_STATUS_8,487 MAX_STATUS_9,488 MAX_STATUS_10,489 MAX_STATUS_11,490 MAX_STATUS_12,491 MAX_STATUS_13,492 MAX_STATUS_14,493 MAX_STATUS_15,494 495 /* Keep last */496 MAX_REGFIELDS497};498 499/**500 * struct tsens_features - Features supported by the IP501 * @ver_major: Major number of IP version502 * @crit_int: does the IP support critical interrupts?503 * @combo_int: does the IP use one IRQ for up, low and critical thresholds?504 * @adc: do the sensors only output adc code (instead of temperature)?505 * @srot_split: does the IP neatly splits the register space into SROT and TM,506 * with SROT only being available to secure boot firmware?507 * @has_watchdog: does this IP support watchdog functionality?508 * @max_sensors: maximum sensors supported by this version of the IP509 * @trip_min_temp: minimum trip temperature supported by this version of the IP510 * @trip_max_temp: maximum trip temperature supported by this version of the IP511 */512struct tsens_features {513 unsigned int ver_major;514 unsigned int crit_int:1;515 unsigned int combo_int:1;516 unsigned int adc:1;517 unsigned int srot_split:1;518 unsigned int has_watchdog:1;519 unsigned int max_sensors;520 int trip_min_temp;521 int trip_max_temp;522};523 524/**525 * struct tsens_plat_data - tsens compile-time platform data526 * @num_sensors: Number of sensors supported by platform527 * @ops: operations the tsens instance supports528 * @hw_ids: Subset of sensors ids supported by platform, if not the first n529 * @feat: features of the IP530 * @fields: bitfield locations531 */532struct tsens_plat_data {533 const u32 num_sensors;534 const struct tsens_ops *ops;535 unsigned int *hw_ids;536 struct tsens_features *feat;537 const struct reg_field *fields;538};539 540/**541 * struct tsens_context - Registers to be saved/restored across a context loss542 * @threshold: Threshold register value543 * @control: Control register value544 */545struct tsens_context {546 int threshold;547 int control;548};549 550/**551 * struct tsens_priv - private data for each instance of the tsens IP552 * @dev: pointer to struct device553 * @num_sensors: number of sensors enabled on this device554 * @tm_map: pointer to TM register address space555 * @srot_map: pointer to SROT register address space556 * @tm_offset: deal with old device trees that don't address TM and SROT557 * address space separately558 * @ul_lock: lock while processing upper/lower threshold interrupts559 * @crit_lock: lock while processing critical threshold interrupts560 * @rf: array of regmap_fields used to store value of the field561 * @ctx: registers to be saved and restored during suspend/resume562 * @feat: features of the IP563 * @fields: bitfield locations564 * @ops: pointer to list of callbacks supported by this device565 * @debug_root: pointer to debugfs dentry for all tsens566 * @debug: pointer to debugfs dentry for tsens controller567 * @sensor: list of sensors attached to this device568 */569struct tsens_priv {570 struct device *dev;571 u32 num_sensors;572 struct regmap *tm_map;573 struct regmap *srot_map;574 u32 tm_offset;575 576 /* lock for upper/lower threshold interrupts */577 spinlock_t ul_lock;578 579 struct regmap_field *rf[MAX_REGFIELDS];580 struct tsens_context ctx;581 struct tsens_features *feat;582 const struct reg_field *fields;583 const struct tsens_ops *ops;584 585 struct dentry *debug_root;586 struct dentry *debug;587 588 struct tsens_sensor sensor[] __counted_by(num_sensors);589};590 591/**592 * struct tsens_single_value - internal representation of a single field inside nvmem calibration data593 * @idx: index into the u32 data array594 * @shift: the shift of the first bit in the value595 * @blob: index of the data blob to use for this cell596 */597struct tsens_single_value {598 u8 idx;599 u8 shift;600 u8 blob;601};602 603/**604 * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob605 * @base_len: the length of the base fields inside calibration data606 * @base_shift: the shift to be applied to base data607 * @sp_len: the length of the sN_pM fields inside calibration data608 * @mode: descriptor of the calibration mode field609 * @invalid: descriptor of the calibration mode invalid field610 * @base: descriptors of the base0 and base1 fields611 * @sp: descriptors of the sN_pM fields612 */613struct tsens_legacy_calibration_format {614 unsigned int base_len;615 unsigned int base_shift;616 unsigned int sp_len;617 /* just two bits */618 struct tsens_single_value mode;619 /* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */620 struct tsens_single_value invalid;621 struct tsens_single_value base[2];622 struct tsens_single_value sp[][2];623};624 625char *qfprom_read(struct device *dev, const char *cname);626int tsens_read_calibration_legacy(struct tsens_priv *priv,627 const struct tsens_legacy_calibration_format *format,628 u32 *p1, u32 *p2,629 u32 *cdata, u32 *csel);630int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup);631int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift);632int tsens_calibrate_common(struct tsens_priv *priv);633void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);634int init_common(struct tsens_priv *priv);635int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);636int get_temp_common(const struct tsens_sensor *s, int *temp);637#ifdef CONFIG_SUSPEND638int tsens_resume_common(struct tsens_priv *priv);639#else640#define tsens_resume_common NULL641#endif642 643/* TSENS target */644extern struct tsens_plat_data data_8960;645 646/* TSENS v0.1 targets */647extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;648 649/* TSENS v1 targets */650extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;651 652/* TSENS v2 targets */653extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;654 655#endif /* __QCOM_TSENS_H__ */656