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1// SPDX-License-Identifier: GPL-2.02/*3 * Tegra30 SoC Thermal Sensor driver4 *5 * Based on downstream HWMON driver from NVIDIA.6 * Copyright (C) 2011 NVIDIA Corporation7 *8 * Author: Dmitry Osipenko <digetx@gmail.com>9 * Copyright (C) 2021 GRATE-DRIVER project10 */11 12#include <linux/bitfield.h>13#include <linux/clk.h>14#include <linux/delay.h>15#include <linux/errno.h>16#include <linux/interrupt.h>17#include <linux/io.h>18#include <linux/iopoll.h>19#include <linux/math.h>20#include <linux/module.h>21#include <linux/of.h>22#include <linux/platform_device.h>23#include <linux/pm.h>24#include <linux/reset.h>25#include <linux/slab.h>26#include <linux/thermal.h>27#include <linux/types.h>28 29#include <soc/tegra/fuse.h>30 31#include "../thermal_hwmon.h"32 33#define TSENSOR_SENSOR0_CONFIG0 0x034#define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0)35#define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1)36#define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2)37#define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3)38#define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4)39#define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5)40#define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6)41#define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8)42#define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24)43 44#define TSENSOR_SENSOR0_CONFIG1 0x845#define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0)46#define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16)47 48#define TSENSOR_SENSOR0_CONFIG2 0xc49#define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0)50 51#define TSENSOR_SENSOR0_STATUS0 0x1852#define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0)53#define TSENSOR_SENSOR0_STATUS0_INTR BIT(8)54#define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9)55 56#define TSENSOR_SENSOR0_TS_STATUS1 0x1c57#define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16)58 59#define TEGRA30_FUSE_TEST_PROG_VER 0x2860 61#define TEGRA30_FUSE_TSENSOR_CALIB 0x9862#define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0)63#define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16)64 65#define TEGRA30_FUSE_SPARE_BIT 0x14466 67struct tegra_tsensor;68 69struct tegra_tsensor_calibration_data {70 int a, b, m, n, p, r;71};72 73struct tegra_tsensor_channel {74 void __iomem *regs;75 unsigned int id;76 struct tegra_tsensor *ts;77 struct thermal_zone_device *tzd;78};79 80struct tegra_tsensor {81 void __iomem *regs;82 bool swap_channels;83 struct clk *clk;84 struct device *dev;85 struct reset_control *rst;86 struct tegra_tsensor_channel ch[2];87 struct tegra_tsensor_calibration_data calib;88};89 90static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts)91{92 u32 val;93 int err;94 95 err = reset_control_assert(ts->rst);96 if (err) {97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);98 return err;99 }100 101 err = clk_prepare_enable(ts->clk);102 if (err) {103 dev_err(ts->dev, "failed to enable clock: %d\n", err);104 return err;105 }106 107 fsleep(1000);108 109 err = reset_control_deassert(ts->rst);110 if (err) {111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err);112 goto disable_clk;113 }114 115 /*116 * Sensors are enabled after reset by default, but not gauging117 * until clock counter is programmed.118 *119 * M: number of reference clock pulses after which every120 * temperature / voltage measurement is made121 *122 * N: number of reference clock counts for which the counter runs123 */124 val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500);125 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255);126 127 /* apply the same configuration to both channels */128 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);129 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);130 131 return 0;132 133disable_clk:134 clk_disable_unprepare(ts->clk);135 136 return err;137}138 139static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts)140{141 int err;142 143 err = reset_control_assert(ts->rst);144 if (err) {145 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);146 return err;147 }148 149 clk_disable_unprepare(ts->clk);150 151 return 0;152}153 154static void devm_tegra_tsensor_hw_disable(void *data)155{156 const struct tegra_tsensor *ts = data;157 158 tegra_tsensor_hw_disable(ts);159}160 161static int tegra_tsensor_get_temp(struct thermal_zone_device *tz, int *temp)162{163 const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz);164 const struct tegra_tsensor *ts = tsc->ts;165 int err, c1, c2, c3, c4, counter;166 u32 val;167 168 /*169 * Counter will be invalid if hardware is misprogrammed or not enough170 * time passed since the time when sensor was enabled.171 */172 err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,173 val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID,174 21 * USEC_PER_MSEC,175 21 * USEC_PER_MSEC * 50);176 if (err) {177 dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id);178 return err;179 }180 181 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1);182 counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val);183 184 /*185 * This shouldn't happen with a valid counter status, nevertheless186 * lets verify the value since it's in a separate (from status)187 * register.188 */189 if (counter == 0xffff) {190 dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id);191 return -EINVAL;192 }193 194 /*195 * temperature = a * counter + b196 * temperature = m * (temperature ^ 2) + n * temperature + p197 */198 c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000);199 c1 = c1 ?: 1;200 c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1);201 c3 = c1 * ts->calib.m;202 c4 = ts->calib.n;203 204 *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000);205 206 return 0;207}208 209static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp)210{211 int c1, c2;212 213 c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m);214 c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1);215 216 return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a);217}218 219static int tegra_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high)220{221 const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz);222 const struct tegra_tsensor *ts = tsc->ts;223 u32 val;224 225 /*226 * TSENSOR doesn't trigger interrupt on the "low" temperature breach,227 * hence bail out if high temperature is unspecified.228 */229 if (high == INT_MAX)230 return 0;231 232 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);233 val &= ~TSENSOR_SENSOR0_CONFIG1_TH1;234 235 high = tegra_tsensor_temp_to_counter(ts, high);236 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high);237 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);238 239 return 0;240}241 242static const struct thermal_zone_device_ops ops = {243 .get_temp = tegra_tsensor_get_temp,244 .set_trips = tegra_tsensor_set_trips,245};246 247static bool248tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts,249 unsigned int id)250{251 const struct tegra_tsensor_channel *tsc = &ts->ch[id];252 u32 val;253 254 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0);255 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);256 257 if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5)258 dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id);259 260 if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val))261 return false;262 263 thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED);264 265 return true;266}267 268static irqreturn_t tegra_tsensor_isr(int irq, void *data)269{270 const struct tegra_tsensor *ts = data;271 bool handled = false;272 unsigned int i;273 274 for (i = 0; i < ARRAY_SIZE(ts->ch); i++)275 handled |= tegra_tsensor_handle_channel_interrupt(ts, i);276 277 return handled ? IRQ_HANDLED : IRQ_NONE;278}279 280static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts,281 unsigned int id)282{283 const struct tegra_tsensor_channel *tsc = &ts->ch[id];284 struct thermal_zone_device *tzd = tsc->tzd;285 u32 val;286 int err;287 288 if (!tzd)289 goto stop_channel;290 291 err = thermal_zone_device_disable(tzd);292 if (err) {293 dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err);294 return err;295 }296 297stop_channel:298 /* stop channel gracefully */299 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);300 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1);301 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);302 303 return 0;304}305 306struct trip_temps {307 int hot_trip;308 int crit_trip;309};310 311static int tegra_tsensor_get_trips_cb(struct thermal_trip *trip, void *arg)312{313 struct trip_temps *temps = arg;314 315 if (trip->type == THERMAL_TRIP_HOT)316 temps->hot_trip = trip->temperature;317 else if (trip->type == THERMAL_TRIP_CRITICAL)318 temps->crit_trip = trip->temperature;319 320 return 0;321}322 323static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd,324 struct trip_temps *temps)325{326 /*327 * 90C is the maximal critical temperature of all Tegra30 SoC variants,328 * use it for the default trip if unspecified in a device-tree.329 */330 temps->hot_trip = 85000;331 temps->crit_trip = 90000;332 333 thermal_zone_for_each_trip(tzd, tegra_tsensor_get_trips_cb, temps);334 335 /* clamp hardware trips to the calibration limits */336 temps->hot_trip = clamp(temps->hot_trip, 25000, 90000);337 338 /*339 * Kernel will perform a normal system shut down if it will340 * see that critical temperature is breached, hence set the341 * hardware limit by 5C higher in order to allow system to342 * shut down gracefully before sending signal to the Power343 * Management controller.344 */345 temps->crit_trip = clamp(temps->crit_trip + 5000, 25000, 90000);346}347 348static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts,349 unsigned int id)350{351 const struct tegra_tsensor_channel *tsc = &ts->ch[id];352 struct thermal_zone_device *tzd = tsc->tzd;353 struct trip_temps temps = { 0 };354 int err;355 u32 val;356 357 if (!tzd) {358 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);359 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;360 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);361 362 return 0;363 }364 365 tegra_tsensor_get_hw_channel_trips(tzd, &temps);366 367 dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n",368 id, DIV_ROUND_CLOSEST(temps.crit_trip, 1000));369 370 temps.hot_trip = tegra_tsensor_temp_to_counter(ts, temps.hot_trip);371 temps.crit_trip = tegra_tsensor_temp_to_counter(ts, temps.crit_trip);372 373 /* program LEVEL2 counter threshold */374 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);375 val &= ~TSENSOR_SENSOR0_CONFIG1_TH2;376 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, temps.hot_trip);377 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);378 379 /* program LEVEL3 counter threshold */380 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2);381 val &= ~TSENSOR_SENSOR0_CONFIG2_TH3;382 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, temps.crit_trip);383 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);384 385 /*386 * Enable sensor, emergency shutdown, interrupts for level 1/2/3387 * breaches and counter overflow condition.388 *389 * Disable DIV2 throttle for now since we need to figure out how390 * to integrate it properly with the thermal framework.391 *392 * Thermal levels supported by hardware:393 *394 * Level 0 = cold395 * Level 1 = passive cooling (cpufreq DVFS)396 * Level 2 = passive cooling assisted by hardware (DIV2)397 * Level 3 = emergency shutdown assisted by hardware (PMC)398 */399 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);400 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;401 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1);402 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0);403 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1);404 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1);405 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1);406 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1);407 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);408 409 err = thermal_zone_device_enable(tzd);410 if (err) {411 dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err);412 return err;413 }414 415 return 0;416}417 418static bool tegra_tsensor_fuse_read_spare(unsigned int spare)419{420 u32 val = 0;421 422 tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val);423 424 return !!val;425}426 427static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts)428{429 u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0;430 int err, c1_25C, c2_90C;431 432 err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver);433 if (err) {434 dev_err_probe(ts->dev, err, "failed to get ATE version\n");435 return err;436 }437 438 if (ate_ver < 8) {439 dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver);440 return -ENODEV;441 }442 443 /*444 * We have two TSENSOR channels in a two different spots on SoC.445 * Second channel provides more accurate data on older SoC versions,446 * use it as a primary channel.447 */448 if (ate_ver <= 21) {449 dev_info_once(ts->dev,450 "older ATE version detected, channels remapped\n");451 ts->swap_channels = true;452 }453 454 err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal);455 if (err) {456 dev_err(ts->dev, "failed to get calibration data: %d\n", err);457 return err;458 }459 460 /* get calibrated counter values for 25C/90C thresholds */461 c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal);462 c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal);463 464 /* and calibrated temperatures corresponding to the counter values */465 for (i = 0; i < 7; i++) {466 t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i;467 t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i;468 469 t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i;470 t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i;471 }472 473 if (c2_90C - c1_25C <= t2_90C - t1_25C) {474 dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n",475 c2_90C, c1_25C, t2_90C, t1_25C);476 return -EINVAL;477 }478 479 /* all calibration coefficients are premultiplied by 1000000 */480 481 ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000,482 (c2_90C - c1_25C));483 484 ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C;485 486 if (tegra_sku_info.revision == TEGRA_REVISION_A01) {487 ts->calib.m = -2775;488 ts->calib.n = 1338811;489 ts->calib.p = -7300000;490 } else {491 ts->calib.m = -3512;492 ts->calib.n = 1528943;493 ts->calib.p = -11100000;494 }495 496 /* except the coefficient of a reduced quadratic equation */497 ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2);498 499 dev_info_once(ts->dev,500 "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n",501 c2_90C, c1_25C, t2_90C, t1_25C, ate_ver,502 tegra_sku_info.revision);503 504 return 0;505}506 507static int tegra_tsensor_register_channel(struct tegra_tsensor *ts,508 unsigned int id)509{510 struct tegra_tsensor_channel *tsc = &ts->ch[id];511 unsigned int hw_id = ts->swap_channels ? !id : id;512 513 tsc->ts = ts;514 tsc->id = id;515 tsc->regs = ts->regs + 0x40 * (hw_id + 1);516 517 tsc->tzd = devm_thermal_of_zone_register(ts->dev, id, tsc, &ops);518 if (IS_ERR(tsc->tzd)) {519 if (PTR_ERR(tsc->tzd) != -ENODEV)520 return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd),521 "failed to register thermal zone\n");522 523 /*524 * It's okay if sensor isn't assigned to any thermal zone525 * in a device-tree.526 */527 tsc->tzd = NULL;528 return 0;529 }530 531 devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd);532 533 return 0;534}535 536static int tegra_tsensor_probe(struct platform_device *pdev)537{538 struct tegra_tsensor *ts;539 unsigned int i;540 int err, irq;541 542 ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL);543 if (!ts)544 return -ENOMEM;545 546 irq = platform_get_irq(pdev, 0);547 if (irq < 0)548 return irq;549 550 ts->dev = &pdev->dev;551 platform_set_drvdata(pdev, ts);552 553 ts->regs = devm_platform_ioremap_resource(pdev, 0);554 if (IS_ERR(ts->regs))555 return PTR_ERR(ts->regs);556 557 ts->clk = devm_clk_get(&pdev->dev, NULL);558 if (IS_ERR(ts->clk))559 return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk),560 "failed to get clock\n");561 562 ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);563 if (IS_ERR(ts->rst))564 return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst),565 "failed to get reset control\n");566 567 err = tegra_tsensor_nvmem_setup(ts);568 if (err)569 return err;570 571 err = tegra_tsensor_hw_enable(ts);572 if (err)573 return err;574 575 err = devm_add_action_or_reset(&pdev->dev,576 devm_tegra_tsensor_hw_disable,577 ts);578 if (err)579 return err;580 581 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {582 err = tegra_tsensor_register_channel(ts, i);583 if (err)584 return err;585 }586 587 /*588 * Enable the channels before setting the interrupt so589 * set_trips() can not be called while we are setting up the590 * register TSENSOR_SENSOR0_CONFIG1. With this we close a591 * potential race window where we are setting up the TH2 and592 * the temperature hits TH1 resulting to an update of the593 * TSENSOR_SENSOR0_CONFIG1 register in the ISR.594 */595 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {596 err = tegra_tsensor_enable_hw_channel(ts, i);597 if (err)598 return err;599 }600 601 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,602 tegra_tsensor_isr, IRQF_ONESHOT,603 "tegra_tsensor", ts);604 if (err)605 return dev_err_probe(&pdev->dev, err,606 "failed to request interrupt\n");607 608 return 0;609}610 611static int __maybe_unused tegra_tsensor_suspend(struct device *dev)612{613 struct tegra_tsensor *ts = dev_get_drvdata(dev);614 unsigned int i;615 int err;616 617 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {618 err = tegra_tsensor_disable_hw_channel(ts, i);619 if (err)620 goto enable_channel;621 }622 623 err = tegra_tsensor_hw_disable(ts);624 if (err)625 goto enable_channel;626 627 return 0;628 629enable_channel:630 while (i--)631 tegra_tsensor_enable_hw_channel(ts, i);632 633 return err;634}635 636static int __maybe_unused tegra_tsensor_resume(struct device *dev)637{638 struct tegra_tsensor *ts = dev_get_drvdata(dev);639 unsigned int i;640 int err;641 642 err = tegra_tsensor_hw_enable(ts);643 if (err)644 return err;645 646 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {647 err = tegra_tsensor_enable_hw_channel(ts, i);648 if (err)649 return err;650 }651 652 return 0;653}654 655static const struct dev_pm_ops tegra_tsensor_pm_ops = {656 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend,657 tegra_tsensor_resume)658};659 660static const struct of_device_id tegra_tsensor_of_match[] = {661 { .compatible = "nvidia,tegra30-tsensor", },662 {},663};664MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match);665 666static struct platform_driver tegra_tsensor_driver = {667 .probe = tegra_tsensor_probe,668 .driver = {669 .name = "tegra30-tsensor",670 .of_match_table = tegra_tsensor_of_match,671 .pm = &tegra_tsensor_pm_ops,672 },673};674module_platform_driver(tegra_tsensor_driver);675 676MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver");677MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");678MODULE_LICENSE("GPL");679