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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * OMAP5xxx bandgap registers, bitfields and temperature definitions4 *5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/6 * Contact:7 * Eduardo Valentin <eduardo.valentin@ti.com>8 */9#ifndef __OMAP5XXX_BANDGAP_H10#define __OMAP5XXX_BANDGAP_H11 12/**13 * *** OMAP5430 ***14 *15 * Below, in sequence, are the Register definitions,16 * the bitfields and the temperature definitions for OMAP5430.17 */18 19/**20 * OMAP5430 register definitions21 *22 * Registers are defined as offsets. The offsets are23 * relative to FUSE_OPP_BGAP_GPU on 5430.24 *25 * Register below are grouped by domain (not necessarily in offset order)26 */27 28/* OMAP5430.GPU register offsets */29#define OMAP5430_FUSE_OPP_BGAP_GPU 0x030#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x15031#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A832#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B433#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F834#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC35 36/* OMAP5430.MPU register offsets */37#define OMAP5430_FUSE_OPP_BGAP_MPU 0x438#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C39#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A440#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B041#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E442#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E843 44/* OMAP5430.MPU register offsets */45#define OMAP5430_FUSE_OPP_BGAP_CORE 0x846#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x15447#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC48#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B849#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C50#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x21051 52/* OMAP5430.common register offsets */53#define OMAP5430_BGAP_CTRL_OFFSET 0x1A054#define OMAP5430_BGAP_STATUS_OFFSET 0x1C855 56/**57 * Register bitfields for OMAP543058 *59 * All the macros bellow define the required bits for60 * controlling temperature on OMAP5430. Bit defines are61 * grouped by register.62 */63 64/* OMAP5430.TEMP_SENSOR */65#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)66#define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)67#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)68#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)69 70/* OMAP5430.BANDGAP_CTRL */71#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)72#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)73#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)74#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)75#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)76#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)77#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)78#define OMAP5430_MASK_COLD_GPU_MASK BIT(2)79#define OMAP5430_MASK_HOT_MPU_MASK BIT(1)80#define OMAP5430_MASK_COLD_MPU_MASK BIT(0)81 82/* OMAP5430.BANDGAP_COUNTER */83#define OMAP5430_COUNTER_MASK (0xffffff << 0)84 85/* OMAP5430.BANDGAP_THRESHOLD */86#define OMAP5430_T_HOT_MASK (0x3ff << 16)87#define OMAP5430_T_COLD_MASK (0x3ff << 0)88 89/* OMAP5430.TSHUT_THRESHOLD */90#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)91#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)92 93/* OMAP5430.BANDGAP_STATUS */94#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)95#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)96#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)97#define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)98#define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)99#define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)100 101/**102 * Temperature limits and thresholds for OMAP5430103 *104 * All the macros bellow are definitions for handling the105 * ADC conversions and representation of temperature limits106 * and thresholds for OMAP5430. Definitions are grouped107 * by temperature domain.108 */109 110/* OMAP5430.common temperature definitions */111/* ADC conversion table limits */112#define OMAP5430_ADC_START_VALUE 540113#define OMAP5430_ADC_END_VALUE 945114 115/* OMAP5430.GPU temperature definitions */116/* bandgap clock limits */117#define OMAP5430_GPU_MAX_FREQ 1500000118#define OMAP5430_GPU_MIN_FREQ 1000000119/* interrupts thresholds */120#define OMAP5430_GPU_TSHUT_HOT 915121#define OMAP5430_GPU_TSHUT_COLD 900122#define OMAP5430_GPU_T_HOT 800123#define OMAP5430_GPU_T_COLD 795124 125/* OMAP5430.MPU temperature definitions */126/* bandgap clock limits */127#define OMAP5430_MPU_MAX_FREQ 1500000128#define OMAP5430_MPU_MIN_FREQ 1000000129/* interrupts thresholds */130#define OMAP5430_MPU_TSHUT_HOT 915131#define OMAP5430_MPU_TSHUT_COLD 900132#define OMAP5430_MPU_T_HOT 800133#define OMAP5430_MPU_T_COLD 795134 135/* OMAP5430.CORE temperature definitions */136/* bandgap clock limits */137#define OMAP5430_CORE_MAX_FREQ 1500000138#define OMAP5430_CORE_MIN_FREQ 1000000139/* interrupts thresholds */140#define OMAP5430_CORE_TSHUT_HOT 915141#define OMAP5430_CORE_TSHUT_COLD 900142#define OMAP5430_CORE_T_HOT 800143#define OMAP5430_CORE_T_COLD 795144 145#endif /* __OMAP5XXX_BANDGAP_H */146