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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Thunderbolt driver - NHI driver4 *5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>6 * Copyright (C) 2018, Intel Corporation7 */8 9#ifndef DSL3510_H_10#define DSL3510_H_11 12#include <linux/thunderbolt.h>13 14enum nhi_fw_mode {15 NHI_FW_SAFE_MODE,16 NHI_FW_AUTH_MODE,17 NHI_FW_EP_MODE,18 NHI_FW_CM_MODE,19};20 21enum nhi_mailbox_cmd {22 NHI_MAILBOX_SAVE_DEVS = 0x05,23 NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,24 NHI_MAILBOX_DRV_UNLOADS = 0x07,25 NHI_MAILBOX_DISCONNECT_PA = 0x10,26 NHI_MAILBOX_DISCONNECT_PB = 0x11,27 NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,28};29 30int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);31enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);32 33/**34 * struct tb_nhi_ops - NHI specific optional operations35 * @init: NHI specific initialization36 * @suspend_noirq: NHI specific suspend_noirq hook37 * @resume_noirq: NHI specific resume_noirq hook38 * @runtime_suspend: NHI specific runtime_suspend hook39 * @runtime_resume: NHI specific runtime_resume hook40 * @shutdown: NHI specific shutdown41 */42struct tb_nhi_ops {43 int (*init)(struct tb_nhi *nhi);44 int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);45 int (*resume_noirq)(struct tb_nhi *nhi);46 int (*runtime_suspend)(struct tb_nhi *nhi);47 int (*runtime_resume)(struct tb_nhi *nhi);48 void (*shutdown)(struct tb_nhi *nhi);49};50 51extern const struct tb_nhi_ops icl_nhi_ops;52 53/*54 * PCI IDs used in this driver from Win Ridge forward. There is no55 * need for the PCI quirk anymore as we will use ICM also on Apple56 * hardware.57 */58#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x113459#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x113760#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d61#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e62#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf63#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c064#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d265#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d366#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d967#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da68#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc69#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd70#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de71#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e772#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e873#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea74#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb75#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef76#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e77#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d78#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x578179#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x578480#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x578681#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a482#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb283#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec284#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec385#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d86#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a1787#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b88#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d89#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f90#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a2191#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e92#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d93#define PCI_DEVICE_ID_INTEL_LNL_NHI0 0xa83394#define PCI_DEVICE_ID_INTEL_LNL_NHI1 0xa83495 96#define PCI_CLASS_SERIAL_USB_USB4 0x0c034097 98#endif99