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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * USB4 port sideband registers found on routers and retimers4 *5 * Copyright (C) 2020, Intel Corporation6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>7 * Rajmohan Mani <rajmohan.mani@intel.com>8 */9 10#ifndef _SB_REGS11#define _SB_REGS12 13#define USB4_SB_VENDOR_ID 0x0014#define USB4_SB_PRODUCT_ID 0x0115#define USB4_SB_FW_VERSION 0x0216#define USB4_SB_DEBUG_CONF 0x0517#define USB4_SB_DEBUG 0x0618#define USB4_SB_LRD_TUNING 0x0719#define USB4_SB_OPCODE 0x0820 21enum usb4_sb_opcode {22 USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */23 USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */24 USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */25 USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */26 USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */27 USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355, /* "USUP" */28 USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */29 USB4_SB_OPCODE_QUERY_CABLE_RETIMER = 0x524c4243, /* "CBLR" */30 USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */31 USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */32 USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */33 USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */34 USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */35 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */36 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */37 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */38 USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */39};40 41#define USB4_SB_METADATA 0x0942#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0)43#define USB4_SB_LINK_CONF 0x0c44#define USB4_SB_GEN23_TXFFE 0x0d45#define USB4_SB_GEN4_TXFFE 0x0e46#define USB4_SB_VERSION 0x0f47#define USB4_SB_DATA 0x1248 49/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */50#define USB4_MARGIN_CAP_0_MODES_HW BIT(0)51#define USB4_MARGIN_CAP_0_MODES_SW BIT(1)52#define USB4_MARGIN_CAP_0_2_LANES BIT(2)53#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3)54#define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x055#define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x156#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x257#define USB4_MARGIN_CAP_0_TIME BIT(5)58#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6)59#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)60#define USB4_MARGIN_CAP_0_OPT_VOLTAGE_SUPPORT BIT(19)61#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK GENMASK(26, 20)62#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)63#define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8)64#define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9)65#define USB4_MARGIN_CAP_1_TIME_MIN 0x066#define USB4_MARGIN_CAP_1_TIME_LR 0x167#define USB4_MARGIN_CAP_1_TIME_BOTH 0x268#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11)69#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16)70#define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21)71#define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26)72 73/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */74#define USB4_MARGIN_HW_TIME BIT(3)75#define USB4_MARGIN_HW_RH BIT(4)76#define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5)77#define USB4_MARGIN_HW_BER_SHIFT 578#define USB4_MARGIN_HW_OPT_VOLTAGE BIT(10)79 80/* Applicable to all margin values */81#define USB4_MARGIN_HW_RES_1_MARGIN_MASK GENMASK(6, 0)82#define USB4_MARGIN_HW_RES_1_EXCEEDS BIT(7)83/* Different lane margin shifts */84#define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT 885#define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT 1686#define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT 2487 88/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */89#define USB4_MARGIN_SW_LANES_MASK GENMASK(2, 0)90#define USB4_MARGIN_SW_LANE_0 0x091#define USB4_MARGIN_SW_LANE_1 0x192#define USB4_MARGIN_SW_ALL_LANES 0x793#define USB4_MARGIN_SW_TIME BIT(3)94#define USB4_MARGIN_SW_RH BIT(4)95#define USB4_MARGIN_SW_OPT_VOLTAGE BIT(5)96#define USB4_MARGIN_SW_VT_MASK GENMASK(12, 6)97#define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13)98 99#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK GENMASK(3, 0)100#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK GENMASK(7, 4)101 102#endif103