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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Thunderbolt driver - Port/Switch config area registers4 *5 * Every thunderbolt device consists (logically) of a switch with multiple6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,7 * COUNTERS) which are used to configure the device.8 *9 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>10 * Copyright (C) 2018, Intel Corporation11 */12 13#ifndef _TB_REGS14#define _TB_REGS15 16#include <linux/types.h>17 18 19#define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */20 21 22/*23 * TODO: should be 63? But we do not know how to receive frames larger than 25624 * bytes at the frame level. (header + checksum = 16, 60*4 = 240)25 */26#define TB_MAX_CONFIG_RW_LENGTH 6027 28enum tb_switch_cap {29 TB_SWITCH_CAP_TMU = 0x03,30 TB_SWITCH_CAP_VSE = 0x05,31};32 33enum tb_switch_vse_cap {34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */35 TB_VSE_CAP_TIME2 = 0x03,36 TB_VSE_CAP_CP_LP = 0x04,37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */38};39 40enum tb_port_cap {41 TB_PORT_CAP_PHY = 0x01,42 TB_PORT_CAP_POWER = 0x02,43 TB_PORT_CAP_TIME1 = 0x03,44 TB_PORT_CAP_ADAP = 0x04,45 TB_PORT_CAP_VSE = 0x05,46 TB_PORT_CAP_USB4 = 0x06,47};48 49enum tb_port_state {50 TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */51 TB_PORT_CONNECTING = 1, /* retry */52 TB_PORT_UP = 2,53 TB_PORT_TX_CL0S = 3,54 TB_PORT_RX_CL0S = 4,55 TB_PORT_CL1 = 5,56 TB_PORT_CL2 = 6,57 TB_PORT_UNPLUGGED = 7,58};59 60/* capability headers */61 62struct tb_cap_basic {63 u8 next;64 /* enum tb_cap cap:8; prevent "narrower than values of its type" */65 u8 cap; /* if cap == 0x05 then we have a extended capability */66} __packed;67 68/**69 * struct tb_cap_extended_short - Switch extended short capability70 * @next: Pointer to the next capability. If @next and @length are zero71 * then we have a long cap.72 * @cap: Base capability ID (see &enum tb_switch_cap)73 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)74 * @length: Length of this capability75 */76struct tb_cap_extended_short {77 u8 next;78 u8 cap;79 u8 vsec_id;80 u8 length;81} __packed;82 83/**84 * struct tb_cap_extended_long - Switch extended long capability85 * @zero1: This field should be zero86 * @cap: Base capability ID (see &enum tb_switch_cap)87 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)88 * @zero2: This field should be zero89 * @next: Pointer to the next capability90 * @length: Length of this capability91 */92struct tb_cap_extended_long {93 u8 zero1;94 u8 cap;95 u8 vsec_id;96 u8 zero2;97 u16 next;98 u16 length;99} __packed;100 101/**102 * struct tb_cap_any - Structure capable of hold every capability103 * @basic: Basic capability104 * @extended_short: Vendor specific capability105 * @extended_long: Vendor specific extended capability106 */107struct tb_cap_any {108 union {109 struct tb_cap_basic basic;110 struct tb_cap_extended_short extended_short;111 struct tb_cap_extended_long extended_long;112 };113} __packed;114 115/* capabilities */116 117struct tb_cap_link_controller {118 struct tb_cap_extended_long cap_header;119 u32 count:4; /* number of link controllers */120 u32 unknown1:4;121 u32 base_offset:8; /*122 * offset (into this capability) of the configuration123 * area of the first link controller124 */125 u32 length:12; /* link controller configuration area length */126 u32 unknown2:4; /* TODO check that length is correct */127} __packed;128 129struct tb_cap_phy {130 struct tb_cap_basic cap_header;131 u32 unknown1:16;132 u32 unknown2:14;133 bool disable:1;134 u32 unknown3:11;135 enum tb_port_state state:4;136 u32 unknown4:2;137} __packed;138 139struct tb_eeprom_ctl {140 bool fl_sk:1; /* send pulse to transfer one bit */141 bool fl_cs:1; /* set to 0 before access */142 bool fl_di:1; /* to eeprom */143 bool fl_do:1; /* from eeprom */144 bool bit_banging_enable:1; /* set to 1 before access */145 bool not_present:1; /* should be 0 */146 bool unknown1:1;147 bool present:1; /* should be 1 */148 u32 unknown2:24;149} __packed;150 151struct tb_cap_plug_events {152 struct tb_cap_extended_short cap_header;153 u32 __unknown1:2; /* VSC_CS_1 */154 u32 plug_events:5; /* VSC_CS_1 */155 u32 __unknown2:25; /* VSC_CS_1 */156 u32 vsc_cs_2;157 u32 vsc_cs_3;158 struct tb_eeprom_ctl eeprom_ctl;159 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */160 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */161} __packed;162 163/* device headers */164 165/* Present on port 0 in TB_CFG_SWITCH at address zero. */166struct tb_regs_switch_header {167 /* DWORD 0 */168 u16 vendor_id;169 u16 device_id;170 /* DWORD 1 */171 u32 first_cap_offset:8;172 u32 upstream_port_number:6;173 u32 max_port_number:6;174 u32 depth:3;175 u32 __unknown1:1;176 u32 revision:8;177 /* DWORD 2 */178 u32 route_lo;179 /* DWORD 3 */180 u32 route_hi:31;181 bool enabled:1;182 /* DWORD 4 */183 u32 plug_events_delay:8; /*184 * RW, pause between plug events in185 * milliseconds. Writing 0x00 is interpreted186 * as 255ms.187 */188 u32 cmuv:8;189 u32 __unknown4:8;190 u32 thunderbolt_version:8;191} __packed;192 193/* Used with the router thunderbolt_version */194#define USB4_VERSION_MAJOR_MASK GENMASK(7, 5)195 196#define ROUTER_CS_1 0x01197#define ROUTER_CS_3 0x03198#define ROUTER_CS_3_V BIT(31)199#define ROUTER_CS_4 0x04200/* Used with the router cmuv field */201#define ROUTER_CS_4_CMUV_V1 0x10202#define ROUTER_CS_4_CMUV_V2 0x20203#define ROUTER_CS_5 0x05204#define ROUTER_CS_5_SLP BIT(0)205#define ROUTER_CS_5_WOP BIT(1)206#define ROUTER_CS_5_WOU BIT(2)207#define ROUTER_CS_5_WOD BIT(3)208#define ROUTER_CS_5_CNS BIT(23)209#define ROUTER_CS_5_PTO BIT(24)210#define ROUTER_CS_5_UTO BIT(25)211#define ROUTER_CS_5_HCO BIT(26)212#define ROUTER_CS_5_CV BIT(31)213#define ROUTER_CS_6 0x06214#define ROUTER_CS_6_SLPR BIT(0)215#define ROUTER_CS_6_TNS BIT(1)216#define ROUTER_CS_6_WOPS BIT(2)217#define ROUTER_CS_6_WOUS BIT(3)218#define ROUTER_CS_6_HCI BIT(18)219#define ROUTER_CS_6_CR BIT(25)220#define ROUTER_CS_7 0x07221#define ROUTER_CS_9 0x09222#define ROUTER_CS_25 0x19223#define ROUTER_CS_26 0x1a224#define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0)225#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)226#define ROUTER_CS_26_STATUS_SHIFT 24227#define ROUTER_CS_26_ONS BIT(30)228#define ROUTER_CS_26_OV BIT(31)229 230/* USB4 router operations opcodes */231enum usb4_switch_op {232 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,233 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,234 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,235 USB4_SWITCH_OP_NVM_WRITE = 0x20,236 USB4_SWITCH_OP_NVM_AUTH = 0x21,237 USB4_SWITCH_OP_NVM_READ = 0x22,238 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,239 USB4_SWITCH_OP_DROM_READ = 0x24,240 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,241 USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,242};243 244/* Router TMU configuration */245#define TMU_RTR_CS_0 0x00246#define TMU_RTR_CS_0_FREQ_WIND_MASK GENMASK(26, 16)247#define TMU_RTR_CS_0_TD BIT(27)248#define TMU_RTR_CS_0_UCAP BIT(30)249#define TMU_RTR_CS_1 0x01250#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)251#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16252#define TMU_RTR_CS_2 0x02253#define TMU_RTR_CS_3 0x03254#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)255#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)256#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16257#define TMU_RTR_CS_15 0x0f258#define TMU_RTR_CS_15_FREQ_AVG_MASK GENMASK(5, 0)259#define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6)260#define TMU_RTR_CS_15_OFFSET_AVG_MASK GENMASK(17, 12)261#define TMU_RTR_CS_15_ERROR_AVG_MASK GENMASK(23, 18)262#define TMU_RTR_CS_18 0x12263#define TMU_RTR_CS_18_DELTA_AVG_CONST_MASK GENMASK(23, 16)264#define TMU_RTR_CS_22 0x16265#define TMU_RTR_CS_24 0x18266#define TMU_RTR_CS_25 0x19267 268enum tb_port_type {269 TB_TYPE_INACTIVE = 0x000000,270 TB_TYPE_PORT = 0x000001,271 TB_TYPE_NHI = 0x000002,272 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */273 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */274 TB_TYPE_DP_HDMI_IN = 0x0e0101,275 TB_TYPE_DP_HDMI_OUT = 0x0e0102,276 TB_TYPE_PCIE_DOWN = 0x100101,277 TB_TYPE_PCIE_UP = 0x100102,278 TB_TYPE_USB3_DOWN = 0x200101,279 TB_TYPE_USB3_UP = 0x200102,280};281 282/* Present on every port in TB_CF_PORT at address zero. */283struct tb_regs_port_header {284 /* DWORD 0 */285 u16 vendor_id;286 u16 device_id;287 /* DWORD 1 */288 u32 first_cap_offset:8;289 u32 max_counters:11;290 u32 counters_support:1;291 u32 __unknown1:4;292 u32 revision:8;293 /* DWORD 2 */294 enum tb_port_type type:24;295 u32 thunderbolt_version:8;296 /* DWORD 3 */297 u32 __unknown2:20;298 u32 port_number:6;299 u32 __unknown3:6;300 /* DWORD 4 */301 u32 nfc_credits;302 /* DWORD 5 */303 u32 max_in_hop_id:11;304 u32 max_out_hop_id:11;305 u32 __unknown4:10;306 /* DWORD 6 */307 u32 __unknown5;308 /* DWORD 7 */309 u32 __unknown6;310 311} __packed;312 313/* Basic adapter configuration registers */314#define ADP_CS_4 0x04315#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)316#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)317#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20318#define ADP_CS_4_LCK BIT(31)319#define ADP_CS_5 0x05320#define ADP_CS_5_LCA_MASK GENMASK(28, 22)321#define ADP_CS_5_LCA_SHIFT 22322#define ADP_CS_5_DHP BIT(31)323 324/* TMU adapter registers */325#define TMU_ADP_CS_3 0x03326#define TMU_ADP_CS_3_UDM BIT(29)327#define TMU_ADP_CS_6 0x06328#define TMU_ADP_CS_6_DTS BIT(1)329#define TMU_ADP_CS_8 0x08330#define TMU_ADP_CS_8_REPL_TIMEOUT_MASK GENMASK(14, 0)331#define TMU_ADP_CS_8_EUDM BIT(15)332#define TMU_ADP_CS_8_REPL_THRESHOLD_MASK GENMASK(25, 16)333#define TMU_ADP_CS_9 0x09334#define TMU_ADP_CS_9_REPL_N_MASK GENMASK(7, 0)335#define TMU_ADP_CS_9_DIRSWITCH_N_MASK GENMASK(15, 8)336#define TMU_ADP_CS_9_ADP_TS_INTERVAL_MASK GENMASK(31, 16)337 338/* Lane adapter registers */339#define LANE_ADP_CS_0 0x00340#define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK GENMASK(19, 16)341#define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT 16342#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)343#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20344#define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL 0x2345#define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26)346#define LANE_ADP_CS_0_CL1_SUPPORT BIT(27)347#define LANE_ADP_CS_0_CL2_SUPPORT BIT(28)348#define LANE_ADP_CS_1 0x01349#define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0)350#define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc351#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(5, 4)352#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4353#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1354#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3355#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK GENMASK(7, 6)356#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX 0x1357#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX 0x2358#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL 0x0359#define LANE_ADP_CS_1_CL0S_ENABLE BIT(10)360#define LANE_ADP_CS_1_CL1_ENABLE BIT(11)361#define LANE_ADP_CS_1_CL2_ENABLE BIT(12)362#define LANE_ADP_CS_1_LD BIT(14)363#define LANE_ADP_CS_1_LB BIT(15)364#define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)365#define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16366#define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8367#define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4368#define LANE_ADP_CS_1_CURRENT_SPEED_GEN4 0x2369#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)370#define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20371#define LANE_ADP_CS_1_PMS BIT(30)372 373/* USB4 port registers */374#define PORT_CS_1 0x01375#define PORT_CS_1_LENGTH_SHIFT 8376#define PORT_CS_1_TARGET_MASK GENMASK(18, 16)377#define PORT_CS_1_TARGET_SHIFT 16378#define PORT_CS_1_RETIMER_INDEX_SHIFT 20379#define PORT_CS_1_WNR_WRITE BIT(24)380#define PORT_CS_1_NR BIT(25)381#define PORT_CS_1_RC BIT(26)382#define PORT_CS_1_PND BIT(31)383#define PORT_CS_2 0x02384#define PORT_CS_18 0x12385#define PORT_CS_18_BE BIT(8)386#define PORT_CS_18_TCM BIT(9)387#define PORT_CS_18_CPS BIT(10)388#define PORT_CS_18_WOCS BIT(16)389#define PORT_CS_18_WODS BIT(17)390#define PORT_CS_18_WOU4S BIT(18)391#define PORT_CS_18_CSA BIT(22)392#define PORT_CS_18_TIP BIT(24)393#define PORT_CS_19 0x13394#define PORT_CS_19_DPR BIT(0)395#define PORT_CS_19_PC BIT(3)396#define PORT_CS_19_PID BIT(4)397#define PORT_CS_19_WOC BIT(16)398#define PORT_CS_19_WOD BIT(17)399#define PORT_CS_19_WOU4 BIT(18)400#define PORT_CS_19_START_ASYM BIT(24)401 402/* Display Port adapter registers */403#define ADP_DP_CS_0 0x00404#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)405#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16406#define ADP_DP_CS_0_AE BIT(30)407#define ADP_DP_CS_0_VE BIT(31)408#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)409#define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)410#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11411#define ADP_DP_CS_2 0x02412#define ADP_DP_CS_2_NRD_MLC_MASK GENMASK(2, 0)413#define ADP_DP_CS_2_HPD BIT(6)414#define ADP_DP_CS_2_NRD_MLR_MASK GENMASK(9, 7)415#define ADP_DP_CS_2_NRD_MLR_SHIFT 7416#define ADP_DP_CS_2_CA BIT(10)417#define ADP_DP_CS_2_GR_MASK GENMASK(12, 11)418#define ADP_DP_CS_2_GR_SHIFT 11419#define ADP_DP_CS_2_GR_0_25G 0x0420#define ADP_DP_CS_2_GR_0_5G 0x1421#define ADP_DP_CS_2_GR_1G 0x2422#define ADP_DP_CS_2_GROUP_ID_MASK GENMASK(15, 13)423#define ADP_DP_CS_2_GROUP_ID_SHIFT 13424#define ADP_DP_CS_2_CM_ID_MASK GENMASK(19, 16)425#define ADP_DP_CS_2_CM_ID_SHIFT 16426#define ADP_DP_CS_2_CMMS BIT(20)427#define ADP_DP_CS_2_ESTIMATED_BW_MASK GENMASK(31, 24)428#define ADP_DP_CS_2_ESTIMATED_BW_SHIFT 24429#define ADP_DP_CS_3 0x03430#define ADP_DP_CS_3_HPDC BIT(9)431#define DP_LOCAL_CAP 0x04432#define DP_REMOTE_CAP 0x05433/* For DP IN adapter */434#define DP_STATUS 0x06435#define DP_STATUS_ALLOCATED_BW_MASK GENMASK(31, 24)436#define DP_STATUS_ALLOCATED_BW_SHIFT 24437/* For DP OUT adapter */438#define DP_STATUS_CTRL 0x06439#define DP_STATUS_CTRL_CMHS BIT(25)440#define DP_STATUS_CTRL_UF BIT(26)441#define DP_COMMON_CAP 0x07442/* Only if DP IN supports BW allocation mode */443#define ADP_DP_CS_8 0x08444#define ADP_DP_CS_8_REQUESTED_BW_MASK GENMASK(7, 0)445#define ADP_DP_CS_8_DPME BIT(30)446#define ADP_DP_CS_8_DR BIT(31)447 448/*449 * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP450 * with exception of DPRX done.451 */452#define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)453#define DP_COMMON_CAP_RATE_SHIFT 8454#define DP_COMMON_CAP_RATE_RBR 0x0455#define DP_COMMON_CAP_RATE_HBR 0x1456#define DP_COMMON_CAP_RATE_HBR2 0x2457#define DP_COMMON_CAP_RATE_HBR3 0x3458#define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)459#define DP_COMMON_CAP_LANES_SHIFT 12460#define DP_COMMON_CAP_1_LANE 0x0461#define DP_COMMON_CAP_2_LANES 0x1462#define DP_COMMON_CAP_4_LANES 0x2463#define DP_COMMON_CAP_UHBR10 BIT(17)464#define DP_COMMON_CAP_UHBR20 BIT(18)465#define DP_COMMON_CAP_UHBR13_5 BIT(19)466#define DP_COMMON_CAP_LTTPR_NS BIT(27)467#define DP_COMMON_CAP_BW_MODE BIT(28)468#define DP_COMMON_CAP_DPRX_DONE BIT(31)469/* Only present if DP IN supports BW allocation mode */470#define ADP_DP_CS_8 0x08471#define ADP_DP_CS_8_DPME BIT(30)472#define ADP_DP_CS_8_DR BIT(31)473 474/* PCIe adapter registers */475#define ADP_PCIE_CS_0 0x00476#define ADP_PCIE_CS_0_PE BIT(31)477#define ADP_PCIE_CS_1 0x01478#define ADP_PCIE_CS_1_EE BIT(0)479 480/* USB adapter registers */481#define ADP_USB3_CS_0 0x00482#define ADP_USB3_CS_0_V BIT(30)483#define ADP_USB3_CS_0_PE BIT(31)484#define ADP_USB3_CS_1 0x01485#define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)486#define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12)487#define ADP_USB3_CS_1_CDBW_SHIFT 12488#define ADP_USB3_CS_1_HCA BIT(31)489#define ADP_USB3_CS_2 0x02490#define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)491#define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12)492#define ADP_USB3_CS_2_ADBW_SHIFT 12493#define ADP_USB3_CS_2_CMR BIT(31)494#define ADP_USB3_CS_3 0x03495#define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)496#define ADP_USB3_CS_4 0x04497#define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12)498#define ADP_USB3_CS_4_MSLR_SHIFT 12499#define ADP_USB3_CS_4_MSLR_20G 0x1500 501/* Hop register from TB_CFG_HOPS. 8 byte per entry. */502struct tb_regs_hop {503 /* DWORD 0 */504 u32 next_hop:11; /*505 * hop to take after sending the packet through506 * out_port (on the incoming port of the next switch)507 */508 u32 out_port:6; /* next port of the path (on the same switch) */509 u32 initial_credits:7;510 u32 pmps:1;511 u32 unknown1:6; /* set to zero */512 bool enable:1;513 514 /* DWORD 1 */515 u32 weight:4;516 u32 unknown2:4; /* set to zero */517 u32 priority:3;518 bool drop_packages:1;519 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */520 bool counter_enable:1;521 bool ingress_fc:1;522 bool egress_fc:1;523 bool ingress_shared_buffer:1;524 bool egress_shared_buffer:1;525 bool pending:1;526 u32 unknown3:3; /* set to zero */527} __packed;528 529/* TMU Thunderbolt 3 registers */530#define TB_TIME_VSEC_3_CS_9 0x9531#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16)532#define TB_TIME_VSEC_3_CS_26 0x1a533#define TB_TIME_VSEC_3_CS_26_TD BIT(22)534 535/*536 * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6537 * (see above) as in USB4 spec, but these specific bits used for Titan Ridge538 * only and reserved in USB4 spec.539 */540#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2)541#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)542#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)543 544/* Plug Events registers */545#define TB_PLUG_EVENTS_USB_DISABLE BIT(2)546#define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3)547#define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4)548#define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5)549#define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6)550 551#define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b552#define TB_PLUG_EVENTS_PCIE_CMD 0x1c553#define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0)554#define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT 10555#define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10)556#define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21)557#define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1558#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT 22559#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22)560#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2561#define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30)562#define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31)563#define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d564 565/* CP Low Power registers */566#define TB_LOW_PWR_C1_CL1 0x1567#define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1)568#define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1)569#define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1)570#define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3)571#define TB_LOW_PWR_C3_CL1 0x3572 573/* Common link controller registers */574#define TB_LC_DESC 0x02575#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)576#define TB_LC_DESC_SIZE_SHIFT 8577#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)578#define TB_LC_DESC_PORT_SIZE_SHIFT 16579#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)580#define TB_LC_FUSE 0x03581#define TB_LC_SNK_ALLOCATION 0x10582#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)583#define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1584#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4585#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)586#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1587#define TB_LC_POWER 0x740588 589/* Link controller registers */590#define TB_LC_PORT_MODE 0x26591#define TB_LC_PORT_MODE_DPR BIT(0)592 593#define TB_LC_CS_42 0x2a594#define TB_LC_CS_42_USB_PLUGGED BIT(31)595 596#define TB_LC_PORT_ATTR 0x8d597#define TB_LC_PORT_ATTR_BE BIT(12)598 599#define TB_LC_SX_CTRL 0x96600#define TB_LC_SX_CTRL_WOC BIT(1)601#define TB_LC_SX_CTRL_WOD BIT(2)602#define TB_LC_SX_CTRL_WODPC BIT(3)603#define TB_LC_SX_CTRL_WODPD BIT(4)604#define TB_LC_SX_CTRL_WOU4 BIT(5)605#define TB_LC_SX_CTRL_WOP BIT(6)606#define TB_LC_SX_CTRL_L1C BIT(16)607#define TB_LC_SX_CTRL_L1D BIT(17)608#define TB_LC_SX_CTRL_L2C BIT(20)609#define TB_LC_SX_CTRL_L2D BIT(21)610#define TB_LC_SX_CTRL_SLI BIT(29)611#define TB_LC_SX_CTRL_UPSTREAM BIT(30)612#define TB_LC_SX_CTRL_SLP BIT(31)613#define TB_LC_LINK_ATTR 0x97614#define TB_LC_LINK_ATTR_CPS BIT(18)615 616#define TB_LC_LINK_REQ 0xad617#define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31)618 619#endif620