808 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Synopsys DesignWare 8250 driver.4 *5 * Copyright 2011 Picochip, Jamie Iles.6 * Copyright 2013 Intel Corporation7 *8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the9 * LCR is written whilst busy. If it is, then a busy detect interrupt is10 * raised, the LCR needs to be rewritten and the uart status register read.11 */12#include <linux/clk.h>13#include <linux/delay.h>14#include <linux/device.h>15#include <linux/io.h>16#include <linux/mod_devicetable.h>17#include <linux/module.h>18#include <linux/notifier.h>19#include <linux/platform_device.h>20#include <linux/pm_runtime.h>21#include <linux/property.h>22#include <linux/reset.h>23#include <linux/slab.h>24#include <linux/workqueue.h>25 26#include <asm/byteorder.h>27 28#include <linux/serial_8250.h>29#include <linux/serial_reg.h>30 31#include "8250_dwlib.h"32 33/* Offsets for the DesignWare specific registers */34#define DW_UART_USR 0x1f /* UART Status Register */35#define DW_UART_DMASA 0xa8 /* DMA Software Ack */36 37#define OCTEON_UART_USR 0x27 /* UART Status Register */38 39#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */40#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */41 42/* DesignWare specific register fields */43#define DW_UART_MCR_SIRE BIT(6)44 45/* Renesas specific register fields */46#define RZN1_UART_xDMACR_DMA_EN BIT(0)47#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)48#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)49#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)50#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)51 52/* Quirks */53#define DW_UART_QUIRK_OCTEON BIT(0)54#define DW_UART_QUIRK_ARMADA_38X BIT(1)55#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)56#define DW_UART_QUIRK_IS_DMA_FC BIT(3)57#define DW_UART_QUIRK_APMC0D08 BIT(4)58#define DW_UART_QUIRK_CPR_VALUE BIT(5)59 60struct dw8250_platform_data {61 u8 usr_reg;62 u32 cpr_value;63 unsigned int quirks;64};65 66struct dw8250_data {67 struct dw8250_port_data data;68 const struct dw8250_platform_data *pdata;69 70 int msr_mask_on;71 int msr_mask_off;72 struct clk *clk;73 struct clk *pclk;74 struct notifier_block clk_notifier;75 struct work_struct clk_work;76 struct reset_control *rst;77 78 unsigned int skip_autocfg:1;79 unsigned int uart_16550_compatible:1;80};81 82static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)83{84 return container_of(data, struct dw8250_data, data);85}86 87static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)88{89 return container_of(nb, struct dw8250_data, clk_notifier);90}91 92static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)93{94 return container_of(work, struct dw8250_data, clk_work);95}96 97static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)98{99 struct dw8250_data *d = to_dw8250_data(p->private_data);100 101 /* Override any modem control signals if needed */102 if (offset == UART_MSR) {103 value |= d->msr_mask_on;104 value &= ~d->msr_mask_off;105 }106 107 return value;108}109 110static void dw8250_force_idle(struct uart_port *p)111{112 struct uart_8250_port *up = up_to_u8250p(p);113 unsigned int lsr;114 115 serial8250_clear_and_reinit_fifos(up);116 117 /*118 * With PSLVERR_RESP_EN parameter set to 1, the device generates an119 * error response when an attempt to read an empty RBR with FIFO120 * enabled.121 */122 if (up->fcr & UART_FCR_ENABLE_FIFO) {123 lsr = p->serial_in(p, UART_LSR);124 if (!(lsr & UART_LSR_DR))125 return;126 }127 128 (void)p->serial_in(p, UART_RX);129}130 131static void dw8250_check_lcr(struct uart_port *p, int offset, int value)132{133 struct dw8250_data *d = to_dw8250_data(p->private_data);134 void __iomem *addr = p->membase + (offset << p->regshift);135 int tries = 1000;136 137 if (offset != UART_LCR || d->uart_16550_compatible)138 return;139 140 /* Make sure LCR write wasn't ignored */141 while (tries--) {142 unsigned int lcr = p->serial_in(p, offset);143 144 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))145 return;146 147 dw8250_force_idle(p);148 149#ifdef CONFIG_64BIT150 if (p->type == PORT_OCTEON)151 __raw_writeq(value & 0xff, addr);152 else153#endif154 if (p->iotype == UPIO_MEM32)155 writel(value, addr);156 else if (p->iotype == UPIO_MEM32BE)157 iowrite32be(value, addr);158 else159 writeb(value, addr);160 }161 /*162 * FIXME: this deadlocks if port->lock is already held163 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);164 */165}166 167/* Returns once the transmitter is empty or we run out of retries */168static void dw8250_tx_wait_empty(struct uart_port *p)169{170 struct uart_8250_port *up = up_to_u8250p(p);171 unsigned int tries = 20000;172 unsigned int delay_threshold = tries - 1000;173 unsigned int lsr;174 175 while (tries--) {176 lsr = readb (p->membase + (UART_LSR << p->regshift));177 up->lsr_saved_flags |= lsr & up->lsr_save_mask;178 179 if (lsr & UART_LSR_TEMT)180 break;181 182 /* The device is first given a chance to empty without delay,183 * to avoid slowdowns at high bitrates. If after 1000 tries184 * the buffer has still not emptied, allow more time for low-185 * speed links. */186 if (tries < delay_threshold)187 udelay (1);188 }189}190 191static void dw8250_serial_out(struct uart_port *p, int offset, int value)192{193 writeb(value, p->membase + (offset << p->regshift));194 dw8250_check_lcr(p, offset, value);195}196 197static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)198{199 /* Allow the TX to drain before we reconfigure */200 if (offset == UART_LCR)201 dw8250_tx_wait_empty(p);202 203 dw8250_serial_out(p, offset, value);204}205 206static unsigned int dw8250_serial_in(struct uart_port *p, int offset)207{208 unsigned int value = readb(p->membase + (offset << p->regshift));209 210 return dw8250_modify_msr(p, offset, value);211}212 213#ifdef CONFIG_64BIT214static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)215{216 u8 value = __raw_readq(p->membase + (offset << p->regshift));217 218 return dw8250_modify_msr(p, offset, value);219}220 221static void dw8250_serial_outq(struct uart_port *p, int offset, int value)222{223 value &= 0xff;224 __raw_writeq(value, p->membase + (offset << p->regshift));225 /* Read back to ensure register write ordering. */226 __raw_readq(p->membase + (UART_LCR << p->regshift));227 228 dw8250_check_lcr(p, offset, value);229}230#endif /* CONFIG_64BIT */231 232static void dw8250_serial_out32(struct uart_port *p, int offset, int value)233{234 writel(value, p->membase + (offset << p->regshift));235 dw8250_check_lcr(p, offset, value);236}237 238static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)239{240 unsigned int value = readl(p->membase + (offset << p->regshift));241 242 return dw8250_modify_msr(p, offset, value);243}244 245static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)246{247 iowrite32be(value, p->membase + (offset << p->regshift));248 dw8250_check_lcr(p, offset, value);249}250 251static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)252{253 unsigned int value = ioread32be(p->membase + (offset << p->regshift));254 255 return dw8250_modify_msr(p, offset, value);256}257 258 259static int dw8250_handle_irq(struct uart_port *p)260{261 struct uart_8250_port *up = up_to_u8250p(p);262 struct dw8250_data *d = to_dw8250_data(p->private_data);263 unsigned int iir = p->serial_in(p, UART_IIR);264 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;265 unsigned int quirks = d->pdata->quirks;266 unsigned int status;267 unsigned long flags;268 269 /*270 * There are ways to get Designware-based UARTs into a state where271 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual272 * data available. If we see such a case then we'll do a bogus273 * read. If we don't do this then the "RX TIMEOUT" interrupt will274 * fire forever.275 *276 * This problem has only been observed so far when not in DMA mode277 * so we limit the workaround only to non-DMA mode.278 */279 if (!up->dma && rx_timeout) {280 uart_port_lock_irqsave(p, &flags);281 status = serial_lsr_in(up);282 283 if (!(status & (UART_LSR_DR | UART_LSR_BI)))284 (void) p->serial_in(p, UART_RX);285 286 uart_port_unlock_irqrestore(p, flags);287 }288 289 /* Manually stop the Rx DMA transfer when acting as flow controller */290 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {291 uart_port_lock_irqsave(p, &flags);292 status = serial_lsr_in(up);293 uart_port_unlock_irqrestore(p, flags);294 295 if (status & (UART_LSR_DR | UART_LSR_BI)) {296 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);297 dw8250_writel_ext(p, DW_UART_DMASA, 1);298 }299 }300 301 if (serial8250_handle_irq(p, iir))302 return 1;303 304 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {305 /* Clear the USR */306 (void)p->serial_in(p, d->pdata->usr_reg);307 308 return 1;309 }310 311 return 0;312}313 314static void dw8250_clk_work_cb(struct work_struct *work)315{316 struct dw8250_data *d = work_to_dw8250_data(work);317 struct uart_8250_port *up;318 unsigned long rate;319 320 rate = clk_get_rate(d->clk);321 if (rate <= 0)322 return;323 324 up = serial8250_get_port(d->data.line);325 326 serial8250_update_uartclk(&up->port, rate);327}328 329static int dw8250_clk_notifier_cb(struct notifier_block *nb,330 unsigned long event, void *data)331{332 struct dw8250_data *d = clk_to_dw8250_data(nb);333 334 /*335 * We have no choice but to defer the uartclk update due to two336 * deadlocks. First one is caused by a recursive mutex lock which337 * happens when clk_set_rate() is called from dw8250_set_termios().338 * Second deadlock is more tricky and is caused by an inverted order of339 * the clk and tty-port mutexes lock. It happens if clock rate change340 * is requested asynchronously while set_termios() is executed between341 * tty-port mutex lock and clk_set_rate() function invocation and342 * vise-versa. Anyway if we didn't have the reference clock alteration343 * in the dw8250_set_termios() method we wouldn't have needed this344 * deferred event handling complication.345 */346 if (event == POST_RATE_CHANGE) {347 queue_work(system_unbound_wq, &d->clk_work);348 return NOTIFY_OK;349 }350 351 return NOTIFY_DONE;352}353 354static void355dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)356{357 if (!state)358 pm_runtime_get_sync(port->dev);359 360 serial8250_do_pm(port, state, old);361 362 if (state)363 pm_runtime_put_sync_suspend(port->dev);364}365 366static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,367 const struct ktermios *old)368{369 unsigned long newrate = tty_termios_baud_rate(termios) * 16;370 struct dw8250_data *d = to_dw8250_data(p->private_data);371 long rate;372 int ret;373 374 clk_disable_unprepare(d->clk);375 rate = clk_round_rate(d->clk, newrate);376 if (rate > 0) {377 /*378 * Note that any clock-notifer worker will block in379 * serial8250_update_uartclk() until we are done.380 */381 ret = clk_set_rate(d->clk, newrate);382 if (!ret)383 p->uartclk = rate;384 }385 clk_prepare_enable(d->clk);386 387 dw8250_do_set_termios(p, termios, old);388}389 390static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)391{392 struct uart_8250_port *up = up_to_u8250p(p);393 unsigned int mcr = p->serial_in(p, UART_MCR);394 395 if (up->capabilities & UART_CAP_IRDA) {396 if (termios->c_line == N_IRDA)397 mcr |= DW_UART_MCR_SIRE;398 else399 mcr &= ~DW_UART_MCR_SIRE;400 401 p->serial_out(p, UART_MCR, mcr);402 }403 serial8250_do_set_ldisc(p, termios);404}405 406/*407 * dw8250_fallback_dma_filter will prevent the UART from getting just any free408 * channel on platforms that have DMA engines, but don't have any channels409 * assigned to the UART.410 *411 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the412 * core problem is fixed, this function is no longer needed.413 */414static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)415{416 return false;417}418 419static bool dw8250_idma_filter(struct dma_chan *chan, void *param)420{421 return param == chan->device->dev;422}423 424static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)425{426 if (max_burst >= 8)427 return RZN1_UART_xDMACR_8_WORD_BURST;428 else if (max_burst >= 4)429 return RZN1_UART_xDMACR_4_WORD_BURST;430 else431 return RZN1_UART_xDMACR_1_WORD_BURST;432}433 434static void dw8250_prepare_tx_dma(struct uart_8250_port *p)435{436 struct uart_port *up = &p->port;437 struct uart_8250_dma *dma = p->dma;438 u32 val;439 440 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);441 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |442 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |443 RZN1_UART_xDMACR_DMA_EN;444 dw8250_writel_ext(up, RZN1_UART_TDMACR, val);445}446 447static void dw8250_prepare_rx_dma(struct uart_8250_port *p)448{449 struct uart_port *up = &p->port;450 struct uart_8250_dma *dma = p->dma;451 u32 val;452 453 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);454 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |455 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |456 RZN1_UART_xDMACR_DMA_EN;457 dw8250_writel_ext(up, RZN1_UART_RDMACR, val);458}459 460static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)461{462 unsigned int quirks = data->pdata ? data->pdata->quirks : 0;463 u32 cpr_value = data->pdata ? data->pdata->cpr_value : 0;464 465 if (quirks & DW_UART_QUIRK_CPR_VALUE)466 data->data.cpr_value = cpr_value;467 468#ifdef CONFIG_64BIT469 if (quirks & DW_UART_QUIRK_OCTEON) {470 p->serial_in = dw8250_serial_inq;471 p->serial_out = dw8250_serial_outq;472 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;473 p->type = PORT_OCTEON;474 data->skip_autocfg = true;475 }476#endif477 478 if (quirks & DW_UART_QUIRK_ARMADA_38X)479 p->serial_out = dw8250_serial_out38x;480 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)481 p->set_termios = dw8250_do_set_termios;482 if (quirks & DW_UART_QUIRK_IS_DMA_FC) {483 data->data.dma.txconf.device_fc = 1;484 data->data.dma.rxconf.device_fc = 1;485 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;486 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;487 }488 if (quirks & DW_UART_QUIRK_APMC0D08) {489 p->iotype = UPIO_MEM32;490 p->regshift = 2;491 p->serial_in = dw8250_serial_in32;492 data->uart_16550_compatible = true;493 }494 495 /* Platforms with iDMA 64-bit */496 if (platform_get_resource_byname(to_platform_device(p->dev),497 IORESOURCE_MEM, "lpss_priv")) {498 data->data.dma.rx_param = p->dev->parent;499 data->data.dma.tx_param = p->dev->parent;500 data->data.dma.fn = dw8250_idma_filter;501 }502}503 504static void dw8250_reset_control_assert(void *data)505{506 reset_control_assert(data);507}508 509static int dw8250_probe(struct platform_device *pdev)510{511 struct uart_8250_port uart = {}, *up = &uart;512 struct uart_port *p = &up->port;513 struct device *dev = &pdev->dev;514 struct dw8250_data *data;515 struct resource *regs;516 int err;517 518 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);519 if (!regs)520 return dev_err_probe(dev, -EINVAL, "no registers defined\n");521 522 spin_lock_init(&p->lock);523 p->handle_irq = dw8250_handle_irq;524 p->pm = dw8250_do_pm;525 p->type = PORT_8250;526 p->flags = UPF_FIXED_PORT;527 p->dev = dev;528 p->set_ldisc = dw8250_set_ldisc;529 p->set_termios = dw8250_set_termios;530 531 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);532 if (!data)533 return -ENOMEM;534 535 data->data.dma.fn = dw8250_fallback_dma_filter;536 data->pdata = device_get_match_data(p->dev);537 p->private_data = &data->data;538 539 data->uart_16550_compatible = device_property_read_bool(dev,540 "snps,uart-16550-compatible");541 542 p->mapbase = regs->start;543 p->mapsize = resource_size(regs);544 545 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize);546 if (!p->membase)547 return -ENOMEM;548 549 err = uart_read_port_properties(p);550 /* no interrupt -> fall back to polling */551 if (err == -ENXIO)552 err = 0;553 if (err)554 return err;555 556 switch (p->iotype) {557 case UPIO_MEM:558 p->serial_in = dw8250_serial_in;559 p->serial_out = dw8250_serial_out;560 break;561 case UPIO_MEM32:562 p->serial_in = dw8250_serial_in32;563 p->serial_out = dw8250_serial_out32;564 break;565 case UPIO_MEM32BE:566 p->serial_in = dw8250_serial_in32be;567 p->serial_out = dw8250_serial_out32be;568 break;569 default:570 return -ENODEV;571 }572 573 if (device_property_read_bool(dev, "dcd-override")) {574 /* Always report DCD as active */575 data->msr_mask_on |= UART_MSR_DCD;576 data->msr_mask_off |= UART_MSR_DDCD;577 }578 579 if (device_property_read_bool(dev, "dsr-override")) {580 /* Always report DSR as active */581 data->msr_mask_on |= UART_MSR_DSR;582 data->msr_mask_off |= UART_MSR_DDSR;583 }584 585 if (device_property_read_bool(dev, "cts-override")) {586 /* Always report CTS as active */587 data->msr_mask_on |= UART_MSR_CTS;588 data->msr_mask_off |= UART_MSR_DCTS;589 }590 591 if (device_property_read_bool(dev, "ri-override")) {592 /* Always report Ring indicator as inactive */593 data->msr_mask_off |= UART_MSR_RI;594 data->msr_mask_off |= UART_MSR_TERI;595 }596 597 /* If there is separate baudclk, get the rate from it. */598 data->clk = devm_clk_get_optional_enabled(dev, "baudclk");599 if (data->clk == NULL)600 data->clk = devm_clk_get_optional_enabled(dev, NULL);601 if (IS_ERR(data->clk))602 return dev_err_probe(dev, PTR_ERR(data->clk),603 "failed to get baudclk\n");604 605 INIT_WORK(&data->clk_work, dw8250_clk_work_cb);606 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;607 608 if (data->clk)609 p->uartclk = clk_get_rate(data->clk);610 611 /* If no clock rate is defined, fail. */612 if (!p->uartclk)613 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");614 615 data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");616 if (IS_ERR(data->pclk))617 return PTR_ERR(data->pclk);618 619 data->rst = devm_reset_control_array_get_optional_exclusive(dev);620 if (IS_ERR(data->rst))621 return PTR_ERR(data->rst);622 623 reset_control_deassert(data->rst);624 625 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);626 if (err)627 return err;628 629 dw8250_quirks(p, data);630 631 /* If the Busy Functionality is not implemented, don't handle it */632 if (data->uart_16550_compatible)633 p->handle_irq = NULL;634 635 if (!data->skip_autocfg)636 dw8250_setup_port(p);637 638 /* If we have a valid fifosize, try hooking up DMA */639 if (p->fifosize) {640 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;641 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;642 up->dma = &data->data.dma;643 }644 645 data->data.line = serial8250_register_8250_port(up);646 if (data->data.line < 0)647 return data->data.line;648 649 /*650 * Some platforms may provide a reference clock shared between several651 * devices. In this case any clock state change must be known to the652 * UART port at least post factum.653 */654 if (data->clk) {655 err = clk_notifier_register(data->clk, &data->clk_notifier);656 if (err)657 return dev_err_probe(dev, err, "Failed to set the clock notifier\n");658 queue_work(system_unbound_wq, &data->clk_work);659 }660 661 platform_set_drvdata(pdev, data);662 663 pm_runtime_set_active(dev);664 pm_runtime_enable(dev);665 666 return 0;667}668 669static void dw8250_remove(struct platform_device *pdev)670{671 struct dw8250_data *data = platform_get_drvdata(pdev);672 struct device *dev = &pdev->dev;673 674 pm_runtime_get_sync(dev);675 676 if (data->clk) {677 clk_notifier_unregister(data->clk, &data->clk_notifier);678 679 flush_work(&data->clk_work);680 }681 682 serial8250_unregister_port(data->data.line);683 684 pm_runtime_disable(dev);685 pm_runtime_put_noidle(dev);686}687 688static int dw8250_suspend(struct device *dev)689{690 struct dw8250_data *data = dev_get_drvdata(dev);691 692 serial8250_suspend_port(data->data.line);693 694 return 0;695}696 697static int dw8250_resume(struct device *dev)698{699 struct dw8250_data *data = dev_get_drvdata(dev);700 701 serial8250_resume_port(data->data.line);702 703 return 0;704}705 706static int dw8250_runtime_suspend(struct device *dev)707{708 struct dw8250_data *data = dev_get_drvdata(dev);709 710 clk_disable_unprepare(data->clk);711 712 clk_disable_unprepare(data->pclk);713 714 return 0;715}716 717static int dw8250_runtime_resume(struct device *dev)718{719 struct dw8250_data *data = dev_get_drvdata(dev);720 721 clk_prepare_enable(data->pclk);722 723 clk_prepare_enable(data->clk);724 725 return 0;726}727 728static const struct dev_pm_ops dw8250_pm_ops = {729 SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)730 RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)731};732 733static const struct dw8250_platform_data dw8250_dw_apb = {734 .usr_reg = DW_UART_USR,735};736 737static const struct dw8250_platform_data dw8250_octeon_3860_data = {738 .usr_reg = OCTEON_UART_USR,739 .quirks = DW_UART_QUIRK_OCTEON,740};741 742static const struct dw8250_platform_data dw8250_armada_38x_data = {743 .usr_reg = DW_UART_USR,744 .quirks = DW_UART_QUIRK_ARMADA_38X,745};746 747static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {748 .usr_reg = DW_UART_USR,749 .cpr_value = 0x00012f32,750 .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,751};752 753static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {754 .usr_reg = DW_UART_USR,755 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,756};757 758static const struct of_device_id dw8250_of_match[] = {759 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },760 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },761 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },762 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },763 { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },764 { /* Sentinel */ }765};766MODULE_DEVICE_TABLE(of, dw8250_of_match);767 768static const struct dw8250_platform_data dw8250_apmc0d08 = {769 .usr_reg = DW_UART_USR,770 .quirks = DW_UART_QUIRK_APMC0D08,771};772 773static const struct acpi_device_id dw8250_acpi_match[] = {774 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },775 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },776 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },777 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },778 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },779 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },780 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },781 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },782 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },783 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },784 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },785 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },786 { "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb },787 { },788};789MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);790 791static struct platform_driver dw8250_platform_driver = {792 .driver = {793 .name = "dw-apb-uart",794 .pm = pm_ptr(&dw8250_pm_ops),795 .of_match_table = dw8250_of_match,796 .acpi_match_table = dw8250_acpi_match,797 },798 .probe = dw8250_probe,799 .remove_new = dw8250_remove,800};801 802module_platform_driver(dw8250_platform_driver);803 804MODULE_AUTHOR("Jamie Iles");805MODULE_LICENSE("GPL");806MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");807MODULE_ALIAS("platform:dw-apb-uart");808