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1// SPDX-License-Identifier: GPL-2.02/*3 * Probe module for 8250/16550-type MCHP PCI serial ports.4 *5 * Based on drivers/tty/serial/8250/8250_pci.c,6 *7 * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved.8 */9 10#include <linux/array_size.h>11#include <linux/bitfield.h>12#include <linux/bits.h>13#include <linux/circ_buf.h>14#include <linux/device.h>15#include <linux/errno.h>16#include <linux/gfp_types.h>17#include <linux/io.h>18#include <linux/iopoll.h>19#include <linux/minmax.h>20#include <linux/module.h>21#include <linux/mutex.h>22#include <linux/overflow.h>23#include <linux/pci.h>24#include <linux/pm.h>25#include <linux/serial_core.h>26#include <linux/serial_reg.h>27#include <linux/serial_8250.h>28#include <linux/spinlock.h>29#include <linux/string.h>30#include <linux/time.h>31#include <linux/tty.h>32#include <linux/tty_flip.h>33#include <linux/types.h>34#include <linux/units.h>35 36#include <asm/byteorder.h>37 38#include "8250.h"39#include "8250_pcilib.h"40 41#define PCI_DEVICE_ID_EFAR_PCI12000 0xa00242#define PCI_DEVICE_ID_EFAR_PCI11010 0xa01243#define PCI_DEVICE_ID_EFAR_PCI11101 0xa02244#define PCI_DEVICE_ID_EFAR_PCI11400 0xa03245#define PCI_DEVICE_ID_EFAR_PCI11414 0xa04246 47#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x000148#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x000249#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x000350#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x000451#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x000552#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x000653#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x000754#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x000855#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x000956#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a57#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b58#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c59#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d60#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e61#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f62 63#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI1200064#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI1101065#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI1110166#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI1140067#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI1141468 69#define UART_SYSTEM_ADDR_BASE 0x100070#define UART_DEV_REV_REG (UART_SYSTEM_ADDR_BASE + 0x00)71#define UART_DEV_REV_MASK GENMASK(7, 0)72#define UART_SYSLOCK_REG (UART_SYSTEM_ADDR_BASE + 0xA0)73#define UART_SYSLOCK BIT(2)74#define SYSLOCK_SLEEP_TIMEOUT 10075#define SYSLOCK_RETRY_CNT 100076 77#define UART_RX_BYTE_FIFO 0x0078#define UART_TX_BYTE_FIFO 0x0079#define UART_FIFO_CTL 0x0280 81#define UART_ACTV_REG 0x1182#define UART_BLOCK_SET_ACTIVE BIT(0)83 84#define UART_PCI_CTRL_REG 0x8085#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4)86#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0)87 88#define ADCL_CFG_REG 0x4089#define ADCL_CFG_POL_SEL BIT(2)90#define ADCL_CFG_PIN_SEL BIT(1)91#define ADCL_CFG_EN BIT(0)92 93#define UART_BIT_SAMPLE_CNT_8 894#define UART_BIT_SAMPLE_CNT_16 1695#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8)96#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8)97 98#define UART_WAKE_REG 0x8C99#define UART_WAKE_MASK_REG 0x90100#define UART_WAKE_N_PIN BIT(2)101#define UART_WAKE_NCTS BIT(1)102#define UART_WAKE_INT BIT(0)103#define UART_WAKE_SRCS \104 (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT)105 106#define UART_BAUD_CLK_DIVISOR_REG 0x54107#define FRAC_DIV_CFG_REG 0x58108 109#define UART_RESET_REG 0x94110#define UART_RESET_D3_RESET_DISABLE BIT(16)111 112#define UART_BURST_STATUS_REG 0x9C113#define UART_TX_BURST_FIFO 0xA0114#define UART_RX_BURST_FIFO 0xA4115 116#define UART_BIT_DIVISOR_8 0x26731000117#define UART_BIT_DIVISOR_16 0x6ef71000118#define UART_BAUD_4MBPS 4000000119 120#define MAX_PORTS 4121#define PORT_OFFSET 0x100122#define RX_BUF_SIZE 512123#define UART_BYTE_SIZE 1124#define UART_BURST_SIZE 4125 126#define UART_BST_STAT_RX_COUNT_MASK 0x00FF127#define UART_BST_STAT_TX_COUNT_MASK 0xFF00128#define UART_BST_STAT_IIR_INT_PEND 0x100000129#define UART_LSR_OVERRUN_ERR_CLR 0x43130#define UART_BST_STAT_LSR_RX_MASK 0x9F000000131#define UART_BST_STAT_LSR_RX_ERR_MASK 0x9E000000132#define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000133#define UART_BST_STAT_LSR_PARITY_ERR 0x4000000134#define UART_BST_STAT_LSR_FRAME_ERR 0x8000000135#define UART_BST_STAT_LSR_THRE 0x20000000136 137struct pci1xxxx_8250 {138 unsigned int nr;139 u8 dev_rev;140 u8 pad[3];141 void __iomem *membase;142 int line[] __counted_by(nr);143};144 145static const struct serial_rs485 pci1xxxx_rs485_supported = {146 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |147 SER_RS485_RTS_AFTER_SEND,148 .delay_rts_after_send = 1,149 /* Delay RTS before send is not supported */150};151 152static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port)153{154 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG);155 return readl(port->membase + UART_SYSLOCK_REG);156}157 158static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port)159{160 u32 regval;161 162 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval,163 (regval & UART_SYSLOCK),164 SYSLOCK_SLEEP_TIMEOUT,165 SYSLOCK_RETRY_CNT * SYSLOCK_SLEEP_TIMEOUT);166}167 168static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port)169{170 writel(0x0, port->membase + UART_SYSLOCK_REG);171}172 173static const int logical_to_physical_port_idx[][MAX_PORTS] = {174 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */175 {0, 1, 2, 3}, /* PCI4p */176 {0, 1, 2, -1}, /* PCI3p012 */177 {0, 1, 3, -1}, /* PCI3p013 */178 {0, 2, 3, -1}, /* PCI3p023 */179 {1, 2, 3, -1}, /* PCI3p123 */180 {0, 1, -1, -1}, /* PCI2p01 */181 {0, 2, -1, -1}, /* PCI2p02 */182 {0, 3, -1, -1}, /* PCI2p03 */183 {1, 2, -1, -1}, /* PCI2p12 */184 {1, 3, -1, -1}, /* PCI2p13 */185 {2, 3, -1, -1}, /* PCI2p23 */186 {0, -1, -1, -1}, /* PCI1p0 */187 {1, -1, -1, -1}, /* PCI1p1 */188 {2, -1, -1, -1}, /* PCI1p2 */189 {3, -1, -1, -1}, /* PCI1p3 */190};191 192static int pci1xxxx_get_num_ports(struct pci_dev *dev)193{194 switch (dev->subsystem_device) {195 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0:196 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1:197 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2:198 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3:199 case PCI_SUBDEVICE_ID_EFAR_PCI12000:200 case PCI_SUBDEVICE_ID_EFAR_PCI11010:201 case PCI_SUBDEVICE_ID_EFAR_PCI11101:202 case PCI_SUBDEVICE_ID_EFAR_PCI11400:203 default:204 return 1;205 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01:206 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02:207 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03:208 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12:209 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13:210 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23:211 return 2;212 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012:213 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123:214 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013:215 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023:216 return 3;217 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p:218 case PCI_SUBDEVICE_ID_EFAR_PCI11414:219 return 4;220 }221}222 223static unsigned int pci1xxxx_get_divisor(struct uart_port *port,224 unsigned int baud, unsigned int *frac)225{226 unsigned int uart_sample_cnt;227 unsigned int quot;228 229 if (baud >= UART_BAUD_4MBPS)230 uart_sample_cnt = UART_BIT_SAMPLE_CNT_8;231 else232 uart_sample_cnt = UART_BIT_SAMPLE_CNT_16;233 234 /*235 * Calculate baud rate sampling period in nanoseconds.236 * Fractional part x denotes x/255 parts of a nanosecond.237 */238 quot = NSEC_PER_SEC / (baud * uart_sample_cnt);239 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) *240 255 / uart_sample_cnt / baud;241 242 return quot;243}244 245static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,246 unsigned int quot, unsigned int frac)247{248 if (baud >= UART_BAUD_4MBPS)249 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG);250 else251 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG);252 253 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac,254 port->membase + UART_BAUD_CLK_DIVISOR_REG);255}256 257static int pci1xxxx_rs485_config(struct uart_port *port,258 struct ktermios *termios,259 struct serial_rs485 *rs485)260{261 u32 delay_in_baud_periods;262 u32 baud_period_in_ns;263 u32 mode_cfg = 0;264 u32 sample_cnt;265 u32 clock_div;266 u32 frac_div;267 268 frac_div = readl(port->membase + FRAC_DIV_CFG_REG);269 270 if (frac_div == UART_BIT_DIVISOR_16)271 sample_cnt = UART_BIT_SAMPLE_CNT_16;272 else273 sample_cnt = UART_BIT_SAMPLE_CNT_8;274 275 /*276 * pci1xxxx's uart hardware supports only RTS delay after277 * Tx and in units of bit times to a maximum of 15278 */279 if (rs485->flags & SER_RS485_ENABLED) {280 mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;281 282 if (!(rs485->flags & SER_RS485_RTS_ON_SEND))283 mode_cfg |= ADCL_CFG_POL_SEL;284 285 if (rs485->delay_rts_after_send) {286 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);287 baud_period_in_ns =288 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *289 sample_cnt;290 delay_in_baud_periods =291 rs485->delay_rts_after_send * NSEC_PER_MSEC /292 baud_period_in_ns;293 delay_in_baud_periods =294 min_t(u32, delay_in_baud_periods,295 FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));296 mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,297 delay_in_baud_periods);298 rs485->delay_rts_after_send =299 baud_period_in_ns * delay_in_baud_periods /300 NSEC_PER_MSEC;301 }302 }303 writel(mode_cfg, port->membase + ADCL_CFG_REG);304 return 0;305}306 307static u32 pci1xxxx_read_burst_status(struct uart_port *port)308{309 u32 status;310 311 status = readl(port->membase + UART_BURST_STATUS_REG);312 if (status & UART_BST_STAT_LSR_RX_ERR_MASK) {313 if (status & UART_BST_STAT_LSR_OVERRUN_ERR) {314 writeb(UART_LSR_OVERRUN_ERR_CLR,315 port->membase + UART_FIFO_CTL);316 port->icount.overrun++;317 }318 319 if (status & UART_BST_STAT_LSR_FRAME_ERR)320 port->icount.frame++;321 322 if (status & UART_BST_STAT_LSR_PARITY_ERR)323 port->icount.parity++;324 }325 return status;326}327 328static void pci1xxxx_process_read_data(struct uart_port *port,329 unsigned char *rx_buff, u32 *buff_index,330 u32 *valid_byte_count)331{332 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE;333 u32 *burst_buf;334 335 /*336 * Depending on the RX Trigger Level the number of bytes that can be337 * stored in RX FIFO at a time varies. Each transaction reads data338 * in DWORDs. If there are less than four remaining valid_byte_count339 * to read, the data is received one byte at a time.340 */341 while (valid_burst_count--) {342 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE))343 break;344 burst_buf = (u32 *)&rx_buff[*buff_index];345 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO);346 *buff_index += UART_BURST_SIZE;347 *valid_byte_count -= UART_BURST_SIZE;348 }349 350 while (*valid_byte_count) {351 if (*buff_index >= RX_BUF_SIZE)352 break;353 rx_buff[*buff_index] = readb(port->membase +354 UART_RX_BYTE_FIFO);355 *buff_index += UART_BYTE_SIZE;356 *valid_byte_count -= UART_BYTE_SIZE;357 }358}359 360static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status)361{362 u32 valid_byte_count = uart_status & UART_BST_STAT_RX_COUNT_MASK;363 struct tty_port *tty_port = &port->state->port;364 unsigned char rx_buff[RX_BUF_SIZE];365 u32 buff_index = 0;366 u32 copied_len;367 368 if (valid_byte_count != 0 &&369 valid_byte_count < RX_BUF_SIZE) {370 pci1xxxx_process_read_data(port, rx_buff, &buff_index,371 &valid_byte_count);372 373 copied_len = (u32)tty_insert_flip_string(tty_port, rx_buff,374 buff_index);375 376 if (copied_len != buff_index)377 port->icount.overrun += buff_index - copied_len;378 379 port->icount.rx += buff_index;380 tty_flip_buffer_push(tty_port);381 }382}383 384static void pci1xxxx_process_write_data(struct uart_port *port,385 int *data_empty_count,386 u32 *valid_byte_count)387{388 struct tty_port *tport = &port->state->port;389 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE;390 391 /*392 * Each transaction transfers data in DWORDs. If there are less than393 * four remaining valid_byte_count to transfer or if the circular394 * buffer has insufficient space for a DWORD, the data is transferred395 * one byte at a time.396 */397 while (valid_burst_count) {398 u32 c;399 400 if (*data_empty_count - UART_BURST_SIZE < 0)401 break;402 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE)403 break;404 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) !=405 sizeof(c)))406 break;407 writel(c, port->membase + UART_TX_BURST_FIFO);408 *valid_byte_count -= UART_BURST_SIZE;409 *data_empty_count -= UART_BURST_SIZE;410 valid_burst_count -= UART_BYTE_SIZE;411 }412 413 while (*valid_byte_count) {414 u8 c;415 416 if (!kfifo_get(&tport->xmit_fifo, &c))417 break;418 writeb(c, port->membase + UART_TX_BYTE_FIFO);419 *data_empty_count -= UART_BYTE_SIZE;420 *valid_byte_count -= UART_BYTE_SIZE;421 422 /*423 * If there are any pending burst count, data is handled by424 * transmitting DWORDs at a time.425 */426 if (valid_burst_count &&427 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE)428 break;429 }430}431 432static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status)433{434 struct uart_8250_port *up = up_to_u8250p(port);435 struct tty_port *tport = &port->state->port;436 u32 valid_byte_count;437 int data_empty_count;438 439 if (port->x_char) {440 writeb(port->x_char, port->membase + UART_TX);441 port->icount.tx++;442 port->x_char = 0;443 return;444 }445 446 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) {447 port->ops->stop_tx(port);448 } else {449 data_empty_count = (pci1xxxx_read_burst_status(port) &450 UART_BST_STAT_TX_COUNT_MASK) >> 8;451 do {452 valid_byte_count = kfifo_len(&tport->xmit_fifo);453 454 pci1xxxx_process_write_data(port,455 &data_empty_count,456 &valid_byte_count);457 458 port->icount.tx++;459 if (kfifo_is_empty(&tport->xmit_fifo))460 break;461 } while (data_empty_count && valid_byte_count);462 }463 464 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)465 uart_write_wakeup(port);466 467 /*468 * With RPM enabled, we have to wait until the FIFO is empty before469 * the HW can go idle. So we get here once again with empty FIFO and470 * disable the interrupt and RPM in __stop_tx()471 */472 if (kfifo_is_empty(&tport->xmit_fifo) &&473 !(up->capabilities & UART_CAP_RPM))474 port->ops->stop_tx(port);475}476 477static int pci1xxxx_handle_irq(struct uart_port *port)478{479 unsigned long flags;480 u32 status;481 482 status = pci1xxxx_read_burst_status(port);483 484 if (status & UART_BST_STAT_IIR_INT_PEND)485 return 0;486 487 spin_lock_irqsave(&port->lock, flags);488 489 if (status & UART_BST_STAT_LSR_RX_MASK)490 pci1xxxx_rx_burst(port, status);491 492 if (status & UART_BST_STAT_LSR_THRE)493 pci1xxxx_tx_burst(port, status);494 495 spin_unlock_irqrestore(&port->lock, flags);496 497 return 1;498}499 500static bool pci1xxxx_port_suspend(int line)501{502 struct uart_8250_port *up = serial8250_get_port(line);503 struct uart_port *port = &up->port;504 struct tty_port *tport = &port->state->port;505 unsigned long flags;506 bool ret = false;507 u8 wakeup_mask;508 509 mutex_lock(&tport->mutex);510 if (port->suspended == 0 && port->dev) {511 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);512 513 uart_port_lock_irqsave(port, &flags);514 port->mctrl &= ~TIOCM_OUT2;515 port->ops->set_mctrl(port, port->mctrl);516 uart_port_unlock_irqrestore(port, flags);517 518 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS;519 }520 521 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);522 mutex_unlock(&tport->mutex);523 524 return ret;525}526 527static void pci1xxxx_port_resume(int line)528{529 struct uart_8250_port *up = serial8250_get_port(line);530 struct uart_port *port = &up->port;531 struct tty_port *tport = &port->state->port;532 unsigned long flags;533 534 mutex_lock(&tport->mutex);535 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);536 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);537 538 if (port->suspended == 0) {539 uart_port_lock_irqsave(port, &flags);540 port->mctrl |= TIOCM_OUT2;541 port->ops->set_mctrl(port, port->mctrl);542 uart_port_unlock_irqrestore(port, flags);543 }544 mutex_unlock(&tport->mutex);545}546 547static int pci1xxxx_suspend(struct device *dev)548{549 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);550 struct pci_dev *pcidev = to_pci_dev(dev);551 bool wakeup = false;552 unsigned int data;553 void __iomem *p;554 int i;555 556 for (i = 0; i < priv->nr; i++) {557 if (priv->line[i] >= 0) {558 serial8250_suspend_port(priv->line[i]);559 wakeup |= pci1xxxx_port_suspend(priv->line[i]);560 }561 }562 563 p = pci_ioremap_bar(pcidev, 0);564 if (!p) {565 dev_err(dev, "remapping of bar 0 memory failed");566 return -ENOMEM;567 }568 569 data = readl(p + UART_RESET_REG);570 writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);571 572 if (wakeup)573 writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG);574 575 iounmap(p);576 device_set_wakeup_enable(dev, true);577 pci_wake_from_d3(pcidev, true);578 579 return 0;580}581 582static int pci1xxxx_resume(struct device *dev)583{584 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);585 struct pci_dev *pcidev = to_pci_dev(dev);586 unsigned int data;587 void __iomem *p;588 int i;589 590 p = pci_ioremap_bar(pcidev, 0);591 if (!p) {592 dev_err(dev, "remapping of bar 0 memory failed");593 return -ENOMEM;594 }595 596 data = readl(p + UART_RESET_REG);597 writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);598 iounmap(p);599 600 for (i = 0; i < priv->nr; i++) {601 if (priv->line[i] >= 0) {602 pci1xxxx_port_resume(priv->line[i]);603 serial8250_resume_port(priv->line[i]);604 }605 }606 607 return 0;608}609 610static int pci1xxxx_setup(struct pci_dev *pdev,611 struct uart_8250_port *port, int port_idx, int rev)612{613 int ret;614 615 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;616 port->port.type = PORT_MCHP16550A;617 /*618 * 8250 core considers prescaller value to be always 16.619 * The MCHP ports support downscaled mode and hence the620 * functional UART clock can be lower, i.e. 62.5MHz, than621 * software expects in order to support higher baud rates.622 * Assign here 64MHz to support 4Mbps.623 *624 * The value itself is not really used anywhere except baud625 * rate calculations, so we can mangle it as we wish.626 */627 port->port.uartclk = 64 * HZ_PER_MHZ;628 port->port.set_termios = serial8250_do_set_termios;629 port->port.get_divisor = pci1xxxx_get_divisor;630 port->port.set_divisor = pci1xxxx_set_divisor;631 port->port.rs485_config = pci1xxxx_rs485_config;632 port->port.rs485_supported = pci1xxxx_rs485_supported;633 634 /* From C0 rev Burst operation is supported */635 if (rev >= 0xC0)636 port->port.handle_irq = pci1xxxx_handle_irq;637 638 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0);639 if (ret < 0)640 return ret;641 642 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);643 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);644 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);645 646 return 0;647}648 649static unsigned int pci1xxxx_get_max_port(int subsys_dev)650{651 unsigned int i = MAX_PORTS;652 653 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))654 while (i--) {655 if (logical_to_physical_port_idx[subsys_dev][i] != -1)656 return logical_to_physical_port_idx[subsys_dev][i] + 1;657 }658 659 if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414)660 return 4;661 662 return 1;663}664 665static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port)666{667 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))668 return logical_to_physical_port_idx[subsys_dev][port];669 670 return logical_to_physical_port_idx[0][port];671}672 673static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv)674{675 u32 regval;676 int ret;677 678 /*679 * DEV REV is a system register, HW Syslock bit680 * should be acquired before accessing the register681 */682 ret = pci1xxxx_acquire_sys_lock(priv);683 if (ret)684 return ret;685 686 regval = readl(priv->membase + UART_DEV_REV_REG);687 priv->dev_rev = regval & UART_DEV_REV_MASK;688 689 pci1xxxx_release_sys_lock(priv);690 691 return 0;692}693 694static int pci1xxxx_serial_probe(struct pci_dev *pdev,695 const struct pci_device_id *id)696{697 struct device *dev = &pdev->dev;698 struct pci1xxxx_8250 *priv;699 struct uart_8250_port uart;700 unsigned int max_vec_reqd;701 unsigned int nr_ports, i;702 int num_vectors;703 int subsys_dev;704 int port_idx;705 int ret;706 int rc;707 708 rc = pcim_enable_device(pdev);709 if (rc)710 return rc;711 712 nr_ports = pci1xxxx_get_num_ports(pdev);713 714 priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL);715 if (!priv)716 return -ENOMEM;717 718 priv->membase = pci_ioremap_bar(pdev, 0);719 if (!priv->membase)720 return -ENOMEM;721 722 ret = pci1xxxx_get_device_revision(priv);723 if (ret)724 return ret;725 726 pci_set_master(pdev);727 728 priv->nr = nr_ports;729 730 subsys_dev = pdev->subsystem_device;731 max_vec_reqd = pci1xxxx_get_max_port(subsys_dev);732 733 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES);734 if (num_vectors < 0) {735 pci_iounmap(pdev, priv->membase);736 return num_vectors;737 }738 739 memset(&uart, 0, sizeof(uart));740 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;741 uart.port.dev = dev;742 743 if (num_vectors == max_vec_reqd)744 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);745 746 for (i = 0; i < nr_ports; i++) {747 priv->line[i] = -ENODEV;748 749 port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i);750 751 if (num_vectors == max_vec_reqd)752 uart.port.irq = pci_irq_vector(pdev, port_idx);753 else754 uart.port.irq = pci_irq_vector(pdev, 0);755 756 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev);757 if (rc) {758 dev_warn(dev, "Failed to setup port %u\n", i);759 continue;760 }761 762 priv->line[i] = serial8250_register_8250_port(&uart);763 if (priv->line[i] < 0) {764 dev_warn(dev,765 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",766 uart.port.iobase, uart.port.irq, uart.port.iotype,767 priv->line[i]);768 }769 }770 771 pci_set_drvdata(pdev, priv);772 773 return 0;774}775 776static void pci1xxxx_serial_remove(struct pci_dev *dev)777{778 struct pci1xxxx_8250 *priv = pci_get_drvdata(dev);779 unsigned int i;780 781 for (i = 0; i < priv->nr; i++) {782 if (priv->line[i] >= 0)783 serial8250_unregister_port(priv->line[i]);784 }785 786 pci_free_irq_vectors(dev);787 pci_iounmap(dev, priv->membase);788}789 790static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume);791 792static const struct pci_device_id pci1xxxx_pci_tbl[] = {793 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) },794 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) },795 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) },796 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) },797 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) },798 {}799};800MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl);801 802static struct pci_driver pci1xxxx_pci_driver = {803 .name = "pci1xxxx serial",804 .probe = pci1xxxx_serial_probe,805 .remove = pci1xxxx_serial_remove,806 .driver = {807 .pm = pm_sleep_ptr(&pci1xxxx_pm_ops),808 },809 .id_table = pci1xxxx_pci_tbl,810};811module_pci_driver(pci1xxxx_pci_driver);812 813static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1));814 815MODULE_IMPORT_NS(SERIAL_8250_PCI);816MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module");817MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");818MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>");819MODULE_LICENSE("GPL");820