brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0+2/*3 *  Driver for AMBA serial ports4 *5 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.6 *7 *  Copyright 1999 ARM Limited8 *  Copyright (C) 2000 Deep Blue Solutions Ltd.9 *  Copyright (C) 2010 ST-Ericsson SA10 *11 * This is a generic driver for ARM AMBA-type serial ports.  They12 * have a lot of 16550-like features, but are not register compatible.13 * Note that although they do have CTS, DCD and DSR inputs, they do14 * not have an RI input, nor do they have DTR or RTS outputs.  If15 * required, these have to be supplied via some other means (eg, GPIO)16 * and hooked into this driver.17 */18 19#include <linux/module.h>20#include <linux/ioport.h>21#include <linux/init.h>22#include <linux/console.h>23#include <linux/platform_device.h>24#include <linux/sysrq.h>25#include <linux/device.h>26#include <linux/tty.h>27#include <linux/tty_flip.h>28#include <linux/serial_core.h>29#include <linux/serial.h>30#include <linux/amba/bus.h>31#include <linux/amba/serial.h>32#include <linux/clk.h>33#include <linux/slab.h>34#include <linux/dmaengine.h>35#include <linux/dma-mapping.h>36#include <linux/scatterlist.h>37#include <linux/delay.h>38#include <linux/types.h>39#include <linux/of.h>40#include <linux/pinctrl/consumer.h>41#include <linux/sizes.h>42#include <linux/io.h>43#include <linux/acpi.h>44 45#define UART_NR			1446 47#define SERIAL_AMBA_MAJOR	20448#define SERIAL_AMBA_MINOR	6449#define SERIAL_AMBA_NR		UART_NR50 51#define AMBA_ISR_PASS_LIMIT	25652 53#define UART_DR_ERROR		(UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE)54#define UART_DUMMY_DR_RX	BIT(16)55 56enum {57	REG_DR,58	REG_ST_DMAWM,59	REG_ST_TIMEOUT,60	REG_FR,61	REG_LCRH_RX,62	REG_LCRH_TX,63	REG_IBRD,64	REG_FBRD,65	REG_CR,66	REG_IFLS,67	REG_IMSC,68	REG_RIS,69	REG_MIS,70	REG_ICR,71	REG_DMACR,72	REG_ST_XFCR,73	REG_ST_XON1,74	REG_ST_XON2,75	REG_ST_XOFF1,76	REG_ST_XOFF2,77	REG_ST_ITCR,78	REG_ST_ITIP,79	REG_ST_ABCR,80	REG_ST_ABIMSC,81 82	/* The size of the array - must be last */83	REG_ARRAY_SIZE,84};85 86static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {87	[REG_DR] = UART01x_DR,88	[REG_FR] = UART01x_FR,89	[REG_LCRH_RX] = UART011_LCRH,90	[REG_LCRH_TX] = UART011_LCRH,91	[REG_IBRD] = UART011_IBRD,92	[REG_FBRD] = UART011_FBRD,93	[REG_CR] = UART011_CR,94	[REG_IFLS] = UART011_IFLS,95	[REG_IMSC] = UART011_IMSC,96	[REG_RIS] = UART011_RIS,97	[REG_MIS] = UART011_MIS,98	[REG_ICR] = UART011_ICR,99	[REG_DMACR] = UART011_DMACR,100};101 102/* There is by now at least one vendor with differing details, so handle it */103struct vendor_data {104	const u16		*reg_offset;105	unsigned int		ifls;106	unsigned int		fr_busy;107	unsigned int		fr_dsr;108	unsigned int		fr_cts;109	unsigned int		fr_ri;110	unsigned int		inv_fr;111	bool			access_32b;112	bool			oversampling;113	bool			dma_threshold;114	bool			cts_event_workaround;115	bool			always_enabled;116	bool			fixed_options;117 118	unsigned int (*get_fifosize)(struct amba_device *dev);119};120 121static unsigned int get_fifosize_arm(struct amba_device *dev)122{123	return amba_rev(dev) < 3 ? 16 : 32;124}125 126static struct vendor_data vendor_arm = {127	.reg_offset		= pl011_std_offsets,128	.ifls			= UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,129	.fr_busy		= UART01x_FR_BUSY,130	.fr_dsr			= UART01x_FR_DSR,131	.fr_cts			= UART01x_FR_CTS,132	.fr_ri			= UART011_FR_RI,133	.oversampling		= false,134	.dma_threshold		= false,135	.cts_event_workaround	= false,136	.always_enabled		= false,137	.fixed_options		= false,138	.get_fifosize		= get_fifosize_arm,139};140 141static const struct vendor_data vendor_sbsa = {142	.reg_offset		= pl011_std_offsets,143	.fr_busy		= UART01x_FR_BUSY,144	.fr_dsr			= UART01x_FR_DSR,145	.fr_cts			= UART01x_FR_CTS,146	.fr_ri			= UART011_FR_RI,147	.access_32b		= true,148	.oversampling		= false,149	.dma_threshold		= false,150	.cts_event_workaround	= false,151	.always_enabled		= true,152	.fixed_options		= true,153};154 155#ifdef CONFIG_ACPI_SPCR_TABLE156static const struct vendor_data vendor_qdt_qdf2400_e44 = {157	.reg_offset		= pl011_std_offsets,158	.fr_busy		= UART011_FR_TXFE,159	.fr_dsr			= UART01x_FR_DSR,160	.fr_cts			= UART01x_FR_CTS,161	.fr_ri			= UART011_FR_RI,162	.inv_fr			= UART011_FR_TXFE,163	.access_32b		= true,164	.oversampling		= false,165	.dma_threshold		= false,166	.cts_event_workaround	= false,167	.always_enabled		= true,168	.fixed_options		= true,169};170#endif171 172static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {173	[REG_DR] = UART01x_DR,174	[REG_ST_DMAWM] = ST_UART011_DMAWM,175	[REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,176	[REG_FR] = UART01x_FR,177	[REG_LCRH_RX] = ST_UART011_LCRH_RX,178	[REG_LCRH_TX] = ST_UART011_LCRH_TX,179	[REG_IBRD] = UART011_IBRD,180	[REG_FBRD] = UART011_FBRD,181	[REG_CR] = UART011_CR,182	[REG_IFLS] = UART011_IFLS,183	[REG_IMSC] = UART011_IMSC,184	[REG_RIS] = UART011_RIS,185	[REG_MIS] = UART011_MIS,186	[REG_ICR] = UART011_ICR,187	[REG_DMACR] = UART011_DMACR,188	[REG_ST_XFCR] = ST_UART011_XFCR,189	[REG_ST_XON1] = ST_UART011_XON1,190	[REG_ST_XON2] = ST_UART011_XON2,191	[REG_ST_XOFF1] = ST_UART011_XOFF1,192	[REG_ST_XOFF2] = ST_UART011_XOFF2,193	[REG_ST_ITCR] = ST_UART011_ITCR,194	[REG_ST_ITIP] = ST_UART011_ITIP,195	[REG_ST_ABCR] = ST_UART011_ABCR,196	[REG_ST_ABIMSC] = ST_UART011_ABIMSC,197};198 199static unsigned int get_fifosize_st(struct amba_device *dev)200{201	return 64;202}203 204static struct vendor_data vendor_st = {205	.reg_offset		= pl011_st_offsets,206	.ifls			= UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF,207	.fr_busy		= UART01x_FR_BUSY,208	.fr_dsr			= UART01x_FR_DSR,209	.fr_cts			= UART01x_FR_CTS,210	.fr_ri			= UART011_FR_RI,211	.oversampling		= true,212	.dma_threshold		= true,213	.cts_event_workaround	= true,214	.always_enabled		= false,215	.fixed_options		= false,216	.get_fifosize		= get_fifosize_st,217};218 219/* Deals with DMA transactions */220 221struct pl011_dmabuf {222	dma_addr_t		dma;223	size_t			len;224	char			*buf;225};226 227struct pl011_dmarx_data {228	struct dma_chan		*chan;229	struct completion	complete;230	bool			use_buf_b;231	struct pl011_dmabuf	dbuf_a;232	struct pl011_dmabuf	dbuf_b;233	dma_cookie_t		cookie;234	bool			running;235	struct timer_list	timer;236	unsigned int last_residue;237	unsigned long last_jiffies;238	bool auto_poll_rate;239	unsigned int poll_rate;240	unsigned int poll_timeout;241};242 243struct pl011_dmatx_data {244	struct dma_chan		*chan;245	dma_addr_t		dma;246	size_t			len;247	char			*buf;248	bool			queued;249};250 251/*252 * We wrap our port structure around the generic uart_port.253 */254struct uart_amba_port {255	struct uart_port	port;256	const u16		*reg_offset;257	struct clk		*clk;258	const struct vendor_data *vendor;259	unsigned int		im;		/* interrupt mask */260	unsigned int		old_status;261	unsigned int		fifosize;	/* vendor-specific */262	unsigned int		fixed_baud;	/* vendor-set fixed baud rate */263	char			type[12];264	bool			rs485_tx_started;265	unsigned int		rs485_tx_drain_interval; /* usecs */266#ifdef CONFIG_DMA_ENGINE267	/* DMA stuff */268	unsigned int		dmacr;		/* dma control reg */269	bool			using_tx_dma;270	bool			using_rx_dma;271	struct pl011_dmarx_data dmarx;272	struct pl011_dmatx_data	dmatx;273	bool			dma_probed;274#endif275};276 277static unsigned int pl011_tx_empty(struct uart_port *port);278 279static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,280					unsigned int reg)281{282	return uap->reg_offset[reg];283}284 285static unsigned int pl011_read(const struct uart_amba_port *uap,286			       unsigned int reg)287{288	void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);289 290	return (uap->port.iotype == UPIO_MEM32) ?291		readl_relaxed(addr) : readw_relaxed(addr);292}293 294static void pl011_write(unsigned int val, const struct uart_amba_port *uap,295			unsigned int reg)296{297	void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);298 299	if (uap->port.iotype == UPIO_MEM32)300		writel_relaxed(val, addr);301	else302		writew_relaxed(val, addr);303}304 305/*306 * Reads up to 256 characters from the FIFO or until it's empty and307 * inserts them into the TTY layer. Returns the number of characters308 * read from the FIFO.309 */310static int pl011_fifo_to_tty(struct uart_amba_port *uap)311{312	unsigned int ch, fifotaken;313	int sysrq;314	u16 status;315	u8 flag;316 317	for (fifotaken = 0; fifotaken != 256; fifotaken++) {318		status = pl011_read(uap, REG_FR);319		if (status & UART01x_FR_RXFE)320			break;321 322		/* Take chars from the FIFO and update status */323		ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;324		flag = TTY_NORMAL;325		uap->port.icount.rx++;326 327		if (unlikely(ch & UART_DR_ERROR)) {328			if (ch & UART011_DR_BE) {329				ch &= ~(UART011_DR_FE | UART011_DR_PE);330				uap->port.icount.brk++;331				if (uart_handle_break(&uap->port))332					continue;333			} else if (ch & UART011_DR_PE) {334				uap->port.icount.parity++;335			} else if (ch & UART011_DR_FE) {336				uap->port.icount.frame++;337			}338			if (ch & UART011_DR_OE)339				uap->port.icount.overrun++;340 341			ch &= uap->port.read_status_mask;342 343			if (ch & UART011_DR_BE)344				flag = TTY_BREAK;345			else if (ch & UART011_DR_PE)346				flag = TTY_PARITY;347			else if (ch & UART011_DR_FE)348				flag = TTY_FRAME;349		}350 351		sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255);352		if (!sysrq)353			uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);354	}355 356	return fifotaken;357}358 359/*360 * All the DMA operation mode stuff goes inside this ifdef.361 * This assumes that you have a generic DMA device interface,362 * no custom DMA interfaces are supported.363 */364#ifdef CONFIG_DMA_ENGINE365 366#define PL011_DMA_BUFFER_SIZE PAGE_SIZE367 368static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,369			     enum dma_data_direction dir)370{371	db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,372				     &db->dma, GFP_KERNEL);373	if (!db->buf)374		return -ENOMEM;375	db->len = PL011_DMA_BUFFER_SIZE;376 377	return 0;378}379 380static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,381			      enum dma_data_direction dir)382{383	if (db->buf) {384		dma_free_coherent(chan->device->dev,385				  PL011_DMA_BUFFER_SIZE, db->buf, db->dma);386	}387}388 389static void pl011_dma_probe(struct uart_amba_port *uap)390{391	/* DMA is the sole user of the platform data right now */392	struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);393	struct device *dev = uap->port.dev;394	struct dma_slave_config tx_conf = {395		.dst_addr = uap->port.mapbase +396				 pl011_reg_to_offset(uap, REG_DR),397		.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,398		.direction = DMA_MEM_TO_DEV,399		.dst_maxburst = uap->fifosize >> 1,400		.device_fc = false,401	};402	struct dma_chan *chan;403	dma_cap_mask_t mask;404 405	uap->dma_probed = true;406	chan = dma_request_chan(dev, "tx");407	if (IS_ERR(chan)) {408		if (PTR_ERR(chan) == -EPROBE_DEFER) {409			uap->dma_probed = false;410			return;411		}412 413		/* We need platform data */414		if (!plat || !plat->dma_filter) {415			dev_dbg(uap->port.dev, "no DMA platform data\n");416			return;417		}418 419		/* Try to acquire a generic DMA engine slave TX channel */420		dma_cap_zero(mask);421		dma_cap_set(DMA_SLAVE, mask);422 423		chan = dma_request_channel(mask, plat->dma_filter,424					   plat->dma_tx_param);425		if (!chan) {426			dev_err(uap->port.dev, "no TX DMA channel!\n");427			return;428		}429	}430 431	dmaengine_slave_config(chan, &tx_conf);432	uap->dmatx.chan = chan;433 434	dev_info(uap->port.dev, "DMA channel TX %s\n",435		 dma_chan_name(uap->dmatx.chan));436 437	/* Optionally make use of an RX channel as well */438	chan = dma_request_chan(dev, "rx");439 440	if (IS_ERR(chan) && plat && plat->dma_rx_param) {441		chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);442 443		if (!chan) {444			dev_err(uap->port.dev, "no RX DMA channel!\n");445			return;446		}447	}448 449	if (!IS_ERR(chan)) {450		struct dma_slave_config rx_conf = {451			.src_addr = uap->port.mapbase +452				pl011_reg_to_offset(uap, REG_DR),453			.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,454			.direction = DMA_DEV_TO_MEM,455			.src_maxburst = uap->fifosize >> 2,456			.device_fc = false,457		};458		struct dma_slave_caps caps;459 460		/*461		 * Some DMA controllers provide information on their capabilities.462		 * If the controller does, check for suitable residue processing463		 * otherwise assime all is well.464		 */465		if (dma_get_slave_caps(chan, &caps) == 0) {466			if (caps.residue_granularity ==467					DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {468				dma_release_channel(chan);469				dev_info(uap->port.dev,470					 "RX DMA disabled - no residue processing\n");471				return;472			}473		}474		dmaengine_slave_config(chan, &rx_conf);475		uap->dmarx.chan = chan;476 477		uap->dmarx.auto_poll_rate = false;478		if (plat && plat->dma_rx_poll_enable) {479			/* Set poll rate if specified. */480			if (plat->dma_rx_poll_rate) {481				uap->dmarx.auto_poll_rate = false;482				uap->dmarx.poll_rate = plat->dma_rx_poll_rate;483			} else {484				/*485				 * 100 ms defaults to poll rate if not486				 * specified. This will be adjusted with487				 * the baud rate at set_termios.488				 */489				uap->dmarx.auto_poll_rate = true;490				uap->dmarx.poll_rate =  100;491			}492			/* 3 secs defaults poll_timeout if not specified. */493			if (plat->dma_rx_poll_timeout)494				uap->dmarx.poll_timeout =495					plat->dma_rx_poll_timeout;496			else497				uap->dmarx.poll_timeout = 3000;498		} else if (!plat && dev->of_node) {499			uap->dmarx.auto_poll_rate =500					of_property_read_bool(dev->of_node, "auto-poll");501			if (uap->dmarx.auto_poll_rate) {502				u32 x;503 504				if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0)505					uap->dmarx.poll_rate = x;506				else507					uap->dmarx.poll_rate = 100;508				if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0)509					uap->dmarx.poll_timeout = x;510				else511					uap->dmarx.poll_timeout = 3000;512			}513		}514		dev_info(uap->port.dev, "DMA channel RX %s\n",515			 dma_chan_name(uap->dmarx.chan));516	}517}518 519static void pl011_dma_remove(struct uart_amba_port *uap)520{521	if (uap->dmatx.chan)522		dma_release_channel(uap->dmatx.chan);523	if (uap->dmarx.chan)524		dma_release_channel(uap->dmarx.chan);525}526 527/* Forward declare these for the refill routine */528static int pl011_dma_tx_refill(struct uart_amba_port *uap);529static void pl011_start_tx_pio(struct uart_amba_port *uap);530 531/*532 * The current DMA TX buffer has been sent.533 * Try to queue up another DMA buffer.534 */535static void pl011_dma_tx_callback(void *data)536{537	struct uart_amba_port *uap = data;538	struct tty_port *tport = &uap->port.state->port;539	struct pl011_dmatx_data *dmatx = &uap->dmatx;540	unsigned long flags;541	u16 dmacr;542 543	uart_port_lock_irqsave(&uap->port, &flags);544	if (uap->dmatx.queued)545		dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,546				 dmatx->len, DMA_TO_DEVICE);547 548	dmacr = uap->dmacr;549	uap->dmacr = dmacr & ~UART011_TXDMAE;550	pl011_write(uap->dmacr, uap, REG_DMACR);551 552	/*553	 * If TX DMA was disabled, it means that we've stopped the DMA for554	 * some reason (eg, XOFF received, or we want to send an X-char.)555	 *556	 * Note: we need to be careful here of a potential race between DMA557	 * and the rest of the driver - if the driver disables TX DMA while558	 * a TX buffer completing, we must update the tx queued status to559	 * get further refills (hence we check dmacr).560	 */561	if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||562	    kfifo_is_empty(&tport->xmit_fifo)) {563		uap->dmatx.queued = false;564		uart_port_unlock_irqrestore(&uap->port, flags);565		return;566	}567 568	if (pl011_dma_tx_refill(uap) <= 0)569		/*570		 * We didn't queue a DMA buffer for some reason, but we571		 * have data pending to be sent.  Re-enable the TX IRQ.572		 */573		pl011_start_tx_pio(uap);574 575	uart_port_unlock_irqrestore(&uap->port, flags);576}577 578/*579 * Try to refill the TX DMA buffer.580 * Locking: called with port lock held and IRQs disabled.581 * Returns:582 *   1 if we queued up a TX DMA buffer.583 *   0 if we didn't want to handle this by DMA584 *  <0 on error585 */586static int pl011_dma_tx_refill(struct uart_amba_port *uap)587{588	struct pl011_dmatx_data *dmatx = &uap->dmatx;589	struct dma_chan *chan = dmatx->chan;590	struct dma_device *dma_dev = chan->device;591	struct dma_async_tx_descriptor *desc;592	struct tty_port *tport = &uap->port.state->port;593	unsigned int count;594 595	/*596	 * Try to avoid the overhead involved in using DMA if the597	 * transaction fits in the first half of the FIFO, by using598	 * the standard interrupt handling.  This ensures that we599	 * issue a uart_write_wakeup() at the appropriate time.600	 */601	count = kfifo_len(&tport->xmit_fifo);602	if (count < (uap->fifosize >> 1)) {603		uap->dmatx.queued = false;604		return 0;605	}606 607	/*608	 * Bodge: don't send the last character by DMA, as this609	 * will prevent XON from notifying us to restart DMA.610	 */611	count -= 1;612 613	/* Else proceed to copy the TX chars to the DMA buffer and fire DMA */614	if (count > PL011_DMA_BUFFER_SIZE)615		count = PL011_DMA_BUFFER_SIZE;616 617	count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count);618	dmatx->len = count;619	dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,620				    DMA_TO_DEVICE);621	if (dmatx->dma == DMA_MAPPING_ERROR) {622		uap->dmatx.queued = false;623		dev_dbg(uap->port.dev, "unable to map TX DMA\n");624		return -EBUSY;625	}626 627	desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,628					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);629	if (!desc) {630		dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);631		uap->dmatx.queued = false;632		/*633		 * If DMA cannot be used right now, we complete this634		 * transaction via IRQ and let the TTY layer retry.635		 */636		dev_dbg(uap->port.dev, "TX DMA busy\n");637		return -EBUSY;638	}639 640	/* Some data to go along to the callback */641	desc->callback = pl011_dma_tx_callback;642	desc->callback_param = uap;643 644	/* All errors should happen at prepare time */645	dmaengine_submit(desc);646 647	/* Fire the DMA transaction */648	dma_dev->device_issue_pending(chan);649 650	uap->dmacr |= UART011_TXDMAE;651	pl011_write(uap->dmacr, uap, REG_DMACR);652	uap->dmatx.queued = true;653 654	/*655	 * Now we know that DMA will fire, so advance the ring buffer656	 * with the stuff we just dispatched.657	 */658	uart_xmit_advance(&uap->port, count);659 660	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)661		uart_write_wakeup(&uap->port);662 663	return 1;664}665 666/*667 * We received a transmit interrupt without a pending X-char but with668 * pending characters.669 * Locking: called with port lock held and IRQs disabled.670 * Returns:671 *   false if we want to use PIO to transmit672 *   true if we queued a DMA buffer673 */674static bool pl011_dma_tx_irq(struct uart_amba_port *uap)675{676	if (!uap->using_tx_dma)677		return false;678 679	/*680	 * If we already have a TX buffer queued, but received a681	 * TX interrupt, it will be because we've just sent an X-char.682	 * Ensure the TX DMA is enabled and the TX IRQ is disabled.683	 */684	if (uap->dmatx.queued) {685		uap->dmacr |= UART011_TXDMAE;686		pl011_write(uap->dmacr, uap, REG_DMACR);687		uap->im &= ~UART011_TXIM;688		pl011_write(uap->im, uap, REG_IMSC);689		return true;690	}691 692	/*693	 * We don't have a TX buffer queued, so try to queue one.694	 * If we successfully queued a buffer, mask the TX IRQ.695	 */696	if (pl011_dma_tx_refill(uap) > 0) {697		uap->im &= ~UART011_TXIM;698		pl011_write(uap->im, uap, REG_IMSC);699		return true;700	}701	return false;702}703 704/*705 * Stop the DMA transmit (eg, due to received XOFF).706 * Locking: called with port lock held and IRQs disabled.707 */708static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)709{710	if (uap->dmatx.queued) {711		uap->dmacr &= ~UART011_TXDMAE;712		pl011_write(uap->dmacr, uap, REG_DMACR);713	}714}715 716/*717 * Try to start a DMA transmit, or in the case of an XON/OFF718 * character queued for send, try to get that character out ASAP.719 * Locking: called with port lock held and IRQs disabled.720 * Returns:721 *   false if we want the TX IRQ to be enabled722 *   true if we have a buffer queued723 */724static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)725{726	u16 dmacr;727 728	if (!uap->using_tx_dma)729		return false;730 731	if (!uap->port.x_char) {732		/* no X-char, try to push chars out in DMA mode */733		bool ret = true;734 735		if (!uap->dmatx.queued) {736			if (pl011_dma_tx_refill(uap) > 0) {737				uap->im &= ~UART011_TXIM;738				pl011_write(uap->im, uap, REG_IMSC);739			} else {740				ret = false;741			}742		} else if (!(uap->dmacr & UART011_TXDMAE)) {743			uap->dmacr |= UART011_TXDMAE;744			pl011_write(uap->dmacr, uap, REG_DMACR);745		}746		return ret;747	}748 749	/*750	 * We have an X-char to send.  Disable DMA to prevent it loading751	 * the TX fifo, and then see if we can stuff it into the FIFO.752	 */753	dmacr = uap->dmacr;754	uap->dmacr &= ~UART011_TXDMAE;755	pl011_write(uap->dmacr, uap, REG_DMACR);756 757	if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {758		/*759		 * No space in the FIFO, so enable the transmit interrupt760		 * so we know when there is space.  Note that once we've761		 * loaded the character, we should just re-enable DMA.762		 */763		return false;764	}765 766	pl011_write(uap->port.x_char, uap, REG_DR);767	uap->port.icount.tx++;768	uap->port.x_char = 0;769 770	/* Success - restore the DMA state */771	uap->dmacr = dmacr;772	pl011_write(dmacr, uap, REG_DMACR);773 774	return true;775}776 777/*778 * Flush the transmit buffer.779 * Locking: called with port lock held and IRQs disabled.780 */781static void pl011_dma_flush_buffer(struct uart_port *port)782__releases(&uap->port.lock)783__acquires(&uap->port.lock)784{785	struct uart_amba_port *uap =786	    container_of(port, struct uart_amba_port, port);787 788	if (!uap->using_tx_dma)789		return;790 791	dmaengine_terminate_async(uap->dmatx.chan);792 793	if (uap->dmatx.queued) {794		dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,795				 uap->dmatx.len, DMA_TO_DEVICE);796		uap->dmatx.queued = false;797		uap->dmacr &= ~UART011_TXDMAE;798		pl011_write(uap->dmacr, uap, REG_DMACR);799	}800}801 802static void pl011_dma_rx_callback(void *data);803 804static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)805{806	struct dma_chan *rxchan = uap->dmarx.chan;807	struct pl011_dmarx_data *dmarx = &uap->dmarx;808	struct dma_async_tx_descriptor *desc;809	struct pl011_dmabuf *dbuf;810 811	if (!rxchan)812		return -EIO;813 814	/* Start the RX DMA job */815	dbuf = uap->dmarx.use_buf_b ?816		&uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;817	desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,818					   DMA_DEV_TO_MEM,819					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);820	/*821	 * If the DMA engine is busy and cannot prepare a822	 * channel, no big deal, the driver will fall back823	 * to interrupt mode as a result of this error code.824	 */825	if (!desc) {826		uap->dmarx.running = false;827		dmaengine_terminate_all(rxchan);828		return -EBUSY;829	}830 831	/* Some data to go along to the callback */832	desc->callback = pl011_dma_rx_callback;833	desc->callback_param = uap;834	dmarx->cookie = dmaengine_submit(desc);835	dma_async_issue_pending(rxchan);836 837	uap->dmacr |= UART011_RXDMAE;838	pl011_write(uap->dmacr, uap, REG_DMACR);839	uap->dmarx.running = true;840 841	uap->im &= ~UART011_RXIM;842	pl011_write(uap->im, uap, REG_IMSC);843 844	return 0;845}846 847/*848 * This is called when either the DMA job is complete, or849 * the FIFO timeout interrupt occurred. This must be called850 * with the port spinlock uap->port.lock held.851 */852static void pl011_dma_rx_chars(struct uart_amba_port *uap,853			       u32 pending, bool use_buf_b,854			       bool readfifo)855{856	struct tty_port *port = &uap->port.state->port;857	struct pl011_dmabuf *dbuf = use_buf_b ?858		&uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;859	int dma_count = 0;860	u32 fifotaken = 0; /* only used for vdbg() */861 862	struct pl011_dmarx_data *dmarx = &uap->dmarx;863	int dmataken = 0;864 865	if (uap->dmarx.poll_rate) {866		/* The data can be taken by polling */867		dmataken = dbuf->len - dmarx->last_residue;868		/* Recalculate the pending size */869		if (pending >= dmataken)870			pending -= dmataken;871	}872 873	/* Pick the remain data from the DMA */874	if (pending) {875		/*876		 * First take all chars in the DMA pipe, then look in the FIFO.877		 * Note that tty_insert_flip_buf() tries to take as many chars878		 * as it can.879		 */880		dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending);881 882		uap->port.icount.rx += dma_count;883		if (dma_count < pending)884			dev_warn(uap->port.dev,885				 "couldn't insert all characters (TTY is full?)\n");886	}887 888	/* Reset the last_residue for Rx DMA poll */889	if (uap->dmarx.poll_rate)890		dmarx->last_residue = dbuf->len;891 892	/*893	 * Only continue with trying to read the FIFO if all DMA chars have894	 * been taken first.895	 */896	if (dma_count == pending && readfifo) {897		/* Clear any error flags */898		pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |899			    UART011_FEIS, uap, REG_ICR);900 901		/*902		 * If we read all the DMA'd characters, and we had an903		 * incomplete buffer, that could be due to an rx error, or904		 * maybe we just timed out. Read any pending chars and check905		 * the error status.906		 *907		 * Error conditions will only occur in the FIFO, these will908		 * trigger an immediate interrupt and stop the DMA job, so we909		 * will always find the error in the FIFO, never in the DMA910		 * buffer.911		 */912		fifotaken = pl011_fifo_to_tty(uap);913	}914 915	dev_vdbg(uap->port.dev,916		 "Took %d chars from DMA buffer and %d chars from the FIFO\n",917		 dma_count, fifotaken);918	tty_flip_buffer_push(port);919}920 921static void pl011_dma_rx_irq(struct uart_amba_port *uap)922{923	struct pl011_dmarx_data *dmarx = &uap->dmarx;924	struct dma_chan *rxchan = dmarx->chan;925	struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?926		&dmarx->dbuf_b : &dmarx->dbuf_a;927	size_t pending;928	struct dma_tx_state state;929	enum dma_status dmastat;930 931	/*932	 * Pause the transfer so we can trust the current counter,933	 * do this before we pause the PL011 block, else we may934	 * overflow the FIFO.935	 */936	if (dmaengine_pause(rxchan))937		dev_err(uap->port.dev, "unable to pause DMA transfer\n");938	dmastat = rxchan->device->device_tx_status(rxchan,939						   dmarx->cookie, &state);940	if (dmastat != DMA_PAUSED)941		dev_err(uap->port.dev, "unable to pause DMA transfer\n");942 943	/* Disable RX DMA - incoming data will wait in the FIFO */944	uap->dmacr &= ~UART011_RXDMAE;945	pl011_write(uap->dmacr, uap, REG_DMACR);946	uap->dmarx.running = false;947 948	pending = dbuf->len - state.residue;949	BUG_ON(pending > PL011_DMA_BUFFER_SIZE);950	/* Then we terminate the transfer - we now know our residue */951	dmaengine_terminate_all(rxchan);952 953	/*954	 * This will take the chars we have so far and insert955	 * into the framework.956	 */957	pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);958 959	/* Switch buffer & re-trigger DMA job */960	dmarx->use_buf_b = !dmarx->use_buf_b;961	if (pl011_dma_rx_trigger_dma(uap)) {962		dev_dbg(uap->port.dev,963			"could not retrigger RX DMA job fall back to interrupt mode\n");964		uap->im |= UART011_RXIM;965		pl011_write(uap->im, uap, REG_IMSC);966	}967}968 969static void pl011_dma_rx_callback(void *data)970{971	struct uart_amba_port *uap = data;972	struct pl011_dmarx_data *dmarx = &uap->dmarx;973	struct dma_chan *rxchan = dmarx->chan;974	bool lastbuf = dmarx->use_buf_b;975	struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?976		&dmarx->dbuf_b : &dmarx->dbuf_a;977	size_t pending;978	struct dma_tx_state state;979	int ret;980 981	/*982	 * This completion interrupt occurs typically when the983	 * RX buffer is totally stuffed but no timeout has yet984	 * occurred. When that happens, we just want the RX985	 * routine to flush out the secondary DMA buffer while986	 * we immediately trigger the next DMA job.987	 */988	uart_port_lock_irq(&uap->port);989	/*990	 * Rx data can be taken by the UART interrupts during991	 * the DMA irq handler. So we check the residue here.992	 */993	rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);994	pending = dbuf->len - state.residue;995	BUG_ON(pending > PL011_DMA_BUFFER_SIZE);996	/* Then we terminate the transfer - we now know our residue */997	dmaengine_terminate_all(rxchan);998 999	uap->dmarx.running = false;1000	dmarx->use_buf_b = !lastbuf;1001	ret = pl011_dma_rx_trigger_dma(uap);1002 1003	pl011_dma_rx_chars(uap, pending, lastbuf, false);1004	uart_unlock_and_check_sysrq(&uap->port);1005	/*1006	 * Do this check after we picked the DMA chars so we don't1007	 * get some IRQ immediately from RX.1008	 */1009	if (ret) {1010		dev_dbg(uap->port.dev,1011			"could not retrigger RX DMA job fall back to interrupt mode\n");1012		uap->im |= UART011_RXIM;1013		pl011_write(uap->im, uap, REG_IMSC);1014	}1015}1016 1017/*1018 * Stop accepting received characters, when we're shutting down or1019 * suspending this port.1020 * Locking: called with port lock held and IRQs disabled.1021 */1022static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)1023{1024	if (!uap->using_rx_dma)1025		return;1026 1027	/* FIXME.  Just disable the DMA enable */1028	uap->dmacr &= ~UART011_RXDMAE;1029	pl011_write(uap->dmacr, uap, REG_DMACR);1030}1031 1032/*1033 * Timer handler for Rx DMA polling.1034 * Every polling, It checks the residue in the dma buffer and transfer1035 * data to the tty. Also, last_residue is updated for the next polling.1036 */1037static void pl011_dma_rx_poll(struct timer_list *t)1038{1039	struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);1040	struct tty_port *port = &uap->port.state->port;1041	struct pl011_dmarx_data *dmarx = &uap->dmarx;1042	struct dma_chan *rxchan = uap->dmarx.chan;1043	unsigned long flags;1044	unsigned int dmataken = 0;1045	unsigned int size = 0;1046	struct pl011_dmabuf *dbuf;1047	int dma_count;1048	struct dma_tx_state state;1049 1050	dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;1051	rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);1052	if (likely(state.residue < dmarx->last_residue)) {1053		dmataken = dbuf->len - dmarx->last_residue;1054		size = dmarx->last_residue - state.residue;1055		dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,1056						   size);1057		if (dma_count == size)1058			dmarx->last_residue =  state.residue;1059		dmarx->last_jiffies = jiffies;1060	}1061	tty_flip_buffer_push(port);1062 1063	/*1064	 * If no data is received in poll_timeout, the driver will fall back1065	 * to interrupt mode. We will retrigger DMA at the first interrupt.1066	 */1067	if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)1068			> uap->dmarx.poll_timeout) {1069		uart_port_lock_irqsave(&uap->port, &flags);1070		pl011_dma_rx_stop(uap);1071		uap->im |= UART011_RXIM;1072		pl011_write(uap->im, uap, REG_IMSC);1073		uart_port_unlock_irqrestore(&uap->port, flags);1074 1075		uap->dmarx.running = false;1076		dmaengine_terminate_all(rxchan);1077		del_timer(&uap->dmarx.timer);1078	} else {1079		mod_timer(&uap->dmarx.timer,1080			  jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));1081	}1082}1083 1084static void pl011_dma_startup(struct uart_amba_port *uap)1085{1086	int ret;1087 1088	if (!uap->dma_probed)1089		pl011_dma_probe(uap);1090 1091	if (!uap->dmatx.chan)1092		return;1093 1094	uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);1095	if (!uap->dmatx.buf) {1096		uap->port.fifosize = uap->fifosize;1097		return;1098	}1099 1100	uap->dmatx.len = PL011_DMA_BUFFER_SIZE;1101 1102	/* The DMA buffer is now the FIFO the TTY subsystem can use */1103	uap->port.fifosize = PL011_DMA_BUFFER_SIZE;1104	uap->using_tx_dma = true;1105 1106	if (!uap->dmarx.chan)1107		goto skip_rx;1108 1109	/* Allocate and map DMA RX buffers */1110	ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,1111				DMA_FROM_DEVICE);1112	if (ret) {1113		dev_err(uap->port.dev, "failed to init DMA %s: %d\n",1114			"RX buffer A", ret);1115		goto skip_rx;1116	}1117 1118	ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,1119				DMA_FROM_DEVICE);1120	if (ret) {1121		dev_err(uap->port.dev, "failed to init DMA %s: %d\n",1122			"RX buffer B", ret);1123		pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,1124				  DMA_FROM_DEVICE);1125		goto skip_rx;1126	}1127 1128	uap->using_rx_dma = true;1129 1130skip_rx:1131	/* Turn on DMA error (RX/TX will be enabled on demand) */1132	uap->dmacr |= UART011_DMAONERR;1133	pl011_write(uap->dmacr, uap, REG_DMACR);1134 1135	/*1136	 * ST Micro variants has some specific dma burst threshold1137	 * compensation. Set this to 16 bytes, so burst will only1138	 * be issued above/below 16 bytes.1139	 */1140	if (uap->vendor->dma_threshold)1141		pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,1142			    uap, REG_ST_DMAWM);1143 1144	if (uap->using_rx_dma) {1145		if (pl011_dma_rx_trigger_dma(uap))1146			dev_dbg(uap->port.dev,1147				"could not trigger initial RX DMA job, fall back to interrupt mode\n");1148		if (uap->dmarx.poll_rate) {1149			timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);1150			mod_timer(&uap->dmarx.timer,1151				  jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));1152			uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;1153			uap->dmarx.last_jiffies = jiffies;1154		}1155	}1156}1157 1158static void pl011_dma_shutdown(struct uart_amba_port *uap)1159{1160	if (!(uap->using_tx_dma || uap->using_rx_dma))1161		return;1162 1163	/* Disable RX and TX DMA */1164	while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)1165		cpu_relax();1166 1167	uart_port_lock_irq(&uap->port);1168	uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);1169	pl011_write(uap->dmacr, uap, REG_DMACR);1170	uart_port_unlock_irq(&uap->port);1171 1172	if (uap->using_tx_dma) {1173		/* In theory, this should already be done by pl011_dma_flush_buffer */1174		dmaengine_terminate_all(uap->dmatx.chan);1175		if (uap->dmatx.queued) {1176			dma_unmap_single(uap->dmatx.chan->device->dev,1177					 uap->dmatx.dma, uap->dmatx.len,1178					 DMA_TO_DEVICE);1179			uap->dmatx.queued = false;1180		}1181 1182		kfree(uap->dmatx.buf);1183		uap->using_tx_dma = false;1184	}1185 1186	if (uap->using_rx_dma) {1187		dmaengine_terminate_all(uap->dmarx.chan);1188		/* Clean up the RX DMA */1189		pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);1190		pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);1191		if (uap->dmarx.poll_rate)1192			del_timer_sync(&uap->dmarx.timer);1193		uap->using_rx_dma = false;1194	}1195}1196 1197static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)1198{1199	return uap->using_rx_dma;1200}1201 1202static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)1203{1204	return uap->using_rx_dma && uap->dmarx.running;1205}1206 1207#else1208/* Blank functions if the DMA engine is not available */1209static inline void pl011_dma_remove(struct uart_amba_port *uap)1210{1211}1212 1213static inline void pl011_dma_startup(struct uart_amba_port *uap)1214{1215}1216 1217static inline void pl011_dma_shutdown(struct uart_amba_port *uap)1218{1219}1220 1221static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)1222{1223	return false;1224}1225 1226static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)1227{1228}1229 1230static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)1231{1232	return false;1233}1234 1235static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)1236{1237}1238 1239static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)1240{1241}1242 1243static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)1244{1245	return -EIO;1246}1247 1248static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)1249{1250	return false;1251}1252 1253static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)1254{1255	return false;1256}1257 1258#define pl011_dma_flush_buffer	NULL1259#endif1260 1261static void pl011_rs485_tx_stop(struct uart_amba_port *uap)1262{1263	/*1264	 * To be on the safe side only time out after twice as many iterations1265	 * as fifo size.1266	 */1267	const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;1268	struct uart_port *port = &uap->port;1269	int i = 0;1270	u32 cr;1271 1272	/* Wait until hardware tx queue is empty */1273	while (!pl011_tx_empty(port)) {1274		if (i > MAX_TX_DRAIN_ITERS) {1275			dev_warn(port->dev,1276				 "timeout while draining hardware tx queue\n");1277			break;1278		}1279 1280		udelay(uap->rs485_tx_drain_interval);1281		i++;1282	}1283 1284	if (port->rs485.delay_rts_after_send)1285		mdelay(port->rs485.delay_rts_after_send);1286 1287	cr = pl011_read(uap, REG_CR);1288 1289	if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)1290		cr &= ~UART011_CR_RTS;1291	else1292		cr |= UART011_CR_RTS;1293 1294	/* Disable the transmitter and reenable the transceiver */1295	cr &= ~UART011_CR_TXE;1296	cr |= UART011_CR_RXE;1297	pl011_write(cr, uap, REG_CR);1298 1299	uap->rs485_tx_started = false;1300}1301 1302static void pl011_stop_tx(struct uart_port *port)1303{1304	struct uart_amba_port *uap =1305	    container_of(port, struct uart_amba_port, port);1306 1307	uap->im &= ~UART011_TXIM;1308	pl011_write(uap->im, uap, REG_IMSC);1309	pl011_dma_tx_stop(uap);1310 1311	if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)1312		pl011_rs485_tx_stop(uap);1313}1314 1315static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);1316 1317/* Start TX with programmed I/O only (no DMA) */1318static void pl011_start_tx_pio(struct uart_amba_port *uap)1319{1320	if (pl011_tx_chars(uap, false)) {1321		uap->im |= UART011_TXIM;1322		pl011_write(uap->im, uap, REG_IMSC);1323	}1324}1325 1326static void pl011_rs485_tx_start(struct uart_amba_port *uap)1327{1328	struct uart_port *port = &uap->port;1329	u32 cr;1330 1331	/* Enable transmitter */1332	cr = pl011_read(uap, REG_CR);1333	cr |= UART011_CR_TXE;1334 1335	/* Disable receiver if half-duplex */1336	if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))1337		cr &= ~UART011_CR_RXE;1338 1339	if (port->rs485.flags & SER_RS485_RTS_ON_SEND)1340		cr &= ~UART011_CR_RTS;1341	else1342		cr |= UART011_CR_RTS;1343 1344	pl011_write(cr, uap, REG_CR);1345 1346	if (port->rs485.delay_rts_before_send)1347		mdelay(port->rs485.delay_rts_before_send);1348 1349	uap->rs485_tx_started = true;1350}1351 1352static void pl011_start_tx(struct uart_port *port)1353{1354	struct uart_amba_port *uap =1355	    container_of(port, struct uart_amba_port, port);1356 1357	if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&1358	    !uap->rs485_tx_started)1359		pl011_rs485_tx_start(uap);1360 1361	if (!pl011_dma_tx_start(uap))1362		pl011_start_tx_pio(uap);1363}1364 1365static void pl011_stop_rx(struct uart_port *port)1366{1367	struct uart_amba_port *uap =1368	    container_of(port, struct uart_amba_port, port);1369 1370	uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM |1371		     UART011_PEIM | UART011_BEIM | UART011_OEIM);1372	pl011_write(uap->im, uap, REG_IMSC);1373 1374	pl011_dma_rx_stop(uap);1375}1376 1377static void pl011_throttle_rx(struct uart_port *port)1378{1379	unsigned long flags;1380 1381	uart_port_lock_irqsave(port, &flags);1382	pl011_stop_rx(port);1383	uart_port_unlock_irqrestore(port, flags);1384}1385 1386static void pl011_enable_ms(struct uart_port *port)1387{1388	struct uart_amba_port *uap =1389	    container_of(port, struct uart_amba_port, port);1390 1391	uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM;1392	pl011_write(uap->im, uap, REG_IMSC);1393}1394 1395static void pl011_rx_chars(struct uart_amba_port *uap)1396__releases(&uap->port.lock)1397__acquires(&uap->port.lock)1398{1399	pl011_fifo_to_tty(uap);1400 1401	uart_port_unlock(&uap->port);1402	tty_flip_buffer_push(&uap->port.state->port);1403	/*1404	 * If we were temporarily out of DMA mode for a while,1405	 * attempt to switch back to DMA mode again.1406	 */1407	if (pl011_dma_rx_available(uap)) {1408		if (pl011_dma_rx_trigger_dma(uap)) {1409			dev_dbg(uap->port.dev,1410				"could not trigger RX DMA job fall back to interrupt mode again\n");1411			uap->im |= UART011_RXIM;1412			pl011_write(uap->im, uap, REG_IMSC);1413		} else {1414#ifdef CONFIG_DMA_ENGINE1415			/* Start Rx DMA poll */1416			if (uap->dmarx.poll_rate) {1417				uap->dmarx.last_jiffies = jiffies;1418				uap->dmarx.last_residue	= PL011_DMA_BUFFER_SIZE;1419				mod_timer(&uap->dmarx.timer,1420					  jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));1421			}1422#endif1423		}1424	}1425	uart_port_lock(&uap->port);1426}1427 1428static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,1429			  bool from_irq)1430{1431	if (unlikely(!from_irq) &&1432	    pl011_read(uap, REG_FR) & UART01x_FR_TXFF)1433		return false; /* unable to transmit character */1434 1435	pl011_write(c, uap, REG_DR);1436	uap->port.icount.tx++;1437 1438	return true;1439}1440 1441/* Returns true if tx interrupts have to be (kept) enabled  */1442static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)1443{1444	struct tty_port *tport = &uap->port.state->port;1445	int count = uap->fifosize >> 1;1446 1447	if (uap->port.x_char) {1448		if (!pl011_tx_char(uap, uap->port.x_char, from_irq))1449			return true;1450		uap->port.x_char = 0;1451		--count;1452	}1453	if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) {1454		pl011_stop_tx(&uap->port);1455		return false;1456	}1457 1458	/* If we are using DMA mode, try to send some characters. */1459	if (pl011_dma_tx_irq(uap))1460		return true;1461 1462	while (1) {1463		unsigned char c;1464 1465		if (likely(from_irq) && count-- == 0)1466			break;1467 1468		if (!kfifo_peek(&tport->xmit_fifo, &c))1469			break;1470 1471		if (!pl011_tx_char(uap, c, from_irq))1472			break;1473 1474		kfifo_skip(&tport->xmit_fifo);1475	}1476 1477	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)1478		uart_write_wakeup(&uap->port);1479 1480	if (kfifo_is_empty(&tport->xmit_fifo)) {1481		pl011_stop_tx(&uap->port);1482		return false;1483	}1484	return true;1485}1486 1487static void pl011_modem_status(struct uart_amba_port *uap)1488{1489	unsigned int status, delta;1490 1491	status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;1492 1493	delta = status ^ uap->old_status;1494	uap->old_status = status;1495 1496	if (!delta)1497		return;1498 1499	if (delta & UART01x_FR_DCD)1500		uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);1501 1502	if (delta & uap->vendor->fr_dsr)1503		uap->port.icount.dsr++;1504 1505	if (delta & uap->vendor->fr_cts)1506		uart_handle_cts_change(&uap->port,1507				       status & uap->vendor->fr_cts);1508 1509	wake_up_interruptible(&uap->port.state->port.delta_msr_wait);1510}1511 1512static void check_apply_cts_event_workaround(struct uart_amba_port *uap)1513{1514	if (!uap->vendor->cts_event_workaround)1515		return;1516 1517	/* workaround to make sure that all bits are unlocked.. */1518	pl011_write(0x00, uap, REG_ICR);1519 1520	/*1521	 * WA: introduce 26ns(1 uart clk) delay before W1C;1522	 * single apb access will incur 2 pclk(133.12Mhz) delay,1523	 * so add 2 dummy reads1524	 */1525	pl011_read(uap, REG_ICR);1526	pl011_read(uap, REG_ICR);1527}1528 1529static irqreturn_t pl011_int(int irq, void *dev_id)1530{1531	struct uart_amba_port *uap = dev_id;1532	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;1533	int handled = 0;1534 1535	uart_port_lock(&uap->port);1536	status = pl011_read(uap, REG_RIS) & uap->im;1537	if (status) {1538		do {1539			check_apply_cts_event_workaround(uap);1540 1541			pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),1542				    uap, REG_ICR);1543 1544			if (status & (UART011_RTIS | UART011_RXIS)) {1545				if (pl011_dma_rx_running(uap))1546					pl011_dma_rx_irq(uap);1547				else1548					pl011_rx_chars(uap);1549			}1550			if (status & (UART011_DSRMIS | UART011_DCDMIS |1551				      UART011_CTSMIS | UART011_RIMIS))1552				pl011_modem_status(uap);1553			if (status & UART011_TXIS)1554				pl011_tx_chars(uap, true);1555 1556			if (pass_counter-- == 0)1557				break;1558 1559			status = pl011_read(uap, REG_RIS) & uap->im;1560		} while (status != 0);1561		handled = 1;1562	}1563 1564	uart_unlock_and_check_sysrq(&uap->port);1565 1566	return IRQ_RETVAL(handled);1567}1568 1569static unsigned int pl011_tx_empty(struct uart_port *port)1570{1571	struct uart_amba_port *uap =1572	    container_of(port, struct uart_amba_port, port);1573 1574	/* Allow feature register bits to be inverted to work around errata */1575	unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;1576 1577	return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?1578							0 : TIOCSER_TEMT;1579}1580 1581static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask)1582{1583	if (cond)1584		*ptr |= mask;1585}1586 1587static unsigned int pl011_get_mctrl(struct uart_port *port)1588{1589	struct uart_amba_port *uap =1590	    container_of(port, struct uart_amba_port, port);1591	unsigned int result = 0;1592	unsigned int status = pl011_read(uap, REG_FR);1593 1594	pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR);1595	pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR);1596	pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS);1597	pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG);1598 1599	return result;1600}1601 1602static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask)1603{1604	if (cond)1605		*ptr |= mask;1606	else1607		*ptr &= ~mask;1608}1609 1610static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)1611{1612	struct uart_amba_port *uap =1613	    container_of(port, struct uart_amba_port, port);1614	unsigned int cr;1615 1616	cr = pl011_read(uap, REG_CR);1617 1618	pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS);1619	pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR);1620	pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1);1621	pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2);1622	pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE);1623 1624	if (port->status & UPSTAT_AUTORTS) {1625		/* We need to disable auto-RTS if we want to turn RTS off */1626		pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN);1627	}1628 1629	pl011_write(cr, uap, REG_CR);1630}1631 1632static void pl011_break_ctl(struct uart_port *port, int break_state)1633{1634	struct uart_amba_port *uap =1635	    container_of(port, struct uart_amba_port, port);1636	unsigned long flags;1637	unsigned int lcr_h;1638 1639	uart_port_lock_irqsave(&uap->port, &flags);1640	lcr_h = pl011_read(uap, REG_LCRH_TX);1641	if (break_state == -1)1642		lcr_h |= UART01x_LCRH_BRK;1643	else1644		lcr_h &= ~UART01x_LCRH_BRK;1645	pl011_write(lcr_h, uap, REG_LCRH_TX);1646	uart_port_unlock_irqrestore(&uap->port, flags);1647}1648 1649#ifdef CONFIG_CONSOLE_POLL1650 1651static void pl011_quiesce_irqs(struct uart_port *port)1652{1653	struct uart_amba_port *uap =1654	    container_of(port, struct uart_amba_port, port);1655 1656	pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);1657	/*1658	 * There is no way to clear TXIM as this is "ready to transmit IRQ", so1659	 * we simply mask it. start_tx() will unmask it.1660	 *1661	 * Note we can race with start_tx(), and if the race happens, the1662	 * polling user might get another interrupt just after we clear it.1663	 * But it should be OK and can happen even w/o the race, e.g.1664	 * controller immediately got some new data and raised the IRQ.1665	 *1666	 * And whoever uses polling routines assumes that it manages the device1667	 * (including tx queue), so we're also fine with start_tx()'s caller1668	 * side.1669	 */1670	pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,1671		    REG_IMSC);1672}1673 1674static int pl011_get_poll_char(struct uart_port *port)1675{1676	struct uart_amba_port *uap =1677	    container_of(port, struct uart_amba_port, port);1678	unsigned int status;1679 1680	/*1681	 * The caller might need IRQs lowered, e.g. if used with KDB NMI1682	 * debugger.1683	 */1684	pl011_quiesce_irqs(port);1685 1686	status = pl011_read(uap, REG_FR);1687	if (status & UART01x_FR_RXFE)1688		return NO_POLL_CHAR;1689 1690	return pl011_read(uap, REG_DR);1691}1692 1693static void pl011_put_poll_char(struct uart_port *port, unsigned char ch)1694{1695	struct uart_amba_port *uap =1696	    container_of(port, struct uart_amba_port, port);1697 1698	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)1699		cpu_relax();1700 1701	pl011_write(ch, uap, REG_DR);1702}1703 1704#endif /* CONFIG_CONSOLE_POLL */1705 1706static int pl011_hwinit(struct uart_port *port)1707{1708	struct uart_amba_port *uap =1709	    container_of(port, struct uart_amba_port, port);1710	int retval;1711 1712	/* Optionaly enable pins to be muxed in and configured */1713	pinctrl_pm_select_default_state(port->dev);1714 1715	/*1716	 * Try to enable the clock producer.1717	 */1718	retval = clk_prepare_enable(uap->clk);1719	if (retval)1720		return retval;1721 1722	uap->port.uartclk = clk_get_rate(uap->clk);1723 1724	/* Clear pending error and receive interrupts */1725	pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |1726		    UART011_FEIS | UART011_RTIS | UART011_RXIS,1727		    uap, REG_ICR);1728 1729	/*1730	 * Save interrupts enable mask, and enable RX interrupts in case if1731	 * the interrupt is used for NMI entry.1732	 */1733	uap->im = pl011_read(uap, REG_IMSC);1734	pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);1735 1736	if (dev_get_platdata(uap->port.dev)) {1737		struct amba_pl011_data *plat;1738 1739		plat = dev_get_platdata(uap->port.dev);1740		if (plat->init)1741			plat->init();1742	}1743	return 0;1744}1745 1746static bool pl011_split_lcrh(const struct uart_amba_port *uap)1747{1748	return pl011_reg_to_offset(uap, REG_LCRH_RX) !=1749	       pl011_reg_to_offset(uap, REG_LCRH_TX);1750}1751 1752static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)1753{1754	pl011_write(lcr_h, uap, REG_LCRH_RX);1755	if (pl011_split_lcrh(uap)) {1756		int i;1757		/*1758		 * Wait 10 PCLKs before writing LCRH_TX register,1759		 * to get this delay write read only register 10 times1760		 */1761		for (i = 0; i < 10; ++i)1762			pl011_write(0xff, uap, REG_MIS);1763		pl011_write(lcr_h, uap, REG_LCRH_TX);1764	}1765}1766 1767static int pl011_allocate_irq(struct uart_amba_port *uap)1768{1769	pl011_write(uap->im, uap, REG_IMSC);1770 1771	return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);1772}1773 1774/*1775 * Enable interrupts, only timeouts when using DMA1776 * if initial RX DMA job failed, start in interrupt mode1777 * as well.1778 */1779static void pl011_enable_interrupts(struct uart_amba_port *uap)1780{1781	unsigned long flags;1782	unsigned int i;1783 1784	uart_port_lock_irqsave(&uap->port, &flags);1785 1786	/* Clear out any spuriously appearing RX interrupts */1787	pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);1788 1789	/*1790	 * RXIS is asserted only when the RX FIFO transitions from below1791	 * to above the trigger threshold.  If the RX FIFO is already1792	 * full to the threshold this can't happen and RXIS will now be1793	 * stuck off.  Drain the RX FIFO explicitly to fix this:1794	 */1795	for (i = 0; i < uap->fifosize * 2; ++i) {1796		if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)1797			break;1798 1799		pl011_read(uap, REG_DR);1800	}1801 1802	uap->im = UART011_RTIM;1803	if (!pl011_dma_rx_running(uap))1804		uap->im |= UART011_RXIM;1805	pl011_write(uap->im, uap, REG_IMSC);1806	uart_port_unlock_irqrestore(&uap->port, flags);1807}1808 1809static void pl011_unthrottle_rx(struct uart_port *port)1810{1811	struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);1812	unsigned long flags;1813 1814	uart_port_lock_irqsave(&uap->port, &flags);1815 1816	uap->im = UART011_RTIM;1817	if (!pl011_dma_rx_running(uap))1818		uap->im |= UART011_RXIM;1819 1820	pl011_write(uap->im, uap, REG_IMSC);1821 1822	uart_port_unlock_irqrestore(&uap->port, flags);1823}1824 1825static int pl011_startup(struct uart_port *port)1826{1827	struct uart_amba_port *uap =1828	    container_of(port, struct uart_amba_port, port);1829	unsigned int cr;1830	int retval;1831 1832	retval = pl011_hwinit(port);1833	if (retval)1834		goto clk_dis;1835 1836	retval = pl011_allocate_irq(uap);1837	if (retval)1838		goto clk_dis;1839 1840	pl011_write(uap->vendor->ifls, uap, REG_IFLS);1841 1842	uart_port_lock_irq(&uap->port);1843 1844	cr = pl011_read(uap, REG_CR);1845	cr &= UART011_CR_RTS | UART011_CR_DTR;1846	cr |= UART01x_CR_UARTEN | UART011_CR_RXE;1847 1848	if (!(port->rs485.flags & SER_RS485_ENABLED))1849		cr |= UART011_CR_TXE;1850 1851	pl011_write(cr, uap, REG_CR);1852 1853	uart_port_unlock_irq(&uap->port);1854 1855	/*1856	 * initialise the old status of the modem signals1857	 */1858	uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;1859 1860	/* Startup DMA */1861	pl011_dma_startup(uap);1862 1863	pl011_enable_interrupts(uap);1864 1865	return 0;1866 1867 clk_dis:1868	clk_disable_unprepare(uap->clk);1869	return retval;1870}1871 1872static int sbsa_uart_startup(struct uart_port *port)1873{1874	struct uart_amba_port *uap =1875		container_of(port, struct uart_amba_port, port);1876	int retval;1877 1878	retval = pl011_hwinit(port);1879	if (retval)1880		return retval;1881 1882	retval = pl011_allocate_irq(uap);1883	if (retval)1884		return retval;1885 1886	/* The SBSA UART does not support any modem status lines. */1887	uap->old_status = 0;1888 1889	pl011_enable_interrupts(uap);1890 1891	return 0;1892}1893 1894static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh)1895{1896	unsigned long val;1897 1898	val = pl011_read(uap, lcrh);1899	val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);1900	pl011_write(val, uap, lcrh);1901}1902 1903/*1904 * disable the port. It should not disable RTS and DTR.1905 * Also RTS and DTR state should be preserved to restore1906 * it during startup().1907 */1908static void pl011_disable_uart(struct uart_amba_port *uap)1909{1910	unsigned int cr;1911 1912	uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);1913	uart_port_lock_irq(&uap->port);1914	cr = pl011_read(uap, REG_CR);1915	cr &= UART011_CR_RTS | UART011_CR_DTR;1916	cr |= UART01x_CR_UARTEN | UART011_CR_TXE;1917	pl011_write(cr, uap, REG_CR);1918	uart_port_unlock_irq(&uap->port);1919 1920	/*1921	 * disable break condition and fifos1922	 */1923	pl011_shutdown_channel(uap, REG_LCRH_RX);1924	if (pl011_split_lcrh(uap))1925		pl011_shutdown_channel(uap, REG_LCRH_TX);1926}1927 1928static void pl011_disable_interrupts(struct uart_amba_port *uap)1929{1930	uart_port_lock_irq(&uap->port);1931 1932	/* mask all interrupts and clear all pending ones */1933	uap->im = 0;1934	pl011_write(uap->im, uap, REG_IMSC);1935	pl011_write(0xffff, uap, REG_ICR);1936 1937	uart_port_unlock_irq(&uap->port);1938}1939 1940static void pl011_shutdown(struct uart_port *port)1941{1942	struct uart_amba_port *uap =1943		container_of(port, struct uart_amba_port, port);1944 1945	pl011_disable_interrupts(uap);1946 1947	pl011_dma_shutdown(uap);1948 1949	if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)1950		pl011_rs485_tx_stop(uap);1951 1952	free_irq(uap->port.irq, uap);1953 1954	pl011_disable_uart(uap);1955 1956	/*1957	 * Shut down the clock producer1958	 */1959	clk_disable_unprepare(uap->clk);1960	/* Optionally let pins go into sleep states */1961	pinctrl_pm_select_sleep_state(port->dev);1962 1963	if (dev_get_platdata(uap->port.dev)) {1964		struct amba_pl011_data *plat;1965 1966		plat = dev_get_platdata(uap->port.dev);1967		if (plat->exit)1968			plat->exit();1969	}1970 1971	if (uap->port.ops->flush_buffer)1972		uap->port.ops->flush_buffer(port);1973}1974 1975static void sbsa_uart_shutdown(struct uart_port *port)1976{1977	struct uart_amba_port *uap =1978		container_of(port, struct uart_amba_port, port);1979 1980	pl011_disable_interrupts(uap);1981 1982	free_irq(uap->port.irq, uap);1983 1984	if (uap->port.ops->flush_buffer)1985		uap->port.ops->flush_buffer(port);1986}1987 1988static void1989pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)1990{1991	port->read_status_mask = UART011_DR_OE | 255;1992	if (termios->c_iflag & INPCK)1993		port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;1994	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))1995		port->read_status_mask |= UART011_DR_BE;1996 1997	/*1998	 * Characters to ignore1999	 */2000	port->ignore_status_mask = 0;2001	if (termios->c_iflag & IGNPAR)2002		port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;2003	if (termios->c_iflag & IGNBRK) {2004		port->ignore_status_mask |= UART011_DR_BE;2005		/*2006		 * If we're ignoring parity and break indicators,2007		 * ignore overruns too (for real raw support).2008		 */2009		if (termios->c_iflag & IGNPAR)2010			port->ignore_status_mask |= UART011_DR_OE;2011	}2012 2013	/*2014	 * Ignore all characters if CREAD is not set.2015	 */2016	if ((termios->c_cflag & CREAD) == 0)2017		port->ignore_status_mask |= UART_DUMMY_DR_RX;2018}2019 2020static void2021pl011_set_termios(struct uart_port *port, struct ktermios *termios,2022		  const struct ktermios *old)2023{2024	struct uart_amba_port *uap =2025	    container_of(port, struct uart_amba_port, port);2026	unsigned int lcr_h, old_cr;2027	unsigned long flags;2028	unsigned int baud, quot, clkdiv;2029	unsigned int bits;2030 2031	if (uap->vendor->oversampling)2032		clkdiv = 8;2033	else2034		clkdiv = 16;2035 2036	/*2037	 * Ask the core to calculate the divisor for us.2038	 */2039	baud = uart_get_baud_rate(port, termios, old, 0,2040				  port->uartclk / clkdiv);2041#ifdef CONFIG_DMA_ENGINE2042	/*2043	 * Adjust RX DMA polling rate with baud rate if not specified.2044	 */2045	if (uap->dmarx.auto_poll_rate)2046		uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);2047#endif2048 2049	if (baud > port->uartclk / 16)2050		quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);2051	else2052		quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);2053 2054	switch (termios->c_cflag & CSIZE) {2055	case CS5:2056		lcr_h = UART01x_LCRH_WLEN_5;2057		break;2058	case CS6:2059		lcr_h = UART01x_LCRH_WLEN_6;2060		break;2061	case CS7:2062		lcr_h = UART01x_LCRH_WLEN_7;2063		break;2064	default: // CS82065		lcr_h = UART01x_LCRH_WLEN_8;2066		break;2067	}2068	if (termios->c_cflag & CSTOPB)2069		lcr_h |= UART01x_LCRH_STP2;2070	if (termios->c_cflag & PARENB) {2071		lcr_h |= UART01x_LCRH_PEN;2072		if (!(termios->c_cflag & PARODD))2073			lcr_h |= UART01x_LCRH_EPS;2074		if (termios->c_cflag & CMSPAR)2075			lcr_h |= UART011_LCRH_SPS;2076	}2077	if (uap->fifosize > 1)2078		lcr_h |= UART01x_LCRH_FEN;2079 2080	bits = tty_get_frame_size(termios->c_cflag);2081 2082	uart_port_lock_irqsave(port, &flags);2083 2084	/*2085	 * Update the per-port timeout.2086	 */2087	uart_update_timeout(port, termios->c_cflag, baud);2088 2089	/*2090	 * Calculate the approximated time it takes to transmit one character2091	 * with the given baud rate. We use this as the poll interval when we2092	 * wait for the tx queue to empty.2093	 */2094	uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);2095 2096	pl011_setup_status_masks(port, termios);2097 2098	if (UART_ENABLE_MS(port, termios->c_cflag))2099		pl011_enable_ms(port);2100 2101	if (port->rs485.flags & SER_RS485_ENABLED)2102		termios->c_cflag &= ~CRTSCTS;2103 2104	old_cr = pl011_read(uap, REG_CR);2105 2106	if (termios->c_cflag & CRTSCTS) {2107		if (old_cr & UART011_CR_RTS)2108			old_cr |= UART011_CR_RTSEN;2109 2110		old_cr |= UART011_CR_CTSEN;2111		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;2112	} else {2113		old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);2114		port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);2115	}2116 2117	if (uap->vendor->oversampling) {2118		if (baud > port->uartclk / 16)2119			old_cr |= ST_UART011_CR_OVSFACT;2120		else2121			old_cr &= ~ST_UART011_CR_OVSFACT;2122	}2123 2124	/*2125	 * Workaround for the ST Micro oversampling variants to2126	 * increase the bitrate slightly, by lowering the divisor,2127	 * to avoid delayed sampling of start bit at high speeds,2128	 * else we see data corruption.2129	 */2130	if (uap->vendor->oversampling) {2131		if (baud >= 3000000 && baud < 3250000 && quot > 1)2132			quot -= 1;2133		else if (baud > 3250000 && quot > 2)2134			quot -= 2;2135	}2136	/* Set baud rate */2137	pl011_write(quot & 0x3f, uap, REG_FBRD);2138	pl011_write(quot >> 6, uap, REG_IBRD);2139 2140	/*2141	 * ----------v----------v----------v----------v-----2142	 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER2143	 * REG_FBRD & REG_IBRD.2144	 * ----------^----------^----------^----------^-----2145	 */2146	pl011_write_lcr_h(uap, lcr_h);2147 2148	/*2149	 * Receive was disabled by pl011_disable_uart during shutdown.2150	 * Need to reenable receive if you need to use a tty_driver2151	 * returns from tty_find_polling_driver() after a port shutdown.2152	 */2153	old_cr |= UART011_CR_RXE;2154	pl011_write(old_cr, uap, REG_CR);2155 2156	uart_port_unlock_irqrestore(port, flags);2157}2158 2159static void2160sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,2161		      const struct ktermios *old)2162{2163	struct uart_amba_port *uap =2164	    container_of(port, struct uart_amba_port, port);2165	unsigned long flags;2166 2167	tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);2168 2169	/* The SBSA UART only supports 8n1 without hardware flow control. */2170	termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);2171	termios->c_cflag &= ~(CMSPAR | CRTSCTS);2172	termios->c_cflag |= CS8 | CLOCAL;2173 2174	uart_port_lock_irqsave(port, &flags);2175	uart_update_timeout(port, CS8, uap->fixed_baud);2176	pl011_setup_status_masks(port, termios);2177	uart_port_unlock_irqrestore(port, flags);2178}2179 2180static const char *pl011_type(struct uart_port *port)2181{2182	struct uart_amba_port *uap =2183	    container_of(port, struct uart_amba_port, port);2184	return uap->port.type == PORT_AMBA ? uap->type : NULL;2185}2186 2187/*2188 * Configure/autoconfigure the port.2189 */2190static void pl011_config_port(struct uart_port *port, int flags)2191{2192	if (flags & UART_CONFIG_TYPE)2193		port->type = PORT_AMBA;2194}2195 2196/*2197 * verify the new serial_struct (for TIOCSSERIAL).2198 */2199static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)2200{2201	int ret = 0;2202 2203	if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)2204		ret = -EINVAL;2205	if (ser->irq < 0 || ser->irq >= nr_irqs)2206		ret = -EINVAL;2207	if (ser->baud_base < 9600)2208		ret = -EINVAL;2209	if (port->mapbase != (unsigned long)ser->iomem_base)2210		ret = -EINVAL;2211	return ret;2212}2213 2214static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,2215			      struct serial_rs485 *rs485)2216{2217	struct uart_amba_port *uap =2218		container_of(port, struct uart_amba_port, port);2219 2220	if (port->rs485.flags & SER_RS485_ENABLED)2221		pl011_rs485_tx_stop(uap);2222 2223	/* Make sure auto RTS is disabled */2224	if (rs485->flags & SER_RS485_ENABLED) {2225		u32 cr = pl011_read(uap, REG_CR);2226 2227		cr &= ~UART011_CR_RTSEN;2228		pl011_write(cr, uap, REG_CR);2229		port->status &= ~UPSTAT_AUTORTS;2230	}2231 2232	return 0;2233}2234 2235static const struct uart_ops amba_pl011_pops = {2236	.tx_empty	= pl011_tx_empty,2237	.set_mctrl	= pl011_set_mctrl,2238	.get_mctrl	= pl011_get_mctrl,2239	.stop_tx	= pl011_stop_tx,2240	.start_tx	= pl011_start_tx,2241	.stop_rx	= pl011_stop_rx,2242	.throttle	= pl011_throttle_rx,2243	.unthrottle	= pl011_unthrottle_rx,2244	.enable_ms	= pl011_enable_ms,2245	.break_ctl	= pl011_break_ctl,2246	.startup	= pl011_startup,2247	.shutdown	= pl011_shutdown,2248	.flush_buffer	= pl011_dma_flush_buffer,2249	.set_termios	= pl011_set_termios,2250	.type		= pl011_type,2251	.config_port	= pl011_config_port,2252	.verify_port	= pl011_verify_port,2253#ifdef CONFIG_CONSOLE_POLL2254	.poll_init     = pl011_hwinit,2255	.poll_get_char = pl011_get_poll_char,2256	.poll_put_char = pl011_put_poll_char,2257#endif2258};2259 2260static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)2261{2262}2263 2264static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)2265{2266	return 0;2267}2268 2269static const struct uart_ops sbsa_uart_pops = {2270	.tx_empty	= pl011_tx_empty,2271	.set_mctrl	= sbsa_uart_set_mctrl,2272	.get_mctrl	= sbsa_uart_get_mctrl,2273	.stop_tx	= pl011_stop_tx,2274	.start_tx	= pl011_start_tx,2275	.stop_rx	= pl011_stop_rx,2276	.startup	= sbsa_uart_startup,2277	.shutdown	= sbsa_uart_shutdown,2278	.set_termios	= sbsa_uart_set_termios,2279	.type		= pl011_type,2280	.config_port	= pl011_config_port,2281	.verify_port	= pl011_verify_port,2282#ifdef CONFIG_CONSOLE_POLL2283	.poll_init     = pl011_hwinit,2284	.poll_get_char = pl011_get_poll_char,2285	.poll_put_char = pl011_put_poll_char,2286#endif2287};2288 2289static struct uart_amba_port *amba_ports[UART_NR];2290 2291#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE2292 2293static void pl011_console_putchar(struct uart_port *port, unsigned char ch)2294{2295	struct uart_amba_port *uap =2296	    container_of(port, struct uart_amba_port, port);2297 2298	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)2299		cpu_relax();2300	pl011_write(ch, uap, REG_DR);2301}2302 2303static void2304pl011_console_write(struct console *co, const char *s, unsigned int count)2305{2306	struct uart_amba_port *uap = amba_ports[co->index];2307	unsigned int old_cr = 0, new_cr;2308	unsigned long flags;2309	int locked = 1;2310 2311	clk_enable(uap->clk);2312 2313	if (oops_in_progress)2314		locked = uart_port_trylock_irqsave(&uap->port, &flags);2315	else2316		uart_port_lock_irqsave(&uap->port, &flags);2317 2318	/*2319	 *	First save the CR then disable the interrupts2320	 */2321	if (!uap->vendor->always_enabled) {2322		old_cr = pl011_read(uap, REG_CR);2323		new_cr = old_cr & ~UART011_CR_CTSEN;2324		new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;2325		pl011_write(new_cr, uap, REG_CR);2326	}2327 2328	uart_console_write(&uap->port, s, count, pl011_console_putchar);2329 2330	/*2331	 *	Finally, wait for transmitter to become empty and restore the2332	 *	TCR. Allow feature register bits to be inverted to work around2333	 *	errata.2334	 */2335	while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)2336						& uap->vendor->fr_busy)2337		cpu_relax();2338	if (!uap->vendor->always_enabled)2339		pl011_write(old_cr, uap, REG_CR);2340 2341	if (locked)2342		uart_port_unlock_irqrestore(&uap->port, flags);2343 2344	clk_disable(uap->clk);2345}2346 2347static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,2348				      int *parity, int *bits)2349{2350	unsigned int lcr_h, ibrd, fbrd;2351 2352	if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))2353		return;2354 2355	lcr_h = pl011_read(uap, REG_LCRH_TX);2356 2357	*parity = 'n';2358	if (lcr_h & UART01x_LCRH_PEN) {2359		if (lcr_h & UART01x_LCRH_EPS)2360			*parity = 'e';2361		else2362			*parity = 'o';2363	}2364 2365	if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)2366		*bits = 7;2367	else2368		*bits = 8;2369 2370	ibrd = pl011_read(uap, REG_IBRD);2371	fbrd = pl011_read(uap, REG_FBRD);2372 2373	*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);2374 2375	if (uap->vendor->oversampling &&2376	    (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))2377		*baud *= 2;2378}2379 2380static int pl011_console_setup(struct console *co, char *options)2381{2382	struct uart_amba_port *uap;2383	int baud = 38400;2384	int bits = 8;2385	int parity = 'n';2386	int flow = 'n';2387	int ret;2388 2389	/*2390	 * Check whether an invalid uart number has been specified, and2391	 * if so, search for the first available port that does have2392	 * console support.2393	 */2394	if (co->index >= UART_NR)2395		co->index = 0;2396	uap = amba_ports[co->index];2397	if (!uap)2398		return -ENODEV;2399 2400	/* Allow pins to be muxed in and configured */2401	pinctrl_pm_select_default_state(uap->port.dev);2402 2403	ret = clk_prepare(uap->clk);2404	if (ret)2405		return ret;2406 2407	if (dev_get_platdata(uap->port.dev)) {2408		struct amba_pl011_data *plat;2409 2410		plat = dev_get_platdata(uap->port.dev);2411		if (plat->init)2412			plat->init();2413	}2414 2415	uap->port.uartclk = clk_get_rate(uap->clk);2416 2417	if (uap->vendor->fixed_options) {2418		baud = uap->fixed_baud;2419	} else {2420		if (options)2421			uart_parse_options(options,2422					   &baud, &parity, &bits, &flow);2423		else2424			pl011_console_get_options(uap, &baud, &parity, &bits);2425	}2426 2427	return uart_set_options(&uap->port, co, baud, parity, bits, flow);2428}2429 2430/**2431 *	pl011_console_match - non-standard console matching2432 *	@co:	  registering console2433 *	@name:	  name from console command line2434 *	@idx:	  index from console command line2435 *	@options: ptr to option string from console command line2436 *2437 *	Only attempts to match console command lines of the form:2438 *	    console=pl011,mmio|mmio32,<addr>[,<options>]2439 *	    console=pl011,0x<addr>[,<options>]2440 *	This form is used to register an initial earlycon boot console and2441 *	replace it with the amba_console at pl011 driver init.2442 *2443 *	Performs console setup for a match (as required by interface)2444 *	If no <options> are specified, then assume the h/w is already setup.2445 *2446 *	Returns 0 if console matches; otherwise non-zero to use default matching2447 */2448static int pl011_console_match(struct console *co, char *name, int idx,2449			       char *options)2450{2451	unsigned char iotype;2452	resource_size_t addr;2453	int i;2454 2455	/*2456	 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum2457	 * have a distinct console name, so make sure we check for that.2458	 * The actual implementation of the erratum occurs in the probe2459	 * function.2460	 */2461	if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))2462		return -ENODEV;2463 2464	if (uart_parse_earlycon(options, &iotype, &addr, &options))2465		return -ENODEV;2466 2467	if (iotype != UPIO_MEM && iotype != UPIO_MEM32)2468		return -ENODEV;2469 2470	/* try to match the port specified on the command line */2471	for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {2472		struct uart_port *port;2473 2474		if (!amba_ports[i])2475			continue;2476 2477		port = &amba_ports[i]->port;2478 2479		if (port->mapbase != addr)2480			continue;2481 2482		co->index = i;2483		uart_port_set_cons(port, co);2484		return pl011_console_setup(co, options);2485	}2486 2487	return -ENODEV;2488}2489 2490static struct uart_driver amba_reg;2491static struct console amba_console = {2492	.name		= "ttyAMA",2493	.write		= pl011_console_write,2494	.device		= uart_console_device,2495	.setup		= pl011_console_setup,2496	.match		= pl011_console_match,2497	.flags		= CON_PRINTBUFFER | CON_ANYTIME,2498	.index		= -1,2499	.data		= &amba_reg,2500};2501 2502#define AMBA_CONSOLE	(&amba_console)2503 2504static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)2505{2506	while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)2507		cpu_relax();2508	writel(c, port->membase + UART01x_DR);2509	while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))2510		cpu_relax();2511}2512 2513static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n)2514{2515	struct earlycon_device *dev = con->data;2516 2517	uart_console_write(&dev->port, s, n, qdf2400_e44_putc);2518}2519 2520static void pl011_putc(struct uart_port *port, unsigned char c)2521{2522	while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)2523		cpu_relax();2524	if (port->iotype == UPIO_MEM32)2525		writel(c, port->membase + UART01x_DR);2526	else2527		writeb(c, port->membase + UART01x_DR);2528	while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)2529		cpu_relax();2530}2531 2532static void pl011_early_write(struct console *con, const char *s, unsigned int n)2533{2534	struct earlycon_device *dev = con->data;2535 2536	uart_console_write(&dev->port, s, n, pl011_putc);2537}2538 2539#ifdef CONFIG_CONSOLE_POLL2540static int pl011_getc(struct uart_port *port)2541{2542	if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)2543		return NO_POLL_CHAR;2544 2545	if (port->iotype == UPIO_MEM32)2546		return readl(port->membase + UART01x_DR);2547	else2548		return readb(port->membase + UART01x_DR);2549}2550 2551static int pl011_early_read(struct console *con, char *s, unsigned int n)2552{2553	struct earlycon_device *dev = con->data;2554	int ch, num_read = 0;2555 2556	while (num_read < n) {2557		ch = pl011_getc(&dev->port);2558		if (ch == NO_POLL_CHAR)2559			break;2560 2561		s[num_read++] = ch;2562	}2563 2564	return num_read;2565}2566#else2567#define pl011_early_read NULL2568#endif2569 2570/*2571 * On non-ACPI systems, earlycon is enabled by specifying2572 * "earlycon=pl011,<address>" on the kernel command line.2573 *2574 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,2575 * by specifying only "earlycon" on the command line.  Because it requires2576 * SPCR, the console starts after ACPI is parsed, which is later than a2577 * traditional early console.2578 *2579 * To get the traditional early console that starts before ACPI is parsed,2580 * specify the full "earlycon=pl011,<address>" option.2581 */2582static int __init pl011_early_console_setup(struct earlycon_device *device,2583					    const char *opt)2584{2585	if (!device->port.membase)2586		return -ENODEV;2587 2588	device->con->write = pl011_early_write;2589	device->con->read = pl011_early_read;2590 2591	return 0;2592}2593 2594OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);2595 2596OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);2597 2598/*2599 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by2600 * Erratum 44, traditional earlycon can be enabled by specifying2601 * "earlycon=qdf2400_e44,<address>".  Any options are ignored.2602 *2603 * Alternatively, you can just specify "earlycon", and the early console2604 * will be enabled with the information from the SPCR table.  In this2605 * case, the SPCR code will detect the need for the E44 work-around,2606 * and set the console name to "qdf2400_e44".2607 */2608static int __init2609qdf2400_e44_early_console_setup(struct earlycon_device *device,2610				const char *opt)2611{2612	if (!device->port.membase)2613		return -ENODEV;2614 2615	device->con->write = qdf2400_e44_early_write;2616	return 0;2617}2618 2619EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);2620 2621#else2622#define AMBA_CONSOLE	NULL2623#endif2624 2625static struct uart_driver amba_reg = {2626	.owner			= THIS_MODULE,2627	.driver_name		= "ttyAMA",2628	.dev_name		= "ttyAMA",2629	.major			= SERIAL_AMBA_MAJOR,2630	.minor			= SERIAL_AMBA_MINOR,2631	.nr			= UART_NR,2632	.cons			= AMBA_CONSOLE,2633};2634 2635static int pl011_probe_dt_alias(int index, struct device *dev)2636{2637	struct device_node *np;2638	static bool seen_dev_with_alias;2639	static bool seen_dev_without_alias;2640	int ret = index;2641 2642	if (!IS_ENABLED(CONFIG_OF))2643		return ret;2644 2645	np = dev->of_node;2646	if (!np)2647		return ret;2648 2649	ret = of_alias_get_id(np, "serial");2650	if (ret < 0) {2651		seen_dev_without_alias = true;2652		ret = index;2653	} else {2654		seen_dev_with_alias = true;2655		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) {2656			dev_warn(dev, "requested serial port %d  not available.\n", ret);2657			ret = index;2658		}2659	}2660 2661	if (seen_dev_with_alias && seen_dev_without_alias)2662		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");2663 2664	return ret;2665}2666 2667/* unregisters the driver also if no more ports are left */2668static void pl011_unregister_port(struct uart_amba_port *uap)2669{2670	int i;2671	bool busy = false;2672 2673	for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {2674		if (amba_ports[i] == uap)2675			amba_ports[i] = NULL;2676		else if (amba_ports[i])2677			busy = true;2678	}2679	pl011_dma_remove(uap);2680	if (!busy)2681		uart_unregister_driver(&amba_reg);2682}2683 2684static int pl011_find_free_port(void)2685{2686	int i;2687 2688	for (i = 0; i < ARRAY_SIZE(amba_ports); i++)2689		if (!amba_ports[i])2690			return i;2691 2692	return -EBUSY;2693}2694 2695static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,2696			    struct resource *mmiobase, int index)2697{2698	void __iomem *base;2699	int ret;2700 2701	base = devm_ioremap_resource(dev, mmiobase);2702	if (IS_ERR(base))2703		return PTR_ERR(base);2704 2705	index = pl011_probe_dt_alias(index, dev);2706 2707	uap->port.dev = dev;2708	uap->port.mapbase = mmiobase->start;2709	uap->port.membase = base;2710	uap->port.fifosize = uap->fifosize;2711	uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);2712	uap->port.flags = UPF_BOOT_AUTOCONF;2713	uap->port.line = index;2714 2715	ret = uart_get_rs485_mode(&uap->port);2716	if (ret)2717		return ret;2718 2719	amba_ports[index] = uap;2720 2721	return 0;2722}2723 2724static int pl011_register_port(struct uart_amba_port *uap)2725{2726	int ret, i;2727 2728	/* Ensure interrupts from this UART are masked and cleared */2729	pl011_write(0, uap, REG_IMSC);2730	pl011_write(0xffff, uap, REG_ICR);2731 2732	if (!amba_reg.state) {2733		ret = uart_register_driver(&amba_reg);2734		if (ret < 0) {2735			dev_err(uap->port.dev,2736				"Failed to register AMBA-PL011 driver\n");2737			for (i = 0; i < ARRAY_SIZE(amba_ports); i++)2738				if (amba_ports[i] == uap)2739					amba_ports[i] = NULL;2740			return ret;2741		}2742	}2743 2744	ret = uart_add_one_port(&amba_reg, &uap->port);2745	if (ret)2746		pl011_unregister_port(uap);2747 2748	return ret;2749}2750 2751static const struct serial_rs485 pl011_rs485_supported = {2752	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |2753		 SER_RS485_RX_DURING_TX,2754	.delay_rts_before_send = 1,2755	.delay_rts_after_send = 1,2756};2757 2758static int pl011_probe(struct amba_device *dev, const struct amba_id *id)2759{2760	struct uart_amba_port *uap;2761	struct vendor_data *vendor = id->data;2762	int portnr, ret;2763	u32 val;2764 2765	portnr = pl011_find_free_port();2766	if (portnr < 0)2767		return portnr;2768 2769	uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),2770			   GFP_KERNEL);2771	if (!uap)2772		return -ENOMEM;2773 2774	uap->clk = devm_clk_get(&dev->dev, NULL);2775	if (IS_ERR(uap->clk))2776		return PTR_ERR(uap->clk);2777 2778	uap->reg_offset = vendor->reg_offset;2779	uap->vendor = vendor;2780	uap->fifosize = vendor->get_fifosize(dev);2781	uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;2782	uap->port.irq = dev->irq[0];2783	uap->port.ops = &amba_pl011_pops;2784	uap->port.rs485_config = pl011_rs485_config;2785	uap->port.rs485_supported = pl011_rs485_supported;2786	snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));2787 2788	if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {2789		switch (val) {2790		case 1:2791			uap->port.iotype = UPIO_MEM;2792			break;2793		case 4:2794			uap->port.iotype = UPIO_MEM32;2795			break;2796		default:2797			dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",2798				 val);2799			return -EINVAL;2800		}2801	}2802 2803	ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);2804	if (ret)2805		return ret;2806 2807	amba_set_drvdata(dev, uap);2808 2809	return pl011_register_port(uap);2810}2811 2812static void pl011_remove(struct amba_device *dev)2813{2814	struct uart_amba_port *uap = amba_get_drvdata(dev);2815 2816	uart_remove_one_port(&amba_reg, &uap->port);2817	pl011_unregister_port(uap);2818}2819 2820#ifdef CONFIG_PM_SLEEP2821static int pl011_suspend(struct device *dev)2822{2823	struct uart_amba_port *uap = dev_get_drvdata(dev);2824 2825	if (!uap)2826		return -EINVAL;2827 2828	return uart_suspend_port(&amba_reg, &uap->port);2829}2830 2831static int pl011_resume(struct device *dev)2832{2833	struct uart_amba_port *uap = dev_get_drvdata(dev);2834 2835	if (!uap)2836		return -EINVAL;2837 2838	return uart_resume_port(&amba_reg, &uap->port);2839}2840#endif2841 2842static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);2843 2844#ifdef CONFIG_ACPI_SPCR_TABLE2845static void qpdf2400_erratum44_workaround(struct device *dev,2846					  struct uart_amba_port *uap)2847{2848	if (!qdf2400_e44_present)2849		return;2850 2851	dev_info(dev, "working around QDF2400 SoC erratum 44\n");2852	uap->vendor = &vendor_qdt_qdf2400_e44;2853}2854#else2855static void qpdf2400_erratum44_workaround(struct device *dev,2856					  struct uart_amba_port *uap)2857{ /* empty */ }2858#endif2859 2860static int sbsa_uart_probe(struct platform_device *pdev)2861{2862	struct uart_amba_port *uap;2863	struct resource *r;2864	int portnr, ret;2865	int baudrate;2866 2867	/*2868	 * Check the mandatory baud rate parameter in the DT node early2869	 * so that we can easily exit with the error.2870	 */2871	if (pdev->dev.of_node) {2872		struct device_node *np = pdev->dev.of_node;2873 2874		ret = of_property_read_u32(np, "current-speed", &baudrate);2875		if (ret)2876			return ret;2877	} else {2878		baudrate = 115200;2879	}2880 2881	portnr = pl011_find_free_port();2882	if (portnr < 0)2883		return portnr;2884 2885	uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),2886			   GFP_KERNEL);2887	if (!uap)2888		return -ENOMEM;2889 2890	ret = platform_get_irq(pdev, 0);2891	if (ret < 0)2892		return ret;2893	uap->port.irq	= ret;2894 2895	uap->vendor = &vendor_sbsa;2896	qpdf2400_erratum44_workaround(&pdev->dev, uap);2897 2898	uap->reg_offset	= uap->vendor->reg_offset;2899	uap->fifosize	= 32;2900	uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;2901	uap->port.ops	= &sbsa_uart_pops;2902	uap->fixed_baud = baudrate;2903 2904	snprintf(uap->type, sizeof(uap->type), "SBSA");2905 2906	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);2907 2908	ret = pl011_setup_port(&pdev->dev, uap, r, portnr);2909	if (ret)2910		return ret;2911 2912	platform_set_drvdata(pdev, uap);2913 2914	return pl011_register_port(uap);2915}2916 2917static void sbsa_uart_remove(struct platform_device *pdev)2918{2919	struct uart_amba_port *uap = platform_get_drvdata(pdev);2920 2921	uart_remove_one_port(&amba_reg, &uap->port);2922	pl011_unregister_port(uap);2923}2924 2925static const struct of_device_id sbsa_uart_of_match[] = {2926	{ .compatible = "arm,sbsa-uart", },2927	{},2928};2929MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);2930 2931static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {2932	{ "ARMH0011", 0 },2933	{ "ARMHB000", 0 },2934	{},2935};2936MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);2937 2938static struct platform_driver arm_sbsa_uart_platform_driver = {2939	.probe		= sbsa_uart_probe,2940	.remove_new	= sbsa_uart_remove,2941	.driver	= {2942		.name	= "sbsa-uart",2943		.pm	= &pl011_dev_pm_ops,2944		.of_match_table = of_match_ptr(sbsa_uart_of_match),2945		.acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),2946		.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),2947	},2948};2949 2950static const struct amba_id pl011_ids[] = {2951	{2952		.id	= 0x00041011,2953		.mask	= 0x000fffff,2954		.data	= &vendor_arm,2955	},2956	{2957		.id	= 0x00380802,2958		.mask	= 0x00ffffff,2959		.data	= &vendor_st,2960	},2961	{ 0, 0 },2962};2963 2964MODULE_DEVICE_TABLE(amba, pl011_ids);2965 2966static struct amba_driver pl011_driver = {2967	.drv = {2968		.name	= "uart-pl011",2969		.pm	= &pl011_dev_pm_ops,2970		.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),2971	},2972	.id_table	= pl011_ids,2973	.probe		= pl011_probe,2974	.remove		= pl011_remove,2975};2976 2977static int __init pl011_init(void)2978{2979	pr_info("Serial: AMBA PL011 UART driver\n");2980 2981	if (platform_driver_register(&arm_sbsa_uart_platform_driver))2982		pr_warn("could not register SBSA UART platform driver\n");2983	return amba_driver_register(&pl011_driver);2984}2985 2986static void __exit pl011_exit(void)2987{2988	platform_driver_unregister(&arm_sbsa_uart_platform_driver);2989	amba_driver_unregister(&pl011_driver);2990}2991 2992/*2993 * While this can be a module, if builtin it's most likely the console2994 * So let's leave module_exit but move module_init to an earlier place2995 */2996arch_initcall(pl011_init);2997module_exit(pl011_exit);2998 2999MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");3000MODULE_DESCRIPTION("ARM AMBA serial port driver");3001MODULE_LICENSE("GPL");3002