brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0+2/*3 *  Freescale lpuart serial port driver4 *5 *  Copyright 2012-2014 Freescale Semiconductor, Inc.6 */7 8#include <linux/bitfield.h>9#include <linux/bits.h>10#include <linux/circ_buf.h>11#include <linux/clk.h>12#include <linux/console.h>13#include <linux/delay.h>14#include <linux/dma-mapping.h>15#include <linux/dmaengine.h>16#include <linux/dmapool.h>17#include <linux/io.h>18#include <linux/iopoll.h>19#include <linux/irq.h>20#include <linux/module.h>21#include <linux/of.h>22#include <linux/of_dma.h>23#include <linux/pinctrl/consumer.h>24#include <linux/platform_device.h>25#include <linux/pm_runtime.h>26#include <linux/serial_core.h>27#include <linux/slab.h>28#include <linux/tty_flip.h>29 30/* All registers are 8-bit width */31#define UARTBDH			0x0032#define UARTBDL			0x0133#define UARTCR1			0x0234#define UARTCR2			0x0335#define UARTSR1			0x0436#define UARTCR3			0x0637#define UARTDR			0x0738#define UARTCR4			0x0a39#define UARTCR5			0x0b40#define UARTMODEM		0x0d41#define UARTPFIFO		0x1042#define UARTCFIFO		0x1143#define UARTSFIFO		0x1244#define UARTTWFIFO		0x1345#define UARTTCFIFO		0x1446#define UARTRWFIFO		0x1547 48#define UARTBDH_LBKDIE		0x8049#define UARTBDH_RXEDGIE		0x4050#define UARTBDH_SBR_MASK	0x1f51 52#define UARTCR1_LOOPS		0x8053#define UARTCR1_RSRC		0x2054#define UARTCR1_M		0x1055#define UARTCR1_WAKE		0x0856#define UARTCR1_ILT		0x0457#define UARTCR1_PE		0x0258#define UARTCR1_PT		0x0159 60#define UARTCR2_TIE		0x8061#define UARTCR2_TCIE		0x4062#define UARTCR2_RIE		0x2063#define UARTCR2_ILIE		0x1064#define UARTCR2_TE		0x0865#define UARTCR2_RE		0x0466#define UARTCR2_RWU		0x0267#define UARTCR2_SBK		0x0168 69#define UARTSR1_TDRE		0x8070#define UARTSR1_TC		0x4071#define UARTSR1_RDRF		0x2072#define UARTSR1_IDLE		0x1073#define UARTSR1_OR		0x0874#define UARTSR1_NF		0x0475#define UARTSR1_FE		0x0276#define UARTSR1_PE		0x0177 78#define UARTCR3_R8		0x8079#define UARTCR3_T8		0x4080#define UARTCR3_TXDIR		0x2081#define UARTCR3_TXINV		0x1082#define UARTCR3_ORIE		0x0883#define UARTCR3_NEIE		0x0484#define UARTCR3_FEIE		0x0285#define UARTCR3_PEIE		0x0186 87#define UARTCR4_MAEN1		0x8088#define UARTCR4_MAEN2		0x4089#define UARTCR4_M10		0x2090#define UARTCR4_BRFA_MASK	0x1f91#define UARTCR4_BRFA_OFF	092 93#define UARTCR5_TDMAS		0x8094#define UARTCR5_RDMAS		0x2095 96#define UARTMODEM_RXRTSE	0x0897#define UARTMODEM_TXRTSPOL	0x0498#define UARTMODEM_TXRTSE	0x0299#define UARTMODEM_TXCTSE	0x01100 101#define UARTPFIFO_TXFE		0x80102#define UARTPFIFO_FIFOSIZE_MASK	0x7103#define UARTPFIFO_TXSIZE_OFF	4104#define UARTPFIFO_RXFE		0x08105#define UARTPFIFO_RXSIZE_OFF	0106 107#define UARTCFIFO_TXFLUSH	0x80108#define UARTCFIFO_RXFLUSH	0x40109#define UARTCFIFO_RXOFE		0x04110#define UARTCFIFO_TXOFE		0x02111#define UARTCFIFO_RXUFE		0x01112 113#define UARTSFIFO_TXEMPT	0x80114#define UARTSFIFO_RXEMPT	0x40115#define UARTSFIFO_RXOF		0x04116#define UARTSFIFO_TXOF		0x02117#define UARTSFIFO_RXUF		0x01118 119/* 32-bit global registers only for i.MX7ULP/i.MX8x120 * Used to reset all internal logic and registers, except the Global Register.121 */122#define UART_GLOBAL		0x8123 124/* 32-bit register definition */125#define UARTBAUD		0x00126#define UARTSTAT		0x04127#define UARTCTRL		0x08128#define UARTDATA		0x0C129#define UARTMATCH		0x10130#define UARTMODIR		0x14131#define UARTFIFO		0x18132#define UARTWATER		0x1c133 134#define UARTBAUD_MAEN1		0x80000000135#define UARTBAUD_MAEN2		0x40000000136#define UARTBAUD_M10		0x20000000137#define UARTBAUD_TDMAE		0x00800000138#define UARTBAUD_RDMAE		0x00200000139#define UARTBAUD_MATCFG		0x00400000140#define UARTBAUD_BOTHEDGE	0x00020000141#define UARTBAUD_RESYNCDIS	0x00010000142#define UARTBAUD_LBKDIE		0x00008000143#define UARTBAUD_RXEDGIE	0x00004000144#define UARTBAUD_SBNS		0x00002000145#define UARTBAUD_SBR		0x00000000146#define UARTBAUD_SBR_MASK	0x1fff147#define UARTBAUD_OSR_MASK       0x1f148#define UARTBAUD_OSR_SHIFT      24149 150#define UARTSTAT_LBKDIF		0x80000000151#define UARTSTAT_RXEDGIF	0x40000000152#define UARTSTAT_MSBF		0x20000000153#define UARTSTAT_RXINV		0x10000000154#define UARTSTAT_RWUID		0x08000000155#define UARTSTAT_BRK13		0x04000000156#define UARTSTAT_LBKDE		0x02000000157#define UARTSTAT_RAF		0x01000000158#define UARTSTAT_TDRE		0x00800000159#define UARTSTAT_TC		0x00400000160#define UARTSTAT_RDRF		0x00200000161#define UARTSTAT_IDLE		0x00100000162#define UARTSTAT_OR		0x00080000163#define UARTSTAT_NF		0x00040000164#define UARTSTAT_FE		0x00020000165#define UARTSTAT_PE		0x00010000166#define UARTSTAT_MA1F		0x00008000167#define UARTSTAT_M21F		0x00004000168 169#define UARTCTRL_R8T9		0x80000000170#define UARTCTRL_R9T8		0x40000000171#define UARTCTRL_TXDIR		0x20000000172#define UARTCTRL_TXINV		0x10000000173#define UARTCTRL_ORIE		0x08000000174#define UARTCTRL_NEIE		0x04000000175#define UARTCTRL_FEIE		0x02000000176#define UARTCTRL_PEIE		0x01000000177#define UARTCTRL_TIE		0x00800000178#define UARTCTRL_TCIE		0x00400000179#define UARTCTRL_RIE		0x00200000180#define UARTCTRL_ILIE		0x00100000181#define UARTCTRL_TE		0x00080000182#define UARTCTRL_RE		0x00040000183#define UARTCTRL_RWU		0x00020000184#define UARTCTRL_SBK		0x00010000185#define UARTCTRL_MA1IE		0x00008000186#define UARTCTRL_MA2IE		0x00004000187#define UARTCTRL_IDLECFG	GENMASK(10, 8)188#define UARTCTRL_LOOPS		0x00000080189#define UARTCTRL_DOZEEN		0x00000040190#define UARTCTRL_RSRC		0x00000020191#define UARTCTRL_M		0x00000010192#define UARTCTRL_WAKE		0x00000008193#define UARTCTRL_ILT		0x00000004194#define UARTCTRL_PE		0x00000002195#define UARTCTRL_PT		0x00000001196 197#define UARTDATA_NOISY		0x00008000198#define UARTDATA_PARITYE	0x00004000199#define UARTDATA_FRETSC		0x00002000200#define UARTDATA_RXEMPT		0x00001000201#define UARTDATA_IDLINE		0x00000800202#define UARTDATA_MASK		0x3ff203 204#define UARTMODIR_IREN		0x00020000205#define UARTMODIR_RTSWATER	GENMASK(10, 8)206#define UARTMODIR_TXCTSSRC	0x00000020207#define UARTMODIR_TXCTSC	0x00000010208#define UARTMODIR_RXRTSE	0x00000008209#define UARTMODIR_TXRTSPOL	0x00000004210#define UARTMODIR_TXRTSE	0x00000002211#define UARTMODIR_TXCTSE	0x00000001212 213#define UARTFIFO_TXEMPT		0x00800000214#define UARTFIFO_RXEMPT		0x00400000215#define UARTFIFO_TXOF		0x00020000216#define UARTFIFO_RXUF		0x00010000217#define UARTFIFO_TXFLUSH	0x00008000218#define UARTFIFO_RXFLUSH	0x00004000219#define UARTFIFO_RXIDEN	GENMASK(12, 10)220#define UARTFIFO_TXOFE		0x00000200221#define UARTFIFO_RXUFE		0x00000100222#define UARTFIFO_TXFE		0x00000080223#define UARTFIFO_FIFOSIZE_MASK	0x7224#define UARTFIFO_TXSIZE_OFF	4225#define UARTFIFO_RXFE		0x00000008226#define UARTFIFO_RXSIZE_OFF	0227#define UARTFIFO_DEPTH(x)	(0x1 << ((x) ? ((x) + 1) : 0))228 229#define UARTWATER_COUNT_MASK	0xff230#define UARTWATER_TXCNT_OFF	8231#define UARTWATER_RXCNT_OFF	24232#define UARTWATER_WATER_MASK	0xff233#define UARTWATER_TXWATER_OFF	0234#define UARTWATER_RXWATER_OFF	16235 236#define UART_GLOBAL_RST	0x2237#define GLOBAL_RST_MIN_US	20238#define GLOBAL_RST_MAX_US	40239 240/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */241#define DMA_RX_TIMEOUT		(10)242#define DMA_RX_IDLE_CHARS	8243#define UART_AUTOSUSPEND_TIMEOUT	3000244 245#define DRIVER_NAME	"fsl-lpuart"246#define DEV_NAME	"ttyLP"247#define UART_NR		8248 249/* IMX lpuart has four extra unused regs located at the beginning */250#define IMX_REG_OFF	0x10251 252enum lpuart_type {253	VF610_LPUART,254	LS1021A_LPUART,255	LS1028A_LPUART,256	IMX7ULP_LPUART,257	IMX8ULP_LPUART,258	IMX8QXP_LPUART,259	IMXRT1050_LPUART,260};261 262struct lpuart_port {263	struct uart_port	port;264	enum lpuart_type	devtype;265	struct clk		*ipg_clk;266	struct clk		*baud_clk;267	unsigned int		txfifo_size;268	unsigned int		rxfifo_size;269 270	u8			rx_watermark;271	bool			lpuart_dma_tx_use;272	bool			lpuart_dma_rx_use;273	struct dma_chan		*dma_tx_chan;274	struct dma_chan		*dma_rx_chan;275	struct dma_async_tx_descriptor  *dma_tx_desc;276	struct dma_async_tx_descriptor  *dma_rx_desc;277	dma_cookie_t		dma_tx_cookie;278	dma_cookie_t		dma_rx_cookie;279	unsigned int		dma_tx_bytes;280	unsigned int		dma_rx_bytes;281	bool			dma_tx_in_progress;282	unsigned int		dma_rx_timeout;283	struct timer_list	lpuart_timer;284	struct scatterlist	rx_sgl, tx_sgl[2];285	struct circ_buf		rx_ring;286	int			rx_dma_rng_buf_len;287	int                     last_residue;288	unsigned int		dma_tx_nents;289	wait_queue_head_t	dma_wait;290	bool			is_cs7; /* Set to true when character size is 7 */291					/* and the parity is enabled		*/292	bool			dma_idle_int;293};294 295struct lpuart_soc_data {296	enum lpuart_type devtype;297	char iotype;298	u8 reg_off;299	u8 rx_watermark;300};301 302static const struct lpuart_soc_data vf_data = {303	.devtype = VF610_LPUART,304	.iotype = UPIO_MEM,305	.rx_watermark = 1,306};307 308static const struct lpuart_soc_data ls1021a_data = {309	.devtype = LS1021A_LPUART,310	.iotype = UPIO_MEM32BE,311	.rx_watermark = 1,312};313 314static const struct lpuart_soc_data ls1028a_data = {315	.devtype = LS1028A_LPUART,316	.iotype = UPIO_MEM32,317	.rx_watermark = 0,318};319 320static struct lpuart_soc_data imx7ulp_data = {321	.devtype = IMX7ULP_LPUART,322	.iotype = UPIO_MEM32,323	.reg_off = IMX_REG_OFF,324	.rx_watermark = 1,325};326 327static struct lpuart_soc_data imx8ulp_data = {328	.devtype = IMX8ULP_LPUART,329	.iotype = UPIO_MEM32,330	.reg_off = IMX_REG_OFF,331	.rx_watermark = 3,332};333 334static struct lpuart_soc_data imx8qxp_data = {335	.devtype = IMX8QXP_LPUART,336	.iotype = UPIO_MEM32,337	.reg_off = IMX_REG_OFF,338	.rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */339};340static struct lpuart_soc_data imxrt1050_data = {341	.devtype = IMXRT1050_LPUART,342	.iotype = UPIO_MEM32,343	.reg_off = IMX_REG_OFF,344	.rx_watermark = 1,345};346 347static const struct of_device_id lpuart_dt_ids[] = {348	{ .compatible = "fsl,vf610-lpuart",	.data = &vf_data, },349	{ .compatible = "fsl,ls1021a-lpuart",	.data = &ls1021a_data, },350	{ .compatible = "fsl,ls1028a-lpuart",	.data = &ls1028a_data, },351	{ .compatible = "fsl,imx7ulp-lpuart",	.data = &imx7ulp_data, },352	{ .compatible = "fsl,imx8ulp-lpuart",	.data = &imx8ulp_data, },353	{ .compatible = "fsl,imx8qxp-lpuart",	.data = &imx8qxp_data, },354	{ .compatible = "fsl,imxrt1050-lpuart",	.data = &imxrt1050_data},355	{ /* sentinel */ }356};357MODULE_DEVICE_TABLE(of, lpuart_dt_ids);358 359/* Forward declare this for the dma callbacks*/360static void lpuart_dma_tx_complete(void *arg);361 362static inline bool is_layerscape_lpuart(struct lpuart_port *sport)363{364	return (sport->devtype == LS1021A_LPUART ||365		sport->devtype == LS1028A_LPUART);366}367 368static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)369{370	return sport->devtype == IMX7ULP_LPUART;371}372 373static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)374{375	return sport->devtype == IMX8ULP_LPUART;376}377 378static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)379{380	return sport->devtype == IMX8QXP_LPUART;381}382 383static inline u32 lpuart32_read(struct uart_port *port, u32 off)384{385	switch (port->iotype) {386	case UPIO_MEM32:387		return readl(port->membase + off);388	case UPIO_MEM32BE:389		return ioread32be(port->membase + off);390	default:391		return 0;392	}393}394 395static inline void lpuart32_write(struct uart_port *port, u32 val,396				  u32 off)397{398	switch (port->iotype) {399	case UPIO_MEM32:400		writel(val, port->membase + off);401		break;402	case UPIO_MEM32BE:403		iowrite32be(val, port->membase + off);404		break;405	}406}407 408static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)409{410	int ret = 0;411 412	if (is_en) {413		ret = clk_prepare_enable(sport->ipg_clk);414		if (ret)415			return ret;416 417		ret = clk_prepare_enable(sport->baud_clk);418		if (ret) {419			clk_disable_unprepare(sport->ipg_clk);420			return ret;421		}422	} else {423		clk_disable_unprepare(sport->baud_clk);424		clk_disable_unprepare(sport->ipg_clk);425	}426 427	return 0;428}429 430static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)431{432	if (is_imx8qxp_lpuart(sport))433		return clk_get_rate(sport->baud_clk);434 435	return clk_get_rate(sport->ipg_clk);436}437 438#define lpuart_enable_clks(x)	__lpuart_enable_clks(x, true)439#define lpuart_disable_clks(x)	__lpuart_enable_clks(x, false)440 441static void lpuart_stop_tx(struct uart_port *port)442{443	unsigned char temp;444 445	temp = readb(port->membase + UARTCR2);446	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);447	writeb(temp, port->membase + UARTCR2);448}449 450static void lpuart32_stop_tx(struct uart_port *port)451{452	unsigned long temp;453 454	temp = lpuart32_read(port, UARTCTRL);455	temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);456	lpuart32_write(port, temp, UARTCTRL);457}458 459static void lpuart_stop_rx(struct uart_port *port)460{461	unsigned char temp;462 463	temp = readb(port->membase + UARTCR2);464	writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);465}466 467static void lpuart32_stop_rx(struct uart_port *port)468{469	unsigned long temp;470 471	temp = lpuart32_read(port, UARTCTRL);472	lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);473}474 475static void lpuart_dma_tx(struct lpuart_port *sport)476{477	struct tty_port *tport = &sport->port.state->port;478	struct scatterlist *sgl = sport->tx_sgl;479	struct device *dev = sport->port.dev;480	struct dma_chan *chan = sport->dma_tx_chan;481	int ret;482 483	if (sport->dma_tx_in_progress)484		return;485 486	sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));487	sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo);488	sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,489			ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes);490 491	ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,492			 DMA_TO_DEVICE);493	if (!ret) {494		dev_err(dev, "DMA mapping error for TX.\n");495		return;496	}497 498	sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,499					ret, DMA_MEM_TO_DEV,500					DMA_PREP_INTERRUPT);501	if (!sport->dma_tx_desc) {502		dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,503			      DMA_TO_DEVICE);504		dev_err(dev, "Cannot prepare TX slave DMA!\n");505		return;506	}507 508	sport->dma_tx_desc->callback = lpuart_dma_tx_complete;509	sport->dma_tx_desc->callback_param = sport;510	sport->dma_tx_in_progress = true;511	sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);512	dma_async_issue_pending(chan);513}514 515static bool lpuart_stopped_or_empty(struct uart_port *port)516{517	return kfifo_is_empty(&port->state->port.xmit_fifo) ||518		uart_tx_stopped(port);519}520 521static void lpuart_dma_tx_complete(void *arg)522{523	struct lpuart_port *sport = arg;524	struct scatterlist *sgl = &sport->tx_sgl[0];525	struct tty_port *tport = &sport->port.state->port;526	struct dma_chan *chan = sport->dma_tx_chan;527	unsigned long flags;528 529	uart_port_lock_irqsave(&sport->port, &flags);530	if (!sport->dma_tx_in_progress) {531		uart_port_unlock_irqrestore(&sport->port, flags);532		return;533	}534 535	dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,536		     DMA_TO_DEVICE);537 538	uart_xmit_advance(&sport->port, sport->dma_tx_bytes);539	sport->dma_tx_in_progress = false;540	uart_port_unlock_irqrestore(&sport->port, flags);541 542	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)543		uart_write_wakeup(&sport->port);544 545	if (waitqueue_active(&sport->dma_wait)) {546		wake_up(&sport->dma_wait);547		return;548	}549 550	uart_port_lock_irqsave(&sport->port, &flags);551 552	if (!lpuart_stopped_or_empty(&sport->port))553		lpuart_dma_tx(sport);554 555	uart_port_unlock_irqrestore(&sport->port, flags);556}557 558static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)559{560	switch (sport->port.iotype) {561	case UPIO_MEM32:562		return sport->port.mapbase + UARTDATA;563	case UPIO_MEM32BE:564		return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;565	}566	return sport->port.mapbase + UARTDR;567}568 569static int lpuart_dma_tx_request(struct uart_port *port)570{571	struct lpuart_port *sport = container_of(port,572					struct lpuart_port, port);573	struct dma_slave_config dma_tx_sconfig = {};574	int ret;575 576	dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);577	dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;578	dma_tx_sconfig.dst_maxburst = 1;579	dma_tx_sconfig.direction = DMA_MEM_TO_DEV;580	ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);581 582	if (ret) {583		dev_err(sport->port.dev,584				"DMA slave config failed, err = %d\n", ret);585		return ret;586	}587 588	return 0;589}590 591static bool lpuart_is_32(struct lpuart_port *sport)592{593	return sport->port.iotype == UPIO_MEM32 ||594	       sport->port.iotype ==  UPIO_MEM32BE;595}596 597static void lpuart_flush_buffer(struct uart_port *port)598{599	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);600	struct dma_chan *chan = sport->dma_tx_chan;601	u32 val;602 603	if (sport->lpuart_dma_tx_use) {604		if (sport->dma_tx_in_progress) {605			dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],606				sport->dma_tx_nents, DMA_TO_DEVICE);607			sport->dma_tx_in_progress = false;608		}609		dmaengine_terminate_async(chan);610	}611 612	if (lpuart_is_32(sport)) {613		val = lpuart32_read(&sport->port, UARTFIFO);614		val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;615		lpuart32_write(&sport->port, val, UARTFIFO);616	} else {617		val = readb(sport->port.membase + UARTCFIFO);618		val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;619		writeb(val, sport->port.membase + UARTCFIFO);620	}621}622 623static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,624				u8 bit)625{626	while (!(readb(port->membase + offset) & bit))627		cpu_relax();628}629 630static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,631				  u32 bit)632{633	while (!(lpuart32_read(port, offset) & bit))634		cpu_relax();635}636 637#if defined(CONFIG_CONSOLE_POLL)638 639static int lpuart_poll_init(struct uart_port *port)640{641	struct lpuart_port *sport = container_of(port,642					struct lpuart_port, port);643	unsigned long flags;644	unsigned char temp;645 646	sport->port.fifosize = 0;647 648	uart_port_lock_irqsave(&sport->port, &flags);649	/* Disable Rx & Tx */650	writeb(0, sport->port.membase + UARTCR2);651 652	temp = readb(sport->port.membase + UARTPFIFO);653	/* Enable Rx and Tx FIFO */654	writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,655			sport->port.membase + UARTPFIFO);656 657	/* flush Tx and Rx FIFO */658	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,659			sport->port.membase + UARTCFIFO);660 661	/* explicitly clear RDRF */662	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {663		readb(sport->port.membase + UARTDR);664		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);665	}666 667	writeb(0, sport->port.membase + UARTTWFIFO);668	writeb(1, sport->port.membase + UARTRWFIFO);669 670	/* Enable Rx and Tx */671	writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);672	uart_port_unlock_irqrestore(&sport->port, flags);673 674	return 0;675}676 677static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)678{679	/* drain */680	lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);681	writeb(c, port->membase + UARTDR);682}683 684static int lpuart_poll_get_char(struct uart_port *port)685{686	if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))687		return NO_POLL_CHAR;688 689	return readb(port->membase + UARTDR);690}691 692static int lpuart32_poll_init(struct uart_port *port)693{694	unsigned long flags;695	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);696	u32 temp;697 698	sport->port.fifosize = 0;699 700	uart_port_lock_irqsave(&sport->port, &flags);701 702	/* Disable Rx & Tx */703	lpuart32_write(&sport->port, 0, UARTCTRL);704 705	temp = lpuart32_read(&sport->port, UARTFIFO);706 707	/* Enable Rx and Tx FIFO */708	lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);709 710	/* flush Tx and Rx FIFO */711	lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);712 713	/* explicitly clear RDRF */714	if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {715		lpuart32_read(&sport->port, UARTDATA);716		lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);717	}718 719	/* Enable Rx and Tx */720	lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);721	uart_port_unlock_irqrestore(&sport->port, flags);722 723	return 0;724}725 726static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)727{728	lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);729	lpuart32_write(port, c, UARTDATA);730}731 732static int lpuart32_poll_get_char(struct uart_port *port)733{734	if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))735		return NO_POLL_CHAR;736 737	return lpuart32_read(port, UARTDATA);738}739#endif740 741static inline void lpuart_transmit_buffer(struct lpuart_port *sport)742{743	struct uart_port *port = &sport->port;744	u8 ch;745 746	uart_port_tx(port, ch,747		readb(port->membase + UARTTCFIFO) < sport->txfifo_size,748		writeb(ch, port->membase + UARTDR));749}750 751static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)752{753	struct tty_port *tport = &sport->port.state->port;754	unsigned long txcnt;755	unsigned char c;756 757	if (sport->port.x_char) {758		lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);759		sport->port.icount.tx++;760		sport->port.x_char = 0;761		return;762	}763 764	if (lpuart_stopped_or_empty(&sport->port)) {765		lpuart32_stop_tx(&sport->port);766		return;767	}768 769	txcnt = lpuart32_read(&sport->port, UARTWATER);770	txcnt = txcnt >> UARTWATER_TXCNT_OFF;771	txcnt &= UARTWATER_COUNT_MASK;772	while (txcnt < sport->txfifo_size &&773			uart_fifo_get(&sport->port, &c)) {774		lpuart32_write(&sport->port, c, UARTDATA);775		txcnt = lpuart32_read(&sport->port, UARTWATER);776		txcnt = txcnt >> UARTWATER_TXCNT_OFF;777		txcnt &= UARTWATER_COUNT_MASK;778	}779 780	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)781		uart_write_wakeup(&sport->port);782 783	if (kfifo_is_empty(&tport->xmit_fifo))784		lpuart32_stop_tx(&sport->port);785}786 787static void lpuart_start_tx(struct uart_port *port)788{789	struct lpuart_port *sport = container_of(port,790			struct lpuart_port, port);791	unsigned char temp;792 793	temp = readb(port->membase + UARTCR2);794	writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);795 796	if (sport->lpuart_dma_tx_use) {797		if (!lpuart_stopped_or_empty(port))798			lpuart_dma_tx(sport);799	} else {800		if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)801			lpuart_transmit_buffer(sport);802	}803}804 805static void lpuart32_start_tx(struct uart_port *port)806{807	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);808	unsigned long temp;809 810	if (sport->lpuart_dma_tx_use) {811		if (!lpuart_stopped_or_empty(port))812			lpuart_dma_tx(sport);813	} else {814		temp = lpuart32_read(port, UARTCTRL);815		lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);816 817		if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)818			lpuart32_transmit_buffer(sport);819	}820}821 822static void823lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)824{825	switch (state) {826	case UART_PM_STATE_OFF:827		pm_runtime_mark_last_busy(port->dev);828		pm_runtime_put_autosuspend(port->dev);829		break;830	default:831		pm_runtime_get_sync(port->dev);832		break;833	}834}835 836/* return TIOCSER_TEMT when transmitter is not busy */837static unsigned int lpuart_tx_empty(struct uart_port *port)838{839	struct lpuart_port *sport = container_of(port,840			struct lpuart_port, port);841	unsigned char sr1 = readb(port->membase + UARTSR1);842	unsigned char sfifo = readb(port->membase + UARTSFIFO);843 844	if (sport->dma_tx_in_progress)845		return 0;846 847	if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)848		return TIOCSER_TEMT;849 850	return 0;851}852 853static unsigned int lpuart32_tx_empty(struct uart_port *port)854{855	struct lpuart_port *sport = container_of(port,856			struct lpuart_port, port);857	unsigned long stat = lpuart32_read(port, UARTSTAT);858	unsigned long sfifo = lpuart32_read(port, UARTFIFO);859	unsigned long ctrl = lpuart32_read(port, UARTCTRL);860 861	if (sport->dma_tx_in_progress)862		return 0;863 864	/*865	 * LPUART Transmission Complete Flag may never be set while queuing a break866	 * character, so avoid checking for transmission complete when UARTCTRL_SBK867	 * is asserted.868	 */869	if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)870		return TIOCSER_TEMT;871 872	return 0;873}874 875static void lpuart_txint(struct lpuart_port *sport)876{877	uart_port_lock(&sport->port);878	lpuart_transmit_buffer(sport);879	uart_port_unlock(&sport->port);880}881 882static void lpuart_rxint(struct lpuart_port *sport)883{884	unsigned int flg, ignored = 0, overrun = 0;885	struct tty_port *port = &sport->port.state->port;886	unsigned char rx, sr;887 888	uart_port_lock(&sport->port);889 890	while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {891		flg = TTY_NORMAL;892		sport->port.icount.rx++;893		/*894		 * to clear the FE, OR, NF, FE, PE flags,895		 * read SR1 then read DR896		 */897		sr = readb(sport->port.membase + UARTSR1);898		rx = readb(sport->port.membase + UARTDR);899 900		if (uart_prepare_sysrq_char(&sport->port, rx))901			continue;902 903		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {904			if (sr & UARTSR1_PE)905				sport->port.icount.parity++;906			else if (sr & UARTSR1_FE)907				sport->port.icount.frame++;908 909			if (sr & UARTSR1_OR)910				overrun++;911 912			if (sr & sport->port.ignore_status_mask) {913				if (++ignored > 100)914					goto out;915				continue;916			}917 918			sr &= sport->port.read_status_mask;919 920			if (sr & UARTSR1_PE)921				flg = TTY_PARITY;922			else if (sr & UARTSR1_FE)923				flg = TTY_FRAME;924 925			if (sr & UARTSR1_OR)926				flg = TTY_OVERRUN;927 928			sport->port.sysrq = 0;929		}930 931		if (tty_insert_flip_char(port, rx, flg) == 0)932			sport->port.icount.buf_overrun++;933	}934 935out:936	if (overrun) {937		sport->port.icount.overrun += overrun;938 939		/*940		 * Overruns cause FIFO pointers to become missaligned.941		 * Flushing the receive FIFO reinitializes the pointers.942		 */943		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);944		writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);945	}946 947	uart_unlock_and_check_sysrq(&sport->port);948 949	tty_flip_buffer_push(port);950}951 952static void lpuart32_txint(struct lpuart_port *sport)953{954	uart_port_lock(&sport->port);955	lpuart32_transmit_buffer(sport);956	uart_port_unlock(&sport->port);957}958 959static void lpuart32_rxint(struct lpuart_port *sport)960{961	unsigned int flg, ignored = 0;962	struct tty_port *port = &sport->port.state->port;963	unsigned long rx, sr;964	bool is_break;965 966	uart_port_lock(&sport->port);967 968	while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {969		flg = TTY_NORMAL;970		sport->port.icount.rx++;971		/*972		 * to clear the FE, OR, NF, FE, PE flags,973		 * read STAT then read DATA reg974		 */975		sr = lpuart32_read(&sport->port, UARTSTAT);976		rx = lpuart32_read(&sport->port, UARTDATA);977		rx &= UARTDATA_MASK;978 979		/*980		 * The LPUART can't distinguish between a break and a framing error,981		 * thus we assume it is a break if the received data is zero.982		 */983		is_break = (sr & UARTSTAT_FE) && !rx;984 985		if (is_break && uart_handle_break(&sport->port))986			continue;987 988		if (uart_prepare_sysrq_char(&sport->port, rx))989			continue;990 991		if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {992			if (sr & UARTSTAT_PE) {993				sport->port.icount.parity++;994			} else if (sr & UARTSTAT_FE) {995				if (is_break)996					sport->port.icount.brk++;997				else998					sport->port.icount.frame++;999			}1000 1001			if (sr & UARTSTAT_OR)1002				sport->port.icount.overrun++;1003 1004			if (sr & sport->port.ignore_status_mask) {1005				if (++ignored > 100)1006					goto out;1007				continue;1008			}1009 1010			sr &= sport->port.read_status_mask;1011 1012			if (sr & UARTSTAT_PE) {1013				flg = TTY_PARITY;1014			} else if (sr & UARTSTAT_FE) {1015				if (is_break)1016					flg = TTY_BREAK;1017				else1018					flg = TTY_FRAME;1019			}1020 1021			if (sr & UARTSTAT_OR)1022				flg = TTY_OVERRUN;1023		}1024 1025		if (sport->is_cs7)1026			rx &= 0x7F;1027 1028		if (tty_insert_flip_char(port, rx, flg) == 0)1029			sport->port.icount.buf_overrun++;1030	}1031 1032out:1033	uart_unlock_and_check_sysrq(&sport->port);1034 1035	tty_flip_buffer_push(port);1036}1037 1038static irqreturn_t lpuart_int(int irq, void *dev_id)1039{1040	struct lpuart_port *sport = dev_id;1041	unsigned char sts;1042 1043	sts = readb(sport->port.membase + UARTSR1);1044 1045	/* SysRq, using dma, check for linebreak by framing err. */1046	if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {1047		readb(sport->port.membase + UARTDR);1048		uart_handle_break(&sport->port);1049		/* linebreak produces some garbage, removing it */1050		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);1051		return IRQ_HANDLED;1052	}1053 1054	if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)1055		lpuart_rxint(sport);1056 1057	if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)1058		lpuart_txint(sport);1059 1060	return IRQ_HANDLED;1061}1062 1063static inline void lpuart_handle_sysrq_chars(struct uart_port *port,1064					     unsigned char *p, int count)1065{1066	while (count--) {1067		if (*p && uart_handle_sysrq_char(port, *p))1068			return;1069		p++;1070	}1071}1072 1073static void lpuart_handle_sysrq(struct lpuart_port *sport)1074{1075	struct circ_buf *ring = &sport->rx_ring;1076	int count;1077 1078	if (ring->head < ring->tail) {1079		count = sport->rx_sgl.length - ring->tail;1080		lpuart_handle_sysrq_chars(&sport->port,1081					  ring->buf + ring->tail, count);1082		ring->tail = 0;1083	}1084 1085	if (ring->head > ring->tail) {1086		count = ring->head - ring->tail;1087		lpuart_handle_sysrq_chars(&sport->port,1088					  ring->buf + ring->tail, count);1089		ring->tail = ring->head;1090	}1091}1092 1093static int lpuart_tty_insert_flip_string(struct tty_port *port,1094	unsigned char *chars, size_t size, bool is_cs7)1095{1096	int i;1097 1098	if (is_cs7)1099		for (i = 0; i < size; i++)1100			chars[i] &= 0x7F;1101	return tty_insert_flip_string(port, chars, size);1102}1103 1104static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)1105{1106	struct tty_port *port = &sport->port.state->port;1107	struct dma_tx_state state;1108	enum dma_status dmastat;1109	struct dma_chan *chan = sport->dma_rx_chan;1110	struct circ_buf *ring = &sport->rx_ring;1111	unsigned long flags;1112	int count, copied;1113 1114	if (lpuart_is_32(sport)) {1115		unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);1116 1117		if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {1118			/* Clear the error flags */1119			lpuart32_write(&sport->port, sr, UARTSTAT);1120 1121			if (sr & UARTSTAT_PE)1122				sport->port.icount.parity++;1123			else if (sr & UARTSTAT_FE)1124				sport->port.icount.frame++;1125		}1126	} else {1127		unsigned char sr = readb(sport->port.membase + UARTSR1);1128 1129		if (sr & (UARTSR1_PE | UARTSR1_FE)) {1130			unsigned char cr2;1131 1132			/* Disable receiver during this operation... */1133			cr2 = readb(sport->port.membase + UARTCR2);1134			cr2 &= ~UARTCR2_RE;1135			writeb(cr2, sport->port.membase + UARTCR2);1136 1137			/* Read DR to clear the error flags */1138			readb(sport->port.membase + UARTDR);1139 1140			if (sr & UARTSR1_PE)1141				sport->port.icount.parity++;1142			else if (sr & UARTSR1_FE)1143				sport->port.icount.frame++;1144			/*1145			 * At this point parity/framing error is1146			 * cleared However, since the DMA already read1147			 * the data register and we had to read it1148			 * again after reading the status register to1149			 * properly clear the flags, the FIFO actually1150			 * underflowed... This requires a clearing of1151			 * the FIFO...1152			 */1153			if (readb(sport->port.membase + UARTSFIFO) &1154			    UARTSFIFO_RXUF) {1155				writeb(UARTSFIFO_RXUF,1156				       sport->port.membase + UARTSFIFO);1157				writeb(UARTCFIFO_RXFLUSH,1158				       sport->port.membase + UARTCFIFO);1159			}1160 1161			cr2 |= UARTCR2_RE;1162			writeb(cr2, sport->port.membase + UARTCR2);1163		}1164	}1165 1166	async_tx_ack(sport->dma_rx_desc);1167 1168	uart_port_lock_irqsave(&sport->port, &flags);1169 1170	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);1171	if (dmastat == DMA_ERROR) {1172		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");1173		uart_port_unlock_irqrestore(&sport->port, flags);1174		return;1175	}1176 1177	/* CPU claims ownership of RX DMA buffer */1178	dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,1179			    DMA_FROM_DEVICE);1180 1181	/*1182	 * ring->head points to the end of data already written by the DMA.1183	 * ring->tail points to the beginning of data to be read by the1184	 * framework.1185	 * The current transfer size should not be larger than the dma buffer1186	 * length.1187	 */1188	ring->head = sport->rx_sgl.length - state.residue;1189	BUG_ON(ring->head > sport->rx_sgl.length);1190 1191	/*1192	 * Silent handling of keys pressed in the sysrq timeframe1193	 */1194	if (sport->port.sysrq) {1195		lpuart_handle_sysrq(sport);1196		goto exit;1197	}1198 1199	/*1200	 * At this point ring->head may point to the first byte right after the1201	 * last byte of the dma buffer:1202	 * 0 <= ring->head <= sport->rx_sgl.length1203	 *1204	 * However ring->tail must always points inside the dma buffer:1205	 * 0 <= ring->tail <= sport->rx_sgl.length - 11206	 *1207	 * Since we use a ring buffer, we have to handle the case1208	 * where head is lower than tail. In such a case, we first read from1209	 * tail to the end of the buffer then reset tail.1210	 */1211	if (ring->head < ring->tail) {1212		count = sport->rx_sgl.length - ring->tail;1213 1214		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,1215					count, sport->is_cs7);1216		if (copied != count)1217			sport->port.icount.buf_overrun++;1218		ring->tail = 0;1219		sport->port.icount.rx += copied;1220	}1221 1222	/* Finally we read data from tail to head */1223	if (ring->tail < ring->head) {1224		count = ring->head - ring->tail;1225		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,1226					count, sport->is_cs7);1227		if (copied != count)1228			sport->port.icount.buf_overrun++;1229		/* Wrap ring->head if needed */1230		if (ring->head >= sport->rx_sgl.length)1231			ring->head = 0;1232		ring->tail = ring->head;1233		sport->port.icount.rx += copied;1234	}1235 1236	sport->last_residue = state.residue;1237 1238exit:1239	dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,1240			       DMA_FROM_DEVICE);1241 1242	uart_port_unlock_irqrestore(&sport->port, flags);1243 1244	tty_flip_buffer_push(port);1245	if (!sport->dma_idle_int)1246		mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);1247}1248 1249static void lpuart_dma_rx_complete(void *arg)1250{1251	struct lpuart_port *sport = arg;1252 1253	lpuart_copy_rx_to_tty(sport);1254}1255 1256static void lpuart32_dma_idleint(struct lpuart_port *sport)1257{1258	enum dma_status dmastat;1259	struct dma_chan *chan = sport->dma_rx_chan;1260	struct circ_buf *ring = &sport->rx_ring;1261	struct dma_tx_state state;1262	int count = 0;1263 1264	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);1265	if (dmastat == DMA_ERROR) {1266		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");1267		return;1268	}1269 1270	ring->head = sport->rx_sgl.length - state.residue;1271	count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);1272 1273	/* Check if new data received before copying */1274	if (count)1275		lpuart_copy_rx_to_tty(sport);1276}1277 1278static irqreturn_t lpuart32_int(int irq, void *dev_id)1279{1280	struct lpuart_port *sport = dev_id;1281	unsigned long sts, rxcount;1282 1283	sts = lpuart32_read(&sport->port, UARTSTAT);1284	rxcount = lpuart32_read(&sport->port, UARTWATER);1285	rxcount = rxcount >> UARTWATER_RXCNT_OFF;1286 1287	if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)1288		lpuart32_rxint(sport);1289 1290	if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)1291		lpuart32_txint(sport);1292 1293	if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int)1294		lpuart32_dma_idleint(sport);1295 1296	lpuart32_write(&sport->port, sts, UARTSTAT);1297	return IRQ_HANDLED;1298}1299 1300/*1301 * Timer function to simulate the hardware EOP (End Of Package) event.1302 * The timer callback is to check for new RX data and copy to TTY buffer.1303 * If no new data are received since last interval, the EOP condition is1304 * met, complete the DMA transfer by copying the data. Otherwise, just1305 * restart timer.1306 */1307static void lpuart_timer_func(struct timer_list *t)1308{1309	struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);1310	enum dma_status dmastat;1311	struct dma_chan *chan = sport->dma_rx_chan;1312	struct circ_buf *ring = &sport->rx_ring;1313	struct dma_tx_state state;1314	unsigned long flags;1315	int count;1316 1317	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);1318	if (dmastat == DMA_ERROR) {1319		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");1320		return;1321	}1322 1323	ring->head = sport->rx_sgl.length - state.residue;1324	count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);1325 1326	/* Check if new data received before copying */1327	if ((count != 0) && (sport->last_residue == state.residue))1328		lpuart_copy_rx_to_tty(sport);1329	else1330		mod_timer(&sport->lpuart_timer,1331			  jiffies + sport->dma_rx_timeout);1332 1333	if (uart_port_trylock_irqsave(&sport->port, &flags)) {1334		sport->last_residue = state.residue;1335		uart_port_unlock_irqrestore(&sport->port, flags);1336	}1337}1338 1339static inline int lpuart_start_rx_dma(struct lpuart_port *sport)1340{1341	struct dma_slave_config dma_rx_sconfig = {};1342	struct circ_buf *ring = &sport->rx_ring;1343	int ret, nent;1344	struct tty_port *port = &sport->port.state->port;1345	struct tty_struct *tty = port->tty;1346	struct ktermios *termios = &tty->termios;1347	struct dma_chan *chan = sport->dma_rx_chan;1348	unsigned int bits = tty_get_frame_size(termios->c_cflag);1349	unsigned int baud = tty_get_baud_rate(tty);1350 1351	/*1352	 * Calculate length of one DMA buffer size to keep latency below1353	 * 10ms at any baud rate.1354	 */1355	sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;1356	sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));1357	sport->rx_dma_rng_buf_len = max_t(int,1358					  sport->rxfifo_size * 2,1359					  sport->rx_dma_rng_buf_len);1360	/*1361	 * Keep this condition check in case rxfifo_size is unavailable1362	 * for some SoCs.1363	 */1364	if (sport->rx_dma_rng_buf_len < 16)1365		sport->rx_dma_rng_buf_len = 16;1366 1367	sport->last_residue = 0;1368	sport->dma_rx_timeout = max(nsecs_to_jiffies(1369		sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);1370 1371	ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);1372	if (!ring->buf)1373		return -ENOMEM;1374 1375	sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);1376	nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,1377			  DMA_FROM_DEVICE);1378 1379	if (!nent) {1380		dev_err(sport->port.dev, "DMA Rx mapping error\n");1381		return -EINVAL;1382	}1383 1384	dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);1385	dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;1386	dma_rx_sconfig.src_maxburst = 1;1387	dma_rx_sconfig.direction = DMA_DEV_TO_MEM;1388	ret = dmaengine_slave_config(chan, &dma_rx_sconfig);1389 1390	if (ret < 0) {1391		dev_err(sport->port.dev,1392				"DMA Rx slave config failed, err = %d\n", ret);1393		return ret;1394	}1395 1396	sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,1397				 sg_dma_address(&sport->rx_sgl),1398				 sport->rx_sgl.length,1399				 sport->rx_sgl.length / 2,1400				 DMA_DEV_TO_MEM,1401				 DMA_PREP_INTERRUPT);1402	if (!sport->dma_rx_desc) {1403		dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");1404		return -EFAULT;1405	}1406 1407	sport->dma_rx_desc->callback = lpuart_dma_rx_complete;1408	sport->dma_rx_desc->callback_param = sport;1409	sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);1410	dma_async_issue_pending(chan);1411 1412	if (lpuart_is_32(sport)) {1413		unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);1414 1415		lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);1416 1417		if (sport->dma_idle_int) {1418			unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);1419 1420			lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);1421		}1422	} else {1423		writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,1424		       sport->port.membase + UARTCR5);1425	}1426 1427	return 0;1428}1429 1430static void lpuart_dma_rx_free(struct uart_port *port)1431{1432	struct lpuart_port *sport = container_of(port,1433					struct lpuart_port, port);1434	struct dma_chan *chan = sport->dma_rx_chan;1435 1436	dmaengine_terminate_sync(chan);1437	if (!sport->dma_idle_int)1438		del_timer_sync(&sport->lpuart_timer);1439 1440	dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);1441	kfree(sport->rx_ring.buf);1442	sport->rx_ring.tail = 0;1443	sport->rx_ring.head = 0;1444	sport->dma_rx_desc = NULL;1445	sport->dma_rx_cookie = -EINVAL;1446}1447 1448static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,1449			struct serial_rs485 *rs485)1450{1451	struct lpuart_port *sport = container_of(port,1452			struct lpuart_port, port);1453 1454	u8 modem = readb(sport->port.membase + UARTMODEM) &1455		~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);1456	writeb(modem, sport->port.membase + UARTMODEM);1457 1458	if (rs485->flags & SER_RS485_ENABLED) {1459		/* Enable auto RS-485 RTS mode */1460		modem |= UARTMODEM_TXRTSE;1461 1462		/*1463		 * The hardware defaults to RTS logic HIGH while transfer.1464		 * Switch polarity in case RTS shall be logic HIGH1465		 * after transfer.1466		 * Note: UART is assumed to be active high.1467		 */1468		if (rs485->flags & SER_RS485_RTS_ON_SEND)1469			modem |= UARTMODEM_TXRTSPOL;1470		else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)1471			modem &= ~UARTMODEM_TXRTSPOL;1472	}1473 1474	writeb(modem, sport->port.membase + UARTMODEM);1475	return 0;1476}1477 1478static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,1479			struct serial_rs485 *rs485)1480{1481	struct lpuart_port *sport = container_of(port,1482			struct lpuart_port, port);1483 1484	unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)1485				& ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);1486	lpuart32_write(&sport->port, modem, UARTMODIR);1487 1488	if (rs485->flags & SER_RS485_ENABLED) {1489		/* Enable auto RS-485 RTS mode */1490		modem |= UARTMODIR_TXRTSE;1491 1492		/*1493		 * The hardware defaults to RTS logic HIGH while transfer.1494		 * Switch polarity in case RTS shall be logic HIGH1495		 * after transfer.1496		 * Note: UART is assumed to be active high.1497		 */1498		if (rs485->flags & SER_RS485_RTS_ON_SEND)1499			modem |= UARTMODIR_TXRTSPOL;1500		else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)1501			modem &= ~UARTMODIR_TXRTSPOL;1502	}1503 1504	lpuart32_write(&sport->port, modem, UARTMODIR);1505	return 0;1506}1507 1508static unsigned int lpuart_get_mctrl(struct uart_port *port)1509{1510	unsigned int mctrl = 0;1511	u8 reg;1512 1513	reg = readb(port->membase + UARTCR1);1514	if (reg & UARTCR1_LOOPS)1515		mctrl |= TIOCM_LOOP;1516 1517	return mctrl;1518}1519 1520static unsigned int lpuart32_get_mctrl(struct uart_port *port)1521{1522	unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;1523	u32 reg;1524 1525	reg = lpuart32_read(port, UARTCTRL);1526	if (reg & UARTCTRL_LOOPS)1527		mctrl |= TIOCM_LOOP;1528 1529	return mctrl;1530}1531 1532static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)1533{1534	u8 reg;1535 1536	reg = readb(port->membase + UARTCR1);1537 1538	/* for internal loopback we need LOOPS=1 and RSRC=0 */1539	reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);1540	if (mctrl & TIOCM_LOOP)1541		reg |= UARTCR1_LOOPS;1542 1543	writeb(reg, port->membase + UARTCR1);1544}1545 1546static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)1547{1548	u32 reg;1549 1550	reg = lpuart32_read(port, UARTCTRL);1551 1552	/* for internal loopback we need LOOPS=1 and RSRC=0 */1553	reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);1554	if (mctrl & TIOCM_LOOP)1555		reg |= UARTCTRL_LOOPS;1556 1557	lpuart32_write(port, reg, UARTCTRL);1558}1559 1560static void lpuart_break_ctl(struct uart_port *port, int break_state)1561{1562	unsigned char temp;1563 1564	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;1565 1566	if (break_state != 0)1567		temp |= UARTCR2_SBK;1568 1569	writeb(temp, port->membase + UARTCR2);1570}1571 1572static void lpuart32_break_ctl(struct uart_port *port, int break_state)1573{1574	unsigned long temp;1575 1576	temp = lpuart32_read(port, UARTCTRL);1577 1578	/*1579	 * LPUART IP now has two known bugs, one is CTS has higher priority than the1580	 * break signal, which causes the break signal sending through UARTCTRL_SBK1581	 * may impacted by the CTS input if the HW flow control is enabled. It1582	 * exists on all platforms we support in this driver.1583	 * Another bug is i.MX8QM LPUART may have an additional break character1584	 * being sent after SBK was cleared.1585	 * To avoid above two bugs, we use Transmit Data Inversion function to send1586	 * the break signal instead of UARTCTRL_SBK.1587	 */1588	if (break_state != 0) {1589		/*1590		 * Disable the transmitter to prevent any data from being sent out1591		 * during break, then invert the TX line to send break.1592		 */1593		temp &= ~UARTCTRL_TE;1594		lpuart32_write(port, temp, UARTCTRL);1595		temp |= UARTCTRL_TXINV;1596		lpuart32_write(port, temp, UARTCTRL);1597	} else {1598		/* Disable the TXINV to turn off break and re-enable transmitter. */1599		temp &= ~UARTCTRL_TXINV;1600		lpuart32_write(port, temp, UARTCTRL);1601		temp |= UARTCTRL_TE;1602		lpuart32_write(port, temp, UARTCTRL);1603	}1604}1605 1606static void lpuart_setup_watermark(struct lpuart_port *sport)1607{1608	unsigned char val, cr2;1609	unsigned char cr2_saved;1610 1611	cr2 = readb(sport->port.membase + UARTCR2);1612	cr2_saved = cr2;1613	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |1614			UARTCR2_RIE | UARTCR2_RE);1615	writeb(cr2, sport->port.membase + UARTCR2);1616 1617	val = readb(sport->port.membase + UARTPFIFO);1618	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,1619			sport->port.membase + UARTPFIFO);1620 1621	/* flush Tx and Rx FIFO */1622	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,1623			sport->port.membase + UARTCFIFO);1624 1625	/* explicitly clear RDRF */1626	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {1627		readb(sport->port.membase + UARTDR);1628		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);1629	}1630 1631	if (uart_console(&sport->port))1632		sport->rx_watermark = 1;1633	writeb(0, sport->port.membase + UARTTWFIFO);1634	writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);1635 1636	/* Restore cr2 */1637	writeb(cr2_saved, sport->port.membase + UARTCR2);1638}1639 1640static void lpuart_setup_watermark_enable(struct lpuart_port *sport)1641{1642	unsigned char cr2;1643 1644	lpuart_setup_watermark(sport);1645 1646	cr2 = readb(sport->port.membase + UARTCR2);1647	cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;1648	writeb(cr2, sport->port.membase + UARTCR2);1649}1650 1651static void lpuart32_setup_watermark(struct lpuart_port *sport)1652{1653	unsigned long val, ctrl;1654	unsigned long ctrl_saved;1655 1656	ctrl = lpuart32_read(&sport->port, UARTCTRL);1657	ctrl_saved = ctrl;1658	ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |1659			UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);1660	lpuart32_write(&sport->port, ctrl, UARTCTRL);1661 1662	/* enable FIFO mode */1663	val = lpuart32_read(&sport->port, UARTFIFO);1664	val |= UARTFIFO_TXFE | UARTFIFO_RXFE;1665	val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;1666	val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);1667	lpuart32_write(&sport->port, val, UARTFIFO);1668 1669	/* set the watermark */1670	if (uart_console(&sport->port))1671		sport->rx_watermark = 1;1672	val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |1673	      (0x0 << UARTWATER_TXWATER_OFF);1674	lpuart32_write(&sport->port, val, UARTWATER);1675 1676	/* set RTS watermark */1677	if (!uart_console(&sport->port)) {1678		val = lpuart32_read(&sport->port, UARTMODIR);1679		val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);1680		lpuart32_write(&sport->port, val, UARTMODIR);1681	}1682 1683	/* Restore cr2 */1684	lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);1685}1686 1687static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)1688{1689	u32 temp;1690 1691	lpuart32_setup_watermark(sport);1692 1693	temp = lpuart32_read(&sport->port, UARTCTRL);1694	temp |= UARTCTRL_RE | UARTCTRL_TE;1695	temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);1696	lpuart32_write(&sport->port, temp, UARTCTRL);1697}1698 1699static void rx_dma_timer_init(struct lpuart_port *sport)1700{1701	if (sport->dma_idle_int)1702		return;1703 1704	timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);1705	sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;1706	add_timer(&sport->lpuart_timer);1707}1708 1709static void lpuart_request_dma(struct lpuart_port *sport)1710{1711	sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");1712	if (IS_ERR(sport->dma_tx_chan)) {1713		dev_dbg_once(sport->port.dev,1714			     "DMA tx channel request failed, operating without tx DMA (%ld)\n",1715			     PTR_ERR(sport->dma_tx_chan));1716		sport->dma_tx_chan = NULL;1717	}1718 1719	sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");1720	if (IS_ERR(sport->dma_rx_chan)) {1721		dev_dbg_once(sport->port.dev,1722			     "DMA rx channel request failed, operating without rx DMA (%ld)\n",1723			     PTR_ERR(sport->dma_rx_chan));1724		sport->dma_rx_chan = NULL;1725	}1726}1727 1728static void lpuart_tx_dma_startup(struct lpuart_port *sport)1729{1730	u32 uartbaud;1731	int ret;1732 1733	if (uart_console(&sport->port))1734		goto err;1735 1736	if (!sport->dma_tx_chan)1737		goto err;1738 1739	ret = lpuart_dma_tx_request(&sport->port);1740	if (ret)1741		goto err;1742 1743	init_waitqueue_head(&sport->dma_wait);1744	sport->lpuart_dma_tx_use = true;1745	if (lpuart_is_32(sport)) {1746		uartbaud = lpuart32_read(&sport->port, UARTBAUD);1747		lpuart32_write(&sport->port,1748			       uartbaud | UARTBAUD_TDMAE, UARTBAUD);1749	} else {1750		writeb(readb(sport->port.membase + UARTCR5) |1751		       UARTCR5_TDMAS, sport->port.membase + UARTCR5);1752	}1753 1754	return;1755 1756err:1757	sport->lpuart_dma_tx_use = false;1758}1759 1760static void lpuart_rx_dma_startup(struct lpuart_port *sport)1761{1762	int ret;1763	unsigned char cr3;1764 1765	if (uart_console(&sport->port))1766		goto err;1767 1768	if (!sport->dma_rx_chan)1769		goto err;1770 1771	/* set default Rx DMA timeout */1772	sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);1773 1774	ret = lpuart_start_rx_dma(sport);1775	if (ret)1776		goto err;1777 1778	if (!sport->dma_rx_timeout)1779		sport->dma_rx_timeout = 1;1780 1781	sport->lpuart_dma_rx_use = true;1782	rx_dma_timer_init(sport);1783 1784	if (sport->port.has_sysrq && !lpuart_is_32(sport)) {1785		cr3 = readb(sport->port.membase + UARTCR3);1786		cr3 |= UARTCR3_FEIE;1787		writeb(cr3, sport->port.membase + UARTCR3);1788	}1789 1790	return;1791 1792err:1793	sport->lpuart_dma_rx_use = false;1794}1795 1796static void lpuart_hw_setup(struct lpuart_port *sport)1797{1798	unsigned long flags;1799 1800	uart_port_lock_irqsave(&sport->port, &flags);1801 1802	lpuart_setup_watermark_enable(sport);1803 1804	lpuart_rx_dma_startup(sport);1805	lpuart_tx_dma_startup(sport);1806 1807	uart_port_unlock_irqrestore(&sport->port, flags);1808}1809 1810static int lpuart_startup(struct uart_port *port)1811{1812	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);1813	unsigned char temp;1814 1815	/* determine FIFO size and enable FIFO mode */1816	temp = readb(sport->port.membase + UARTPFIFO);1817 1818	sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &1819					    UARTPFIFO_FIFOSIZE_MASK);1820	sport->port.fifosize = sport->txfifo_size;1821 1822	sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &1823					    UARTPFIFO_FIFOSIZE_MASK);1824 1825	lpuart_request_dma(sport);1826	lpuart_hw_setup(sport);1827 1828	return 0;1829}1830 1831static void lpuart32_hw_disable(struct lpuart_port *sport)1832{1833	unsigned long temp;1834 1835	temp = lpuart32_read(&sport->port, UARTCTRL);1836	temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |1837		  UARTCTRL_TIE | UARTCTRL_TE);1838	lpuart32_write(&sport->port, temp, UARTCTRL);1839}1840 1841static void lpuart32_configure(struct lpuart_port *sport)1842{1843	unsigned long temp;1844 1845	temp = lpuart32_read(&sport->port, UARTCTRL);1846	if (!sport->lpuart_dma_rx_use)1847		temp |= UARTCTRL_RIE | UARTCTRL_ILIE;1848	if (!sport->lpuart_dma_tx_use)1849		temp |= UARTCTRL_TIE;1850	lpuart32_write(&sport->port, temp, UARTCTRL);1851}1852 1853static void lpuart32_hw_setup(struct lpuart_port *sport)1854{1855	unsigned long flags;1856 1857	uart_port_lock_irqsave(&sport->port, &flags);1858 1859	lpuart32_hw_disable(sport);1860 1861	lpuart_rx_dma_startup(sport);1862	lpuart_tx_dma_startup(sport);1863 1864	lpuart32_setup_watermark_enable(sport);1865	lpuart32_configure(sport);1866 1867	uart_port_unlock_irqrestore(&sport->port, flags);1868}1869 1870static int lpuart32_startup(struct uart_port *port)1871{1872	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);1873	unsigned long temp;1874 1875	/* determine FIFO size */1876	temp = lpuart32_read(&sport->port, UARTFIFO);1877 1878	sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &1879					    UARTFIFO_FIFOSIZE_MASK);1880	sport->port.fifosize = sport->txfifo_size;1881 1882	sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &1883					    UARTFIFO_FIFOSIZE_MASK);1884 1885	/*1886	 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.1887	 * Although they support the RX/TXSIZE fields, their encoding is1888	 * different. Eg the reference manual states 0b101 is 16 words.1889	 */1890	if (is_layerscape_lpuart(sport)) {1891		sport->rxfifo_size = 16;1892		sport->txfifo_size = 16;1893		sport->port.fifosize = sport->txfifo_size;1894	}1895 1896	lpuart_request_dma(sport);1897	lpuart32_hw_setup(sport);1898 1899	return 0;1900}1901 1902static void lpuart_dma_shutdown(struct lpuart_port *sport)1903{1904	if (sport->lpuart_dma_rx_use) {1905		lpuart_dma_rx_free(&sport->port);1906		sport->lpuart_dma_rx_use = false;1907	}1908 1909	if (sport->lpuart_dma_tx_use) {1910		if (wait_event_interruptible_timeout(sport->dma_wait,1911			!sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {1912			sport->dma_tx_in_progress = false;1913			dmaengine_terminate_sync(sport->dma_tx_chan);1914		}1915		sport->lpuart_dma_tx_use = false;1916	}1917 1918	if (sport->dma_tx_chan)1919		dma_release_channel(sport->dma_tx_chan);1920	if (sport->dma_rx_chan)1921		dma_release_channel(sport->dma_rx_chan);1922}1923 1924static void lpuart_shutdown(struct uart_port *port)1925{1926	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);1927	unsigned char temp;1928	unsigned long flags;1929 1930	uart_port_lock_irqsave(port, &flags);1931 1932	/* disable Rx/Tx and interrupts */1933	temp = readb(port->membase + UARTCR2);1934	temp &= ~(UARTCR2_TE | UARTCR2_RE |1935			UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);1936	writeb(temp, port->membase + UARTCR2);1937 1938	uart_port_unlock_irqrestore(port, flags);1939 1940	lpuart_dma_shutdown(sport);1941}1942 1943static void lpuart32_shutdown(struct uart_port *port)1944{1945	struct lpuart_port *sport =1946		container_of(port, struct lpuart_port, port);1947	unsigned long temp;1948	unsigned long flags;1949 1950	uart_port_lock_irqsave(port, &flags);1951 1952	/* clear status */1953	temp = lpuart32_read(&sport->port, UARTSTAT);1954	lpuart32_write(&sport->port, temp, UARTSTAT);1955 1956	/* disable Rx/Tx DMA */1957	temp = lpuart32_read(port, UARTBAUD);1958	temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);1959	lpuart32_write(port, temp, UARTBAUD);1960 1961	/* disable Rx/Tx and interrupts and break condition */1962	temp = lpuart32_read(port, UARTCTRL);1963	temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |1964			UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);1965	lpuart32_write(port, temp, UARTCTRL);1966 1967	uart_port_unlock_irqrestore(port, flags);1968 1969	lpuart_dma_shutdown(sport);1970}1971 1972static void1973lpuart_set_termios(struct uart_port *port, struct ktermios *termios,1974		   const struct ktermios *old)1975{1976	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);1977	unsigned long flags;1978	unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;1979	unsigned int  baud;1980	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;1981	unsigned int sbr, brfa;1982 1983	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);1984	old_cr2 = readb(sport->port.membase + UARTCR2);1985	cr3 = readb(sport->port.membase + UARTCR3);1986	cr4 = readb(sport->port.membase + UARTCR4);1987	bdh = readb(sport->port.membase + UARTBDH);1988	modem = readb(sport->port.membase + UARTMODEM);1989	/*1990	 * only support CS8 and CS7, and for CS7 must enable PE.1991	 * supported mode:1992	 *  - (7,e/o,1)1993	 *  - (8,n,1)1994	 *  - (8,m/s,1)1995	 *  - (8,e/o,1)1996	 */1997	while ((termios->c_cflag & CSIZE) != CS8 &&1998		(termios->c_cflag & CSIZE) != CS7) {1999		termios->c_cflag &= ~CSIZE;2000		termios->c_cflag |= old_csize;2001		old_csize = CS8;2002	}2003 2004	if ((termios->c_cflag & CSIZE) == CS8 ||2005		(termios->c_cflag & CSIZE) == CS7)2006		cr1 = old_cr1 & ~UARTCR1_M;2007 2008	if (termios->c_cflag & CMSPAR) {2009		if ((termios->c_cflag & CSIZE) != CS8) {2010			termios->c_cflag &= ~CSIZE;2011			termios->c_cflag |= CS8;2012		}2013		cr1 |= UARTCR1_M;2014	}2015 2016	/*2017	 * When auto RS-485 RTS mode is enabled,2018	 * hardware flow control need to be disabled.2019	 */2020	if (sport->port.rs485.flags & SER_RS485_ENABLED)2021		termios->c_cflag &= ~CRTSCTS;2022 2023	if (termios->c_cflag & CRTSCTS)2024		modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;2025	else2026		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);2027 2028	termios->c_cflag &= ~CSTOPB;2029 2030	/* parity must be enabled when CS7 to match 8-bits format */2031	if ((termios->c_cflag & CSIZE) == CS7)2032		termios->c_cflag |= PARENB;2033 2034	if (termios->c_cflag & PARENB) {2035		if (termios->c_cflag & CMSPAR) {2036			cr1 &= ~UARTCR1_PE;2037			if (termios->c_cflag & PARODD)2038				cr3 |= UARTCR3_T8;2039			else2040				cr3 &= ~UARTCR3_T8;2041		} else {2042			cr1 |= UARTCR1_PE;2043			if ((termios->c_cflag & CSIZE) == CS8)2044				cr1 |= UARTCR1_M;2045			if (termios->c_cflag & PARODD)2046				cr1 |= UARTCR1_PT;2047			else2048				cr1 &= ~UARTCR1_PT;2049		}2050	} else {2051		cr1 &= ~UARTCR1_PE;2052	}2053 2054	/* ask the core to calculate the divisor */2055	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);2056 2057	/*2058	 * Need to update the Ring buffer length according to the selected2059	 * baud rate and restart Rx DMA path.2060	 *2061	 * Since timer function acqures sport->port.lock, need to stop before2062	 * acquring same lock because otherwise del_timer_sync() can deadlock.2063	 */2064	if (old && sport->lpuart_dma_rx_use)2065		lpuart_dma_rx_free(&sport->port);2066 2067	uart_port_lock_irqsave(&sport->port, &flags);2068 2069	sport->port.read_status_mask = 0;2070	if (termios->c_iflag & INPCK)2071		sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;2072	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))2073		sport->port.read_status_mask |= UARTSR1_FE;2074 2075	/* characters to ignore */2076	sport->port.ignore_status_mask = 0;2077	if (termios->c_iflag & IGNPAR)2078		sport->port.ignore_status_mask |= UARTSR1_PE;2079	if (termios->c_iflag & IGNBRK) {2080		sport->port.ignore_status_mask |= UARTSR1_FE;2081		/*2082		 * if we're ignoring parity and break indicators,2083		 * ignore overruns too (for real raw support).2084		 */2085		if (termios->c_iflag & IGNPAR)2086			sport->port.ignore_status_mask |= UARTSR1_OR;2087	}2088 2089	/* update the per-port timeout */2090	uart_update_timeout(port, termios->c_cflag, baud);2091 2092	/* wait transmit engin complete */2093	lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);2094 2095	/* disable transmit and receive */2096	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),2097			sport->port.membase + UARTCR2);2098 2099	sbr = sport->port.uartclk / (16 * baud);2100	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;2101	bdh &= ~UARTBDH_SBR_MASK;2102	bdh |= (sbr >> 8) & 0x1F;2103	cr4 &= ~UARTCR4_BRFA_MASK;2104	brfa &= UARTCR4_BRFA_MASK;2105	writeb(cr4 | brfa, sport->port.membase + UARTCR4);2106	writeb(bdh, sport->port.membase + UARTBDH);2107	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);2108	writeb(cr3, sport->port.membase + UARTCR3);2109	writeb(cr1, sport->port.membase + UARTCR1);2110	writeb(modem, sport->port.membase + UARTMODEM);2111 2112	/* restore control register */2113	writeb(old_cr2, sport->port.membase + UARTCR2);2114 2115	if (old && sport->lpuart_dma_rx_use) {2116		if (!lpuart_start_rx_dma(sport))2117			rx_dma_timer_init(sport);2118		else2119			sport->lpuart_dma_rx_use = false;2120	}2121 2122	uart_port_unlock_irqrestore(&sport->port, flags);2123}2124 2125static void __lpuart32_serial_setbrg(struct uart_port *port,2126				     unsigned int baudrate, bool use_rx_dma,2127				     bool use_tx_dma)2128{2129	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;2130	u32 clk = port->uartclk;2131 2132	/*2133	 * The idea is to use the best OSR (over-sampling rate) possible.2134	 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.2135	 * Loop to find the best OSR value possible, one that generates minimum2136	 * baud_diff iterate through the rest of the supported values of OSR.2137	 *2138	 * Calculation Formula:2139	 *  Baud Rate = baud clock / ((OSR+1) × SBR)2140	 */2141	baud_diff = baudrate;2142	osr = 0;2143	sbr = 0;2144 2145	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {2146		/* calculate the temporary sbr value  */2147		tmp_sbr = (clk / (baudrate * tmp_osr));2148		if (tmp_sbr == 0)2149			tmp_sbr = 1;2150 2151		/*2152		 * calculate the baud rate difference based on the temporary2153		 * osr and sbr values2154		 */2155		tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;2156 2157		/* select best values between sbr and sbr+1 */2158		tmp = clk / (tmp_osr * (tmp_sbr + 1));2159		if (tmp_diff > (baudrate - tmp)) {2160			tmp_diff = baudrate - tmp;2161			tmp_sbr++;2162		}2163 2164		if (tmp_sbr > UARTBAUD_SBR_MASK)2165			continue;2166 2167		if (tmp_diff <= baud_diff) {2168			baud_diff = tmp_diff;2169			osr = tmp_osr;2170			sbr = tmp_sbr;2171 2172			if (!baud_diff)2173				break;2174		}2175	}2176 2177	/* handle buadrate outside acceptable rate */2178	if (baud_diff > ((baudrate / 100) * 3))2179		dev_warn(port->dev,2180			 "unacceptable baud rate difference of more than 3%%\n");2181 2182	tmp = lpuart32_read(port, UARTBAUD);2183 2184	if ((osr > 3) && (osr < 8))2185		tmp |= UARTBAUD_BOTHEDGE;2186 2187	tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);2188	tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;2189 2190	tmp &= ~UARTBAUD_SBR_MASK;2191	tmp |= sbr & UARTBAUD_SBR_MASK;2192 2193	if (!use_rx_dma)2194		tmp &= ~UARTBAUD_RDMAE;2195	if (!use_tx_dma)2196		tmp &= ~UARTBAUD_TDMAE;2197 2198	lpuart32_write(port, tmp, UARTBAUD);2199}2200 2201static void lpuart32_serial_setbrg(struct lpuart_port *sport,2202				   unsigned int baudrate)2203{2204	__lpuart32_serial_setbrg(&sport->port, baudrate,2205				 sport->lpuart_dma_rx_use,2206				 sport->lpuart_dma_tx_use);2207}2208 2209 2210static void2211lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,2212		     const struct ktermios *old)2213{2214	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);2215	unsigned long flags;2216	unsigned long ctrl, old_ctrl, bd, modem;2217	unsigned int  baud;2218	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;2219 2220	ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);2221	bd = lpuart32_read(&sport->port, UARTBAUD);2222	modem = lpuart32_read(&sport->port, UARTMODIR);2223	sport->is_cs7 = false;2224	/*2225	 * only support CS8 and CS7, and for CS7 must enable PE.2226	 * supported mode:2227	 *  - (7,e/o,1)2228	 *  - (8,n,1)2229	 *  - (8,m/s,1)2230	 *  - (8,e/o,1)2231	 */2232	while ((termios->c_cflag & CSIZE) != CS8 &&2233		(termios->c_cflag & CSIZE) != CS7) {2234		termios->c_cflag &= ~CSIZE;2235		termios->c_cflag |= old_csize;2236		old_csize = CS8;2237	}2238 2239	if ((termios->c_cflag & CSIZE) == CS8 ||2240		(termios->c_cflag & CSIZE) == CS7)2241		ctrl = old_ctrl & ~UARTCTRL_M;2242 2243	if (termios->c_cflag & CMSPAR) {2244		if ((termios->c_cflag & CSIZE) != CS8) {2245			termios->c_cflag &= ~CSIZE;2246			termios->c_cflag |= CS8;2247		}2248		ctrl |= UARTCTRL_M;2249	}2250 2251	/*2252	 * When auto RS-485 RTS mode is enabled,2253	 * hardware flow control need to be disabled.2254	 */2255	if (sport->port.rs485.flags & SER_RS485_ENABLED)2256		termios->c_cflag &= ~CRTSCTS;2257 2258	if (termios->c_cflag & CRTSCTS)2259		modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;2260	else2261		modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);2262 2263	if (termios->c_cflag & CSTOPB)2264		bd |= UARTBAUD_SBNS;2265	else2266		bd &= ~UARTBAUD_SBNS;2267 2268	/* parity must be enabled when CS7 to match 8-bits format */2269	if ((termios->c_cflag & CSIZE) == CS7)2270		termios->c_cflag |= PARENB;2271 2272	if ((termios->c_cflag & PARENB)) {2273		if (termios->c_cflag & CMSPAR) {2274			ctrl &= ~UARTCTRL_PE;2275			ctrl |= UARTCTRL_M;2276		} else {2277			ctrl |= UARTCTRL_PE;2278			if ((termios->c_cflag & CSIZE) == CS8)2279				ctrl |= UARTCTRL_M;2280			if (termios->c_cflag & PARODD)2281				ctrl |= UARTCTRL_PT;2282			else2283				ctrl &= ~UARTCTRL_PT;2284		}2285	} else {2286		ctrl &= ~UARTCTRL_PE;2287	}2288 2289	/* ask the core to calculate the divisor */2290	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);2291 2292	/*2293	 * Need to update the Ring buffer length according to the selected2294	 * baud rate and restart Rx DMA path.2295	 *2296	 * Since timer function acqures sport->port.lock, need to stop before2297	 * acquring same lock because otherwise del_timer_sync() can deadlock.2298	 */2299	if (old && sport->lpuart_dma_rx_use)2300		lpuart_dma_rx_free(&sport->port);2301 2302	uart_port_lock_irqsave(&sport->port, &flags);2303 2304	sport->port.read_status_mask = 0;2305	if (termios->c_iflag & INPCK)2306		sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;2307	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))2308		sport->port.read_status_mask |= UARTSTAT_FE;2309 2310	/* characters to ignore */2311	sport->port.ignore_status_mask = 0;2312	if (termios->c_iflag & IGNPAR)2313		sport->port.ignore_status_mask |= UARTSTAT_PE;2314	if (termios->c_iflag & IGNBRK) {2315		sport->port.ignore_status_mask |= UARTSTAT_FE;2316		/*2317		 * if we're ignoring parity and break indicators,2318		 * ignore overruns too (for real raw support).2319		 */2320		if (termios->c_iflag & IGNPAR)2321			sport->port.ignore_status_mask |= UARTSTAT_OR;2322	}2323 2324	/* update the per-port timeout */2325	uart_update_timeout(port, termios->c_cflag, baud);2326 2327	/*2328	 * LPUART Transmission Complete Flag may never be set while queuing a break2329	 * character, so skip waiting for transmission complete when UARTCTRL_SBK is2330	 * asserted.2331	 */2332	if (!(old_ctrl & UARTCTRL_SBK)) {2333		lpuart32_write(&sport->port, 0, UARTMODIR);2334		lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);2335	}2336 2337	/* disable transmit and receive */2338	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),2339		       UARTCTRL);2340 2341	lpuart32_write(&sport->port, bd, UARTBAUD);2342	lpuart32_serial_setbrg(sport, baud);2343	/* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */2344	lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);2345	/* restore control register */2346	lpuart32_write(&sport->port, ctrl, UARTCTRL);2347	/* re-enable the CTS if needed */2348	lpuart32_write(&sport->port, modem, UARTMODIR);2349 2350	if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)2351		sport->is_cs7 = true;2352 2353	if (old && sport->lpuart_dma_rx_use) {2354		if (!lpuart_start_rx_dma(sport))2355			rx_dma_timer_init(sport);2356		else2357			sport->lpuart_dma_rx_use = false;2358	}2359 2360	uart_port_unlock_irqrestore(&sport->port, flags);2361}2362 2363static const char *lpuart_type(struct uart_port *port)2364{2365	return "FSL_LPUART";2366}2367 2368static void lpuart_release_port(struct uart_port *port)2369{2370	/* nothing to do */2371}2372 2373static int lpuart_request_port(struct uart_port *port)2374{2375	return  0;2376}2377 2378/* configure/autoconfigure the port */2379static void lpuart_config_port(struct uart_port *port, int flags)2380{2381	if (flags & UART_CONFIG_TYPE)2382		port->type = PORT_LPUART;2383}2384 2385static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)2386{2387	int ret = 0;2388 2389	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)2390		ret = -EINVAL;2391	if (port->irq != ser->irq)2392		ret = -EINVAL;2393	if (ser->io_type != UPIO_MEM)2394		ret = -EINVAL;2395	if (port->uartclk / 16 != ser->baud_base)2396		ret = -EINVAL;2397	if (port->iobase != ser->port)2398		ret = -EINVAL;2399	if (ser->hub6 != 0)2400		ret = -EINVAL;2401	return ret;2402}2403 2404static const struct uart_ops lpuart_pops = {2405	.tx_empty	= lpuart_tx_empty,2406	.set_mctrl	= lpuart_set_mctrl,2407	.get_mctrl	= lpuart_get_mctrl,2408	.stop_tx	= lpuart_stop_tx,2409	.start_tx	= lpuart_start_tx,2410	.stop_rx	= lpuart_stop_rx,2411	.break_ctl	= lpuart_break_ctl,2412	.startup	= lpuart_startup,2413	.shutdown	= lpuart_shutdown,2414	.set_termios	= lpuart_set_termios,2415	.pm		= lpuart_uart_pm,2416	.type		= lpuart_type,2417	.request_port	= lpuart_request_port,2418	.release_port	= lpuart_release_port,2419	.config_port	= lpuart_config_port,2420	.verify_port	= lpuart_verify_port,2421	.flush_buffer	= lpuart_flush_buffer,2422#if defined(CONFIG_CONSOLE_POLL)2423	.poll_init	= lpuart_poll_init,2424	.poll_get_char	= lpuart_poll_get_char,2425	.poll_put_char	= lpuart_poll_put_char,2426#endif2427};2428 2429static const struct uart_ops lpuart32_pops = {2430	.tx_empty	= lpuart32_tx_empty,2431	.set_mctrl	= lpuart32_set_mctrl,2432	.get_mctrl	= lpuart32_get_mctrl,2433	.stop_tx	= lpuart32_stop_tx,2434	.start_tx	= lpuart32_start_tx,2435	.stop_rx	= lpuart32_stop_rx,2436	.break_ctl	= lpuart32_break_ctl,2437	.startup	= lpuart32_startup,2438	.shutdown	= lpuart32_shutdown,2439	.set_termios	= lpuart32_set_termios,2440	.pm		= lpuart_uart_pm,2441	.type		= lpuart_type,2442	.request_port	= lpuart_request_port,2443	.release_port	= lpuart_release_port,2444	.config_port	= lpuart_config_port,2445	.verify_port	= lpuart_verify_port,2446	.flush_buffer	= lpuart_flush_buffer,2447#if defined(CONFIG_CONSOLE_POLL)2448	.poll_init	= lpuart32_poll_init,2449	.poll_get_char	= lpuart32_poll_get_char,2450	.poll_put_char	= lpuart32_poll_put_char,2451#endif2452};2453 2454static struct lpuart_port *lpuart_ports[UART_NR];2455 2456#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE2457static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)2458{2459	lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);2460	writeb(ch, port->membase + UARTDR);2461}2462 2463static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)2464{2465	lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);2466	lpuart32_write(port, ch, UARTDATA);2467}2468 2469static void2470lpuart_console_write(struct console *co, const char *s, unsigned int count)2471{2472	struct lpuart_port *sport = lpuart_ports[co->index];2473	unsigned char  old_cr2, cr2;2474	unsigned long flags;2475	int locked = 1;2476 2477	if (oops_in_progress)2478		locked = uart_port_trylock_irqsave(&sport->port, &flags);2479	else2480		uart_port_lock_irqsave(&sport->port, &flags);2481 2482	/* first save CR2 and then disable interrupts */2483	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);2484	cr2 |= UARTCR2_TE | UARTCR2_RE;2485	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);2486	writeb(cr2, sport->port.membase + UARTCR2);2487 2488	uart_console_write(&sport->port, s, count, lpuart_console_putchar);2489 2490	/* wait for transmitter finish complete and restore CR2 */2491	lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);2492 2493	writeb(old_cr2, sport->port.membase + UARTCR2);2494 2495	if (locked)2496		uart_port_unlock_irqrestore(&sport->port, flags);2497}2498 2499static void2500lpuart32_console_write(struct console *co, const char *s, unsigned int count)2501{2502	struct lpuart_port *sport = lpuart_ports[co->index];2503	unsigned long  old_cr, cr;2504	unsigned long flags;2505	int locked = 1;2506 2507	if (oops_in_progress)2508		locked = uart_port_trylock_irqsave(&sport->port, &flags);2509	else2510		uart_port_lock_irqsave(&sport->port, &flags);2511 2512	/* first save CR2 and then disable interrupts */2513	cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);2514	cr |= UARTCTRL_TE | UARTCTRL_RE;2515	cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);2516	lpuart32_write(&sport->port, cr, UARTCTRL);2517 2518	uart_console_write(&sport->port, s, count, lpuart32_console_putchar);2519 2520	/* wait for transmitter finish complete and restore CR2 */2521	lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);2522 2523	lpuart32_write(&sport->port, old_cr, UARTCTRL);2524 2525	if (locked)2526		uart_port_unlock_irqrestore(&sport->port, flags);2527}2528 2529/*2530 * if the port was already initialised (eg, by a boot loader),2531 * try to determine the current setup.2532 */2533static void __init2534lpuart_console_get_options(struct lpuart_port *sport, int *baud,2535			   int *parity, int *bits)2536{2537	unsigned char cr, bdh, bdl, brfa;2538	unsigned int sbr, uartclk, baud_raw;2539 2540	cr = readb(sport->port.membase + UARTCR2);2541	cr &= UARTCR2_TE | UARTCR2_RE;2542	if (!cr)2543		return;2544 2545	/* ok, the port was enabled */2546 2547	cr = readb(sport->port.membase + UARTCR1);2548 2549	*parity = 'n';2550	if (cr & UARTCR1_PE) {2551		if (cr & UARTCR1_PT)2552			*parity = 'o';2553		else2554			*parity = 'e';2555	}2556 2557	if (cr & UARTCR1_M)2558		*bits = 9;2559	else2560		*bits = 8;2561 2562	bdh = readb(sport->port.membase + UARTBDH);2563	bdh &= UARTBDH_SBR_MASK;2564	bdl = readb(sport->port.membase + UARTBDL);2565	sbr = bdh;2566	sbr <<= 8;2567	sbr |= bdl;2568	brfa = readb(sport->port.membase + UARTCR4);2569	brfa &= UARTCR4_BRFA_MASK;2570 2571	uartclk = lpuart_get_baud_clk_rate(sport);2572	/*2573	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)2574	 */2575	baud_raw = uartclk / (16 * (sbr + brfa / 32));2576 2577	if (*baud != baud_raw)2578		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"2579				"from %d to %d\n", baud_raw, *baud);2580}2581 2582static void __init2583lpuart32_console_get_options(struct lpuart_port *sport, int *baud,2584			   int *parity, int *bits)2585{2586	unsigned long cr, bd;2587	unsigned int sbr, uartclk, baud_raw;2588 2589	cr = lpuart32_read(&sport->port, UARTCTRL);2590	cr &= UARTCTRL_TE | UARTCTRL_RE;2591	if (!cr)2592		return;2593 2594	/* ok, the port was enabled */2595 2596	cr = lpuart32_read(&sport->port, UARTCTRL);2597 2598	*parity = 'n';2599	if (cr & UARTCTRL_PE) {2600		if (cr & UARTCTRL_PT)2601			*parity = 'o';2602		else2603			*parity = 'e';2604	}2605 2606	if (cr & UARTCTRL_M)2607		*bits = 9;2608	else2609		*bits = 8;2610 2611	bd = lpuart32_read(&sport->port, UARTBAUD);2612	bd &= UARTBAUD_SBR_MASK;2613	if (!bd)2614		return;2615 2616	sbr = bd;2617	uartclk = lpuart_get_baud_clk_rate(sport);2618	/*2619	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)2620	 */2621	baud_raw = uartclk / (16 * sbr);2622 2623	if (*baud != baud_raw)2624		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"2625				"from %d to %d\n", baud_raw, *baud);2626}2627 2628static int __init lpuart_console_setup(struct console *co, char *options)2629{2630	struct lpuart_port *sport;2631	int baud = 115200;2632	int bits = 8;2633	int parity = 'n';2634	int flow = 'n';2635 2636	/*2637	 * check whether an invalid uart number has been specified, and2638	 * if so, search for the first available port that does have2639	 * console support.2640	 */2641	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))2642		co->index = 0;2643 2644	sport = lpuart_ports[co->index];2645	if (sport == NULL)2646		return -ENODEV;2647 2648	if (options)2649		uart_parse_options(options, &baud, &parity, &bits, &flow);2650	else2651		if (lpuart_is_32(sport))2652			lpuart32_console_get_options(sport, &baud, &parity, &bits);2653		else2654			lpuart_console_get_options(sport, &baud, &parity, &bits);2655 2656	if (lpuart_is_32(sport))2657		lpuart32_setup_watermark(sport);2658	else2659		lpuart_setup_watermark(sport);2660 2661	return uart_set_options(&sport->port, co, baud, parity, bits, flow);2662}2663 2664static struct uart_driver lpuart_reg;2665static struct console lpuart_console = {2666	.name		= DEV_NAME,2667	.write		= lpuart_console_write,2668	.device		= uart_console_device,2669	.setup		= lpuart_console_setup,2670	.flags		= CON_PRINTBUFFER,2671	.index		= -1,2672	.data		= &lpuart_reg,2673};2674 2675static struct console lpuart32_console = {2676	.name		= DEV_NAME,2677	.write		= lpuart32_console_write,2678	.device		= uart_console_device,2679	.setup		= lpuart_console_setup,2680	.flags		= CON_PRINTBUFFER,2681	.index		= -1,2682	.data		= &lpuart_reg,2683};2684 2685static void lpuart_early_write(struct console *con, const char *s, unsigned n)2686{2687	struct earlycon_device *dev = con->data;2688 2689	uart_console_write(&dev->port, s, n, lpuart_console_putchar);2690}2691 2692static void lpuart32_early_write(struct console *con, const char *s, unsigned n)2693{2694	struct earlycon_device *dev = con->data;2695 2696	uart_console_write(&dev->port, s, n, lpuart32_console_putchar);2697}2698 2699static int __init lpuart_early_console_setup(struct earlycon_device *device,2700					  const char *opt)2701{2702	if (!device->port.membase)2703		return -ENODEV;2704 2705	device->con->write = lpuart_early_write;2706	return 0;2707}2708 2709static int __init lpuart32_early_console_setup(struct earlycon_device *device,2710					  const char *opt)2711{2712	if (!device->port.membase)2713		return -ENODEV;2714 2715	if (device->port.iotype != UPIO_MEM32)2716		device->port.iotype = UPIO_MEM32BE;2717 2718	device->con->write = lpuart32_early_write;2719	return 0;2720}2721 2722static int __init ls1028a_early_console_setup(struct earlycon_device *device,2723					      const char *opt)2724{2725	u32 cr;2726 2727	if (!device->port.membase)2728		return -ENODEV;2729 2730	device->port.iotype = UPIO_MEM32;2731	device->con->write = lpuart32_early_write;2732 2733	/* set the baudrate */2734	if (device->port.uartclk && device->baud)2735		__lpuart32_serial_setbrg(&device->port, device->baud,2736					 false, false);2737 2738	/* enable transmitter */2739	cr = lpuart32_read(&device->port, UARTCTRL);2740	cr |= UARTCTRL_TE;2741	lpuart32_write(&device->port, cr, UARTCTRL);2742 2743	return 0;2744}2745 2746static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,2747						   const char *opt)2748{2749	if (!device->port.membase)2750		return -ENODEV;2751 2752	device->port.iotype = UPIO_MEM32;2753	device->port.membase += IMX_REG_OFF;2754	device->con->write = lpuart32_early_write;2755 2756	return 0;2757}2758OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);2759OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);2760OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);2761OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);2762OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);2763OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);2764OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);2765EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);2766EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);2767 2768#define LPUART_CONSOLE	(&lpuart_console)2769#define LPUART32_CONSOLE	(&lpuart32_console)2770#else2771#define LPUART_CONSOLE	NULL2772#define LPUART32_CONSOLE	NULL2773#endif2774 2775static struct uart_driver lpuart_reg = {2776	.owner		= THIS_MODULE,2777	.driver_name	= DRIVER_NAME,2778	.dev_name	= DEV_NAME,2779	.nr		= ARRAY_SIZE(lpuart_ports),2780	.cons		= LPUART_CONSOLE,2781};2782 2783static const struct serial_rs485 lpuart_rs485_supported = {2784	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,2785	/* delay_rts_* and RX_DURING_TX are not supported */2786};2787 2788static int lpuart_global_reset(struct lpuart_port *sport)2789{2790	struct uart_port *port = &sport->port;2791	void __iomem *global_addr;2792	unsigned long ctrl, bd;2793	unsigned int val = 0;2794	int ret;2795 2796	ret = clk_prepare_enable(sport->ipg_clk);2797	if (ret) {2798		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);2799		return ret;2800	}2801 2802	if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {2803		/*2804		 * If the transmitter is used by earlycon, wait for transmit engine to2805		 * complete and then reset.2806		 */2807		ctrl = lpuart32_read(port, UARTCTRL);2808		if (ctrl & UARTCTRL_TE) {2809			bd = lpuart32_read(&sport->port, UARTBAUD);2810			if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,2811					      port)) {2812				dev_warn(sport->port.dev,2813					 "timeout waiting for transmit engine to complete\n");2814				clk_disable_unprepare(sport->ipg_clk);2815				return 0;2816			}2817		}2818 2819		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;2820		writel(UART_GLOBAL_RST, global_addr);2821		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);2822		writel(0, global_addr);2823		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);2824 2825		/* Recover the transmitter for earlycon. */2826		if (ctrl & UARTCTRL_TE) {2827			lpuart32_write(port, bd, UARTBAUD);2828			lpuart32_write(port, ctrl, UARTCTRL);2829		}2830	}2831 2832	clk_disable_unprepare(sport->ipg_clk);2833	return 0;2834}2835 2836static int lpuart_probe(struct platform_device *pdev)2837{2838	const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);2839	struct device_node *np = pdev->dev.of_node;2840	struct lpuart_port *sport;2841	struct resource *res;2842	irq_handler_t handler;2843	int ret;2844 2845	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);2846	if (!sport)2847		return -ENOMEM;2848 2849	sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);2850	if (IS_ERR(sport->port.membase))2851		return PTR_ERR(sport->port.membase);2852 2853	sport->port.membase += sdata->reg_off;2854	sport->port.mapbase = res->start + sdata->reg_off;2855	sport->port.dev = &pdev->dev;2856	sport->port.type = PORT_LPUART;2857	sport->devtype = sdata->devtype;2858	sport->rx_watermark = sdata->rx_watermark;2859	sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||2860			      is_imx8qxp_lpuart(sport);2861	ret = platform_get_irq(pdev, 0);2862	if (ret < 0)2863		return ret;2864	sport->port.irq = ret;2865	sport->port.iotype = sdata->iotype;2866	if (lpuart_is_32(sport))2867		sport->port.ops = &lpuart32_pops;2868	else2869		sport->port.ops = &lpuart_pops;2870	sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);2871	sport->port.flags = UPF_BOOT_AUTOCONF;2872 2873	if (lpuart_is_32(sport))2874		sport->port.rs485_config = lpuart32_config_rs485;2875	else2876		sport->port.rs485_config = lpuart_config_rs485;2877	sport->port.rs485_supported = lpuart_rs485_supported;2878 2879	sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");2880	if (IS_ERR(sport->ipg_clk)) {2881		ret = PTR_ERR(sport->ipg_clk);2882		return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n");2883	}2884 2885	sport->baud_clk = NULL;2886	if (is_imx8qxp_lpuart(sport)) {2887		sport->baud_clk = devm_clk_get(&pdev->dev, "baud");2888		if (IS_ERR(sport->baud_clk)) {2889			ret = PTR_ERR(sport->baud_clk);2890			return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n");2891		}2892	}2893 2894	ret = of_alias_get_id(np, "serial");2895	if (ret < 0) {2896		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);2897		return ret;2898	}2899	if (ret >= ARRAY_SIZE(lpuart_ports)) {2900		dev_err(&pdev->dev, "serial%d out of range\n", ret);2901		return -EINVAL;2902	}2903	sport->port.line = ret;2904 2905	ret = lpuart_enable_clks(sport);2906	if (ret)2907		return ret;2908	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);2909 2910	lpuart_ports[sport->port.line] = sport;2911 2912	platform_set_drvdata(pdev, &sport->port);2913 2914	if (lpuart_is_32(sport)) {2915		lpuart_reg.cons = LPUART32_CONSOLE;2916		handler = lpuart32_int;2917	} else {2918		lpuart_reg.cons = LPUART_CONSOLE;2919		handler = lpuart_int;2920	}2921 2922	pm_runtime_use_autosuspend(&pdev->dev);2923	pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);2924	pm_runtime_set_active(&pdev->dev);2925	pm_runtime_enable(&pdev->dev);2926	pm_runtime_mark_last_busy(&pdev->dev);2927 2928	ret = lpuart_global_reset(sport);2929	if (ret)2930		goto failed_reset;2931 2932	ret = uart_get_rs485_mode(&sport->port);2933	if (ret)2934		goto failed_get_rs485;2935 2936	ret = uart_add_one_port(&lpuart_reg, &sport->port);2937	if (ret)2938		goto failed_attach_port;2939 2940	ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,2941				DRIVER_NAME, sport);2942	if (ret)2943		goto failed_irq_request;2944 2945	return 0;2946 2947failed_irq_request:2948	uart_remove_one_port(&lpuart_reg, &sport->port);2949failed_attach_port:2950failed_get_rs485:2951failed_reset:2952	pm_runtime_disable(&pdev->dev);2953	pm_runtime_set_suspended(&pdev->dev);2954	pm_runtime_dont_use_autosuspend(&pdev->dev);2955	lpuart_disable_clks(sport);2956	return ret;2957}2958 2959static void lpuart_remove(struct platform_device *pdev)2960{2961	struct lpuart_port *sport = platform_get_drvdata(pdev);2962 2963	uart_remove_one_port(&lpuart_reg, &sport->port);2964 2965	lpuart_disable_clks(sport);2966 2967	if (sport->dma_tx_chan)2968		dma_release_channel(sport->dma_tx_chan);2969 2970	if (sport->dma_rx_chan)2971		dma_release_channel(sport->dma_rx_chan);2972 2973	pm_runtime_disable(&pdev->dev);2974	pm_runtime_set_suspended(&pdev->dev);2975	pm_runtime_dont_use_autosuspend(&pdev->dev);2976}2977 2978static int lpuart_runtime_suspend(struct device *dev)2979{2980	struct platform_device *pdev = to_platform_device(dev);2981	struct lpuart_port *sport = platform_get_drvdata(pdev);2982 2983	lpuart_disable_clks(sport);2984 2985	return 0;2986};2987 2988static int lpuart_runtime_resume(struct device *dev)2989{2990	struct platform_device *pdev = to_platform_device(dev);2991	struct lpuart_port *sport = platform_get_drvdata(pdev);2992 2993	return lpuart_enable_clks(sport);2994};2995 2996static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)2997{2998	unsigned int val, baud;2999 3000	if (lpuart_is_32(sport)) {3001		val = lpuart32_read(&sport->port, UARTCTRL);3002		baud = lpuart32_read(&sport->port, UARTBAUD);3003		if (on) {3004			/* set rx_watermark to 0 in wakeup source mode */3005			lpuart32_write(&sport->port, 0, UARTWATER);3006			val |= UARTCTRL_RIE;3007			/* clear RXEDGIF flag before enable RXEDGIE interrupt */3008			lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);3009			baud |= UARTBAUD_RXEDGIE;3010		} else {3011			val &= ~UARTCTRL_RIE;3012			baud &= ~UARTBAUD_RXEDGIE;3013		}3014		lpuart32_write(&sport->port, val, UARTCTRL);3015		lpuart32_write(&sport->port, baud, UARTBAUD);3016	} else {3017		val = readb(sport->port.membase + UARTCR2);3018		if (on)3019			val |= UARTCR2_RIE;3020		else3021			val &= ~UARTCR2_RIE;3022		writeb(val, sport->port.membase + UARTCR2);3023	}3024}3025 3026static bool lpuart_uport_is_active(struct lpuart_port *sport)3027{3028	struct tty_port *port = &sport->port.state->port;3029	struct tty_struct *tty;3030	struct device *tty_dev;3031	int may_wake = 0;3032 3033	tty = tty_port_tty_get(port);3034	if (tty) {3035		tty_dev = tty->dev;3036		may_wake = tty_dev && device_may_wakeup(tty_dev);3037		tty_kref_put(tty);3038	}3039 3040	if ((tty_port_initialized(port) && may_wake) ||3041	    (!console_suspend_enabled && uart_console(&sport->port)))3042		return true;3043 3044	return false;3045}3046 3047static int lpuart_suspend_noirq(struct device *dev)3048{3049	struct lpuart_port *sport = dev_get_drvdata(dev);3050	bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));3051 3052	if (lpuart_uport_is_active(sport))3053		serial_lpuart_enable_wakeup(sport, !!irq_wake);3054 3055	pinctrl_pm_select_sleep_state(dev);3056 3057	return 0;3058}3059 3060static int lpuart_resume_noirq(struct device *dev)3061{3062	struct lpuart_port *sport = dev_get_drvdata(dev);3063	unsigned int val;3064 3065	pinctrl_pm_select_default_state(dev);3066 3067	if (lpuart_uport_is_active(sport)) {3068		serial_lpuart_enable_wakeup(sport, false);3069 3070		/* clear the wakeup flags */3071		if (lpuart_is_32(sport)) {3072			val = lpuart32_read(&sport->port, UARTSTAT);3073			lpuart32_write(&sport->port, val, UARTSTAT);3074		}3075	}3076 3077	return 0;3078}3079 3080static int lpuart_suspend(struct device *dev)3081{3082	struct lpuart_port *sport = dev_get_drvdata(dev);3083	unsigned long temp, flags;3084 3085	uart_suspend_port(&lpuart_reg, &sport->port);3086 3087	if (lpuart_uport_is_active(sport)) {3088		uart_port_lock_irqsave(&sport->port, &flags);3089		if (lpuart_is_32(sport)) {3090			/* disable Rx/Tx and interrupts */3091			temp = lpuart32_read(&sport->port, UARTCTRL);3092			temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);3093			lpuart32_write(&sport->port, temp, UARTCTRL);3094		} else {3095			/* disable Rx/Tx and interrupts */3096			temp = readb(sport->port.membase + UARTCR2);3097			temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);3098			writeb(temp, sport->port.membase + UARTCR2);3099		}3100		uart_port_unlock_irqrestore(&sport->port, flags);3101 3102		if (sport->lpuart_dma_rx_use) {3103			/*3104			 * EDMA driver during suspend will forcefully release any3105			 * non-idle DMA channels. If port wakeup is enabled or if port3106			 * is console port or 'no_console_suspend' is set the Rx DMA3107			 * cannot resume as expected, hence gracefully release the3108			 * Rx DMA path before suspend and start Rx DMA path on resume.3109			 */3110			lpuart_dma_rx_free(&sport->port);3111 3112			/* Disable Rx DMA to use UART port as wakeup source */3113			uart_port_lock_irqsave(&sport->port, &flags);3114			if (lpuart_is_32(sport)) {3115				temp = lpuart32_read(&sport->port, UARTBAUD);3116				lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,3117					       UARTBAUD);3118			} else {3119				writeb(readb(sport->port.membase + UARTCR5) &3120				       ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);3121			}3122			uart_port_unlock_irqrestore(&sport->port, flags);3123		}3124 3125		if (sport->lpuart_dma_tx_use) {3126			uart_port_lock_irqsave(&sport->port, &flags);3127			if (lpuart_is_32(sport)) {3128				temp = lpuart32_read(&sport->port, UARTBAUD);3129				temp &= ~UARTBAUD_TDMAE;3130				lpuart32_write(&sport->port, temp, UARTBAUD);3131			} else {3132				temp = readb(sport->port.membase + UARTCR5);3133				temp &= ~UARTCR5_TDMAS;3134				writeb(temp, sport->port.membase + UARTCR5);3135			}3136			uart_port_unlock_irqrestore(&sport->port, flags);3137			sport->dma_tx_in_progress = false;3138			dmaengine_terminate_sync(sport->dma_tx_chan);3139		}3140	} else if (pm_runtime_active(sport->port.dev)) {3141		lpuart_disable_clks(sport);3142		pm_runtime_disable(sport->port.dev);3143		pm_runtime_set_suspended(sport->port.dev);3144	}3145 3146	return 0;3147}3148 3149static void lpuart_console_fixup(struct lpuart_port *sport)3150{3151	struct tty_port *port = &sport->port.state->port;3152	struct uart_port *uport = &sport->port;3153	struct ktermios termios;3154 3155	/* i.MX7ULP enter VLLS mode that lpuart module power off and registers3156	 * all lost no matter the port is wakeup source.3157	 * For console port, console baud rate setting lost and print messy3158	 * log when enable the console port as wakeup source. To avoid the3159	 * issue happen, user should not enable uart port as wakeup source3160	 * in VLLS mode, or restore console setting here.3161	 */3162	if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&3163	    console_suspend_enabled && uart_console(&sport->port)) {3164 3165		mutex_lock(&port->mutex);3166		memset(&termios, 0, sizeof(struct ktermios));3167		termios.c_cflag = uport->cons->cflag;3168		if (port->tty && termios.c_cflag == 0)3169			termios = port->tty->termios;3170		uport->ops->set_termios(uport, &termios, NULL);3171		mutex_unlock(&port->mutex);3172	}3173}3174 3175static int lpuart_resume(struct device *dev)3176{3177	struct lpuart_port *sport = dev_get_drvdata(dev);3178	int ret;3179 3180	if (lpuart_uport_is_active(sport)) {3181		if (lpuart_is_32(sport))3182			lpuart32_hw_setup(sport);3183		else3184			lpuart_hw_setup(sport);3185	} else if (pm_runtime_active(sport->port.dev)) {3186		ret = lpuart_enable_clks(sport);3187		if (ret)3188			return ret;3189		pm_runtime_set_active(sport->port.dev);3190		pm_runtime_enable(sport->port.dev);3191	}3192 3193	lpuart_console_fixup(sport);3194	uart_resume_port(&lpuart_reg, &sport->port);3195 3196	return 0;3197}3198 3199static const struct dev_pm_ops lpuart_pm_ops = {3200	RUNTIME_PM_OPS(lpuart_runtime_suspend,3201			   lpuart_runtime_resume, NULL)3202	NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,3203				      lpuart_resume_noirq)3204	SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)3205};3206 3207static struct platform_driver lpuart_driver = {3208	.probe		= lpuart_probe,3209	.remove_new	= lpuart_remove,3210	.driver		= {3211		.name	= "fsl-lpuart",3212		.of_match_table = lpuart_dt_ids,3213		.pm	= pm_ptr(&lpuart_pm_ops),3214	},3215};3216 3217static int __init lpuart_serial_init(void)3218{3219	int ret = uart_register_driver(&lpuart_reg);3220 3221	if (ret)3222		return ret;3223 3224	ret = platform_driver_register(&lpuart_driver);3225	if (ret)3226		uart_unregister_driver(&lpuart_reg);3227 3228	return ret;3229}3230 3231static void __exit lpuart_serial_exit(void)3232{3233	platform_driver_unregister(&lpuart_driver);3234	uart_unregister_driver(&lpuart_reg);3235}3236 3237module_init(lpuart_serial_init);3238module_exit(lpuart_serial_exit);3239 3240MODULE_DESCRIPTION("Freescale lpuart serial port driver");3241MODULE_LICENSE("GPL v2");3242