1220 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Driver for Zilog serial chips found on SGI workstations and4 * servers. This driver could actually be made more generic.5 *6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the7 * old drivers/sgi/char/sgiserial.c code which itself is based of the original8 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over9 * directly from there but much has been rewritten. Credits therefore go out10 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell11 * for their work there.12 *13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)14 * Copyright (C) 2002 David S. Miller (davem@redhat.com)15 */16#include <linux/module.h>17#include <linux/kernel.h>18#include <linux/errno.h>19#include <linux/delay.h>20#include <linux/tty.h>21#include <linux/tty_flip.h>22#include <linux/major.h>23#include <linux/string.h>24#include <linux/ptrace.h>25#include <linux/ioport.h>26#include <linux/slab.h>27#include <linux/circ_buf.h>28#include <linux/serial.h>29#include <linux/sysrq.h>30#include <linux/console.h>31#include <linux/spinlock.h>32#include <linux/init.h>33 34#include <linux/io.h>35#include <asm/irq.h>36#include <asm/sgialib.h>37#include <asm/sgi/ioc.h>38#include <asm/sgi/hpc3.h>39#include <asm/sgi/ip22.h>40 41#include <linux/serial_core.h>42 43#include "ip22zilog.h"44 45/*46 * On IP22 we need to delay after register accesses but we do not need to47 * flush writes.48 */49#define ZSDELAY() udelay(5)50#define ZSDELAY_LONG() udelay(20)51#define ZS_WSYNC(channel) do { } while (0)52 53#define NUM_IP22ZILOG 154#define NUM_CHANNELS (NUM_IP22ZILOG * 2)55 56#define ZS_CLOCK 3672000 /* Zilog input clock rate. */57#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */58 59/*60 * We wrap our port structure around the generic uart_port.61 */62struct uart_ip22zilog_port {63 struct uart_port port;64 65 /* IRQ servicing chain. */66 struct uart_ip22zilog_port *next;67 68 /* Current values of Zilog write registers. */69 unsigned char curregs[NUM_ZSREGS];70 71 unsigned int flags;72#define IP22ZILOG_FLAG_IS_CONS 0x0000000473#define IP22ZILOG_FLAG_IS_KGDB 0x0000000874#define IP22ZILOG_FLAG_MODEM_STATUS 0x0000001075#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x0000002076#define IP22ZILOG_FLAG_REGS_HELD 0x0000004077#define IP22ZILOG_FLAG_TX_STOPPED 0x0000008078#define IP22ZILOG_FLAG_TX_ACTIVE 0x0000010079#define IP22ZILOG_FLAG_RESET_DONE 0x0000020080 81 unsigned int tty_break;82 83 unsigned char parity_mask;84 unsigned char prev_status;85};86 87#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))88#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))89#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \90 (UART_ZILOG(PORT)->curregs[REGNUM])91#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))93#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)94#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)95#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)96#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)97#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)98#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)99#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)100 101/* Reading and writing Zilog8530 registers. The delays are to make this102 * driver work on the IP22 which needs a settling delay after each chip103 * register access, other machines handle this in hardware via auxiliary104 * flip-flops which implement the settle time we do in software.105 *106 * The port lock must be held and local IRQs must be disabled107 * when {read,write}_zsreg is invoked.108 */109static unsigned char read_zsreg(struct zilog_channel *channel,110 unsigned char reg)111{112 unsigned char retval;113 114 writeb(reg, &channel->control);115 ZSDELAY();116 retval = readb(&channel->control);117 ZSDELAY();118 119 return retval;120}121 122static void write_zsreg(struct zilog_channel *channel,123 unsigned char reg, unsigned char value)124{125 writeb(reg, &channel->control);126 ZSDELAY();127 writeb(value, &channel->control);128 ZSDELAY();129}130 131static void ip22zilog_clear_fifo(struct zilog_channel *channel)132{133 int i;134 135 for (i = 0; i < 32; i++) {136 unsigned char regval;137 138 regval = readb(&channel->control);139 ZSDELAY();140 if (regval & Rx_CH_AV)141 break;142 143 regval = read_zsreg(channel, R1);144 readb(&channel->data);145 ZSDELAY();146 147 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {148 writeb(ERR_RES, &channel->control);149 ZSDELAY();150 ZS_WSYNC(channel);151 }152 }153}154 155/* This function must only be called when the TX is not busy. The UART156 * port lock must be held and local interrupts disabled.157 */158static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)159{160 int i;161 162 /* Let pending transmits finish. */163 for (i = 0; i < 1000; i++) {164 unsigned char stat = read_zsreg(channel, R1);165 if (stat & ALL_SNT)166 break;167 udelay(100);168 }169 170 writeb(ERR_RES, &channel->control);171 ZSDELAY();172 ZS_WSYNC(channel);173 174 ip22zilog_clear_fifo(channel);175 176 /* Disable all interrupts. */177 write_zsreg(channel, R1,178 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));179 180 /* Set parity, sync config, stop bits, and clock divisor. */181 write_zsreg(channel, R4, regs[R4]);182 183 /* Set misc. TX/RX control bits. */184 write_zsreg(channel, R10, regs[R10]);185 186 /* Set TX/RX controls sans the enable bits. */187 write_zsreg(channel, R3, regs[R3] & ~RxENAB);188 write_zsreg(channel, R5, regs[R5] & ~TxENAB);189 190 /* Synchronous mode config. */191 write_zsreg(channel, R6, regs[R6]);192 write_zsreg(channel, R7, regs[R7]);193 194 /* Don't mess with the interrupt vector (R2, unused by us) and195 * master interrupt control (R9). We make sure this is setup196 * properly at probe time then never touch it again.197 */198 199 /* Disable baud generator. */200 write_zsreg(channel, R14, regs[R14] & ~BRENAB);201 202 /* Clock mode control. */203 write_zsreg(channel, R11, regs[R11]);204 205 /* Lower and upper byte of baud rate generator divisor. */206 write_zsreg(channel, R12, regs[R12]);207 write_zsreg(channel, R13, regs[R13]);208 209 /* Now rewrite R14, with BRENAB (if set). */210 write_zsreg(channel, R14, regs[R14]);211 212 /* External status interrupt control. */213 write_zsreg(channel, R15, regs[R15]);214 215 /* Reset external status interrupts. */216 write_zsreg(channel, R0, RES_EXT_INT);217 write_zsreg(channel, R0, RES_EXT_INT);218 219 /* Rewrite R3/R5, this time without enables masked. */220 write_zsreg(channel, R3, regs[R3]);221 write_zsreg(channel, R5, regs[R5]);222 223 /* Rewrite R1, this time without IRQ enabled masked. */224 write_zsreg(channel, R1, regs[R1]);225}226 227/* Reprogram the Zilog channel HW registers with the copies found in the228 * software state struct. If the transmitter is busy, we defer this update229 * until the next TX complete interrupt. Else, we do it right now.230 *231 * The UART port lock must be held and local interrupts disabled.232 */233static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,234 struct zilog_channel *channel)235{236 if (!ZS_REGS_HELD(up)) {237 if (ZS_TX_ACTIVE(up)) {238 up->flags |= IP22ZILOG_FLAG_REGS_HELD;239 } else {240 __load_zsregs(channel, up->curregs);241 }242 }243}244 245#define Rx_BRK 0x0100 /* BREAK event software flag. */246#define Rx_SYS 0x0200 /* SysRq event software flag. */247 248static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,249 struct zilog_channel *channel)250{251 unsigned int r1;252 u8 ch, flag;253 bool push = up->port.state != NULL;254 255 for (;;) {256 ch = readb(&channel->control);257 ZSDELAY();258 if (!(ch & Rx_CH_AV))259 break;260 261 r1 = read_zsreg(channel, R1);262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {263 writeb(ERR_RES, &channel->control);264 ZSDELAY();265 ZS_WSYNC(channel);266 }267 268 ch = readb(&channel->data);269 ZSDELAY();270 271 ch &= up->parity_mask;272 273 /* Handle the null char got when BREAK is removed. */274 if (!ch)275 r1 |= up->tty_break;276 277 /* A real serial line, record the character and status. */278 flag = TTY_NORMAL;279 up->port.icount.rx++;280 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {281 up->tty_break = 0;282 283 if (r1 & (Rx_SYS | Rx_BRK)) {284 up->port.icount.brk++;285 if (r1 & Rx_SYS)286 continue;287 r1 &= ~(PAR_ERR | CRC_ERR);288 }289 else if (r1 & PAR_ERR)290 up->port.icount.parity++;291 else if (r1 & CRC_ERR)292 up->port.icount.frame++;293 if (r1 & Rx_OVR)294 up->port.icount.overrun++;295 r1 &= up->port.read_status_mask;296 if (r1 & Rx_BRK)297 flag = TTY_BREAK;298 else if (r1 & PAR_ERR)299 flag = TTY_PARITY;300 else if (r1 & CRC_ERR)301 flag = TTY_FRAME;302 }303 304 if (uart_handle_sysrq_char(&up->port, ch))305 continue;306 307 if (push)308 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);309 }310 return push;311}312 313static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,314 struct zilog_channel *channel)315{316 unsigned char status;317 318 status = readb(&channel->control);319 ZSDELAY();320 321 writeb(RES_EXT_INT, &channel->control);322 ZSDELAY();323 ZS_WSYNC(channel);324 325 if (up->curregs[R15] & BRKIE) {326 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {327 if (uart_handle_break(&up->port))328 up->tty_break = Rx_SYS;329 else330 up->tty_break = Rx_BRK;331 }332 }333 334 if (ZS_WANTS_MODEM_STATUS(up)) {335 if (status & SYNC)336 up->port.icount.dsr++;337 338 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.339 * But it does not tell us which bit has changed, we have to keep340 * track of this ourselves.341 */342 if ((status ^ up->prev_status) ^ DCD)343 uart_handle_dcd_change(&up->port,344 (status & DCD));345 if ((status ^ up->prev_status) ^ CTS)346 uart_handle_cts_change(&up->port,347 (status & CTS));348 349 wake_up_interruptible(&up->port.state->port.delta_msr_wait);350 }351 352 up->prev_status = status;353}354 355static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,356 struct zilog_channel *channel)357{358 struct tty_port *tport;359 unsigned char c;360 361 if (ZS_IS_CONS(up)) {362 unsigned char status = readb(&channel->control);363 ZSDELAY();364 365 /* TX still busy? Just wait for the next TX done interrupt.366 *367 * It can occur because of how we do serial console writes. It would368 * be nice to transmit console writes just like we normally would for369 * a TTY line. (ie. buffered and TX interrupt driven). That is not370 * easy because console writes cannot sleep. One solution might be371 * to poll on enough port->xmit space becoming free. -DaveM372 */373 if (!(status & Tx_BUF_EMP))374 return;375 }376 377 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;378 379 if (ZS_REGS_HELD(up)) {380 __load_zsregs(channel, up->curregs);381 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;382 }383 384 if (ZS_TX_STOPPED(up)) {385 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;386 goto ack_tx_int;387 }388 389 if (up->port.x_char) {390 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;391 writeb(up->port.x_char, &channel->data);392 ZSDELAY();393 ZS_WSYNC(channel);394 395 up->port.icount.tx++;396 up->port.x_char = 0;397 return;398 }399 400 if (up->port.state == NULL)401 goto ack_tx_int;402 tport = &up->port.state->port;403 if (uart_tx_stopped(&up->port))404 goto ack_tx_int;405 if (!uart_fifo_get(&up->port, &c))406 goto ack_tx_int;407 408 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;409 writeb(c, &channel->data);410 ZSDELAY();411 ZS_WSYNC(channel);412 413 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)414 uart_write_wakeup(&up->port);415 416 return;417 418ack_tx_int:419 writeb(RES_Tx_P, &channel->control);420 ZSDELAY();421 ZS_WSYNC(channel);422}423 424static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)425{426 struct uart_ip22zilog_port *up = dev_id;427 428 while (up) {429 struct zilog_channel *channel430 = ZILOG_CHANNEL_FROM_PORT(&up->port);431 unsigned char r3;432 bool push = false;433 434 uart_port_lock(&up->port);435 r3 = read_zsreg(channel, R3);436 437 /* Channel A */438 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {439 writeb(RES_H_IUS, &channel->control);440 ZSDELAY();441 ZS_WSYNC(channel);442 443 if (r3 & CHARxIP)444 push = ip22zilog_receive_chars(up, channel);445 if (r3 & CHAEXT)446 ip22zilog_status_handle(up, channel);447 if (r3 & CHATxIP)448 ip22zilog_transmit_chars(up, channel);449 }450 uart_port_unlock(&up->port);451 452 if (push)453 tty_flip_buffer_push(&up->port.state->port);454 455 /* Channel B */456 up = up->next;457 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);458 push = false;459 460 uart_port_lock(&up->port);461 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {462 writeb(RES_H_IUS, &channel->control);463 ZSDELAY();464 ZS_WSYNC(channel);465 466 if (r3 & CHBRxIP)467 push = ip22zilog_receive_chars(up, channel);468 if (r3 & CHBEXT)469 ip22zilog_status_handle(up, channel);470 if (r3 & CHBTxIP)471 ip22zilog_transmit_chars(up, channel);472 }473 uart_port_unlock(&up->port);474 475 if (push)476 tty_flip_buffer_push(&up->port.state->port);477 478 up = up->next;479 }480 481 return IRQ_HANDLED;482}483 484/* A convenient way to quickly get R0 status. The caller must _not_ hold the485 * port lock, it is acquired here.486 */487static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)488{489 struct zilog_channel *channel;490 unsigned char status;491 492 channel = ZILOG_CHANNEL_FROM_PORT(port);493 status = readb(&channel->control);494 ZSDELAY();495 496 return status;497}498 499/* The port lock is not held. */500static unsigned int ip22zilog_tx_empty(struct uart_port *port)501{502 unsigned long flags;503 unsigned char status;504 unsigned int ret;505 506 uart_port_lock_irqsave(port, &flags);507 508 status = ip22zilog_read_channel_status(port);509 510 uart_port_unlock_irqrestore(port, flags);511 512 if (status & Tx_BUF_EMP)513 ret = TIOCSER_TEMT;514 else515 ret = 0;516 517 return ret;518}519 520/* The port lock is held and interrupts are disabled. */521static unsigned int ip22zilog_get_mctrl(struct uart_port *port)522{523 unsigned char status;524 unsigned int ret;525 526 status = ip22zilog_read_channel_status(port);527 528 ret = 0;529 if (status & DCD)530 ret |= TIOCM_CAR;531 if (status & SYNC)532 ret |= TIOCM_DSR;533 if (status & CTS)534 ret |= TIOCM_CTS;535 536 return ret;537}538 539/* The port lock is held and interrupts are disabled. */540static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)541{542 struct uart_ip22zilog_port *up =543 container_of(port, struct uart_ip22zilog_port, port);544 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);545 unsigned char set_bits, clear_bits;546 547 set_bits = clear_bits = 0;548 549 if (mctrl & TIOCM_RTS)550 set_bits |= RTS;551 else552 clear_bits |= RTS;553 if (mctrl & TIOCM_DTR)554 set_bits |= DTR;555 else556 clear_bits |= DTR;557 558 /* NOTE: Not subject to 'transmitter active' rule. */559 up->curregs[R5] |= set_bits;560 up->curregs[R5] &= ~clear_bits;561 write_zsreg(channel, R5, up->curregs[R5]);562}563 564/* The port lock is held and interrupts are disabled. */565static void ip22zilog_stop_tx(struct uart_port *port)566{567 struct uart_ip22zilog_port *up =568 container_of(port, struct uart_ip22zilog_port, port);569 570 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;571}572 573/* The port lock is held and interrupts are disabled. */574static void ip22zilog_start_tx(struct uart_port *port)575{576 struct uart_ip22zilog_port *up =577 container_of(port, struct uart_ip22zilog_port, port);578 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);579 unsigned char status;580 581 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;582 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;583 584 status = readb(&channel->control);585 ZSDELAY();586 587 /* TX busy? Just wait for the TX done interrupt. */588 if (!(status & Tx_BUF_EMP))589 return;590 591 /* Send the first character to jump-start the TX done592 * IRQ sending engine.593 */594 if (port->x_char) {595 writeb(port->x_char, &channel->data);596 ZSDELAY();597 ZS_WSYNC(channel);598 599 port->icount.tx++;600 port->x_char = 0;601 } else {602 struct tty_port *tport = &port->state->port;603 unsigned char c;604 605 if (!uart_fifo_get(port, &c))606 return;607 writeb(c, &channel->data);608 ZSDELAY();609 ZS_WSYNC(channel);610 611 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)612 uart_write_wakeup(&up->port);613 }614}615 616/* The port lock is held and interrupts are disabled. */617static void ip22zilog_stop_rx(struct uart_port *port)618{619 struct uart_ip22zilog_port *up = UART_ZILOG(port);620 struct zilog_channel *channel;621 622 if (ZS_IS_CONS(up))623 return;624 625 channel = ZILOG_CHANNEL_FROM_PORT(port);626 627 /* Disable all RX interrupts. */628 up->curregs[R1] &= ~RxINT_MASK;629 ip22zilog_maybe_update_regs(up, channel);630}631 632/* The port lock is held. */633static void ip22zilog_enable_ms(struct uart_port *port)634{635 struct uart_ip22zilog_port *up =636 container_of(port, struct uart_ip22zilog_port, port);637 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);638 unsigned char new_reg;639 640 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);641 if (new_reg != up->curregs[R15]) {642 up->curregs[R15] = new_reg;643 644 /* NOTE: Not subject to 'transmitter active' rule. */645 write_zsreg(channel, R15, up->curregs[R15]);646 }647}648 649/* The port lock is not held. */650static void ip22zilog_break_ctl(struct uart_port *port, int break_state)651{652 struct uart_ip22zilog_port *up =653 container_of(port, struct uart_ip22zilog_port, port);654 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);655 unsigned char set_bits, clear_bits, new_reg;656 unsigned long flags;657 658 set_bits = clear_bits = 0;659 660 if (break_state)661 set_bits |= SND_BRK;662 else663 clear_bits |= SND_BRK;664 665 uart_port_lock_irqsave(port, &flags);666 667 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;668 if (new_reg != up->curregs[R5]) {669 up->curregs[R5] = new_reg;670 671 /* NOTE: Not subject to 'transmitter active' rule. */672 write_zsreg(channel, R5, up->curregs[R5]);673 }674 675 uart_port_unlock_irqrestore(port, flags);676}677 678static void __ip22zilog_reset(struct uart_ip22zilog_port *up)679{680 struct zilog_channel *channel;681 int i;682 683 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)684 return;685 686 /* Let pending transmits finish. */687 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);688 for (i = 0; i < 1000; i++) {689 unsigned char stat = read_zsreg(channel, R1);690 if (stat & ALL_SNT)691 break;692 udelay(100);693 }694 695 if (!ZS_IS_CHANNEL_A(up)) {696 up++;697 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);698 }699 write_zsreg(channel, R9, FHWRES);700 ZSDELAY_LONG();701 (void) read_zsreg(channel, R0);702 703 up->flags |= IP22ZILOG_FLAG_RESET_DONE;704 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;705}706 707static void __ip22zilog_startup(struct uart_ip22zilog_port *up)708{709 struct zilog_channel *channel;710 711 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);712 713 __ip22zilog_reset(up);714 715 __load_zsregs(channel, up->curregs);716 /* set master interrupt enable */717 write_zsreg(channel, R9, up->curregs[R9]);718 up->prev_status = readb(&channel->control);719 720 /* Enable receiver and transmitter. */721 up->curregs[R3] |= RxENAB;722 up->curregs[R5] |= TxENAB;723 724 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;725 ip22zilog_maybe_update_regs(up, channel);726}727 728static int ip22zilog_startup(struct uart_port *port)729{730 struct uart_ip22zilog_port *up = UART_ZILOG(port);731 unsigned long flags;732 733 if (ZS_IS_CONS(up))734 return 0;735 736 uart_port_lock_irqsave(port, &flags);737 __ip22zilog_startup(up);738 uart_port_unlock_irqrestore(port, flags);739 return 0;740}741 742/*743 * The test for ZS_IS_CONS is explained by the following e-mail:744 *****745 * From: Russell King <rmk@arm.linux.org.uk>746 * Date: Sun, 8 Dec 2002 10:18:38 +0000747 *748 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:749 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,750 * > and I noticed that something is not right with reference751 * > counting in this case. It seems that when the console752 * > is open by kernel initially, this is not accounted753 * > as an open, and uart_startup is not called.754 *755 * That is correct. We are unable to call uart_startup when the serial756 * console is initialised because it may need to allocate memory (as757 * request_irq does) and the memory allocators may not have been758 * initialised.759 *760 * 1. initialise the port into a state where it can send characters in the761 * console write method.762 *763 * 2. don't do the actual hardware shutdown in your shutdown() method (but764 * do the normal software shutdown - ie, free irqs etc)765 *****766 */767static void ip22zilog_shutdown(struct uart_port *port)768{769 struct uart_ip22zilog_port *up = UART_ZILOG(port);770 struct zilog_channel *channel;771 unsigned long flags;772 773 if (ZS_IS_CONS(up))774 return;775 776 uart_port_lock_irqsave(port, &flags);777 778 channel = ZILOG_CHANNEL_FROM_PORT(port);779 780 /* Disable receiver and transmitter. */781 up->curregs[R3] &= ~RxENAB;782 up->curregs[R5] &= ~TxENAB;783 784 /* Disable all interrupts and BRK assertion. */785 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);786 up->curregs[R5] &= ~SND_BRK;787 ip22zilog_maybe_update_regs(up, channel);788 789 uart_port_unlock_irqrestore(port, flags);790}791 792/* Shared by TTY driver and serial console setup. The port lock is held793 * and local interrupts are disabled.794 */795static void796ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,797 unsigned int iflag, int brg)798{799 800 up->curregs[R10] = NRZ;801 up->curregs[R11] = TCBR | RCBR;802 803 /* Program BAUD and clock source. */804 up->curregs[R4] &= ~XCLK_MASK;805 up->curregs[R4] |= X16CLK;806 up->curregs[R12] = brg & 0xff;807 up->curregs[R13] = (brg >> 8) & 0xff;808 up->curregs[R14] = BRENAB;809 810 /* Character size, stop bits, and parity. */811 up->curregs[3] &= ~RxN_MASK;812 up->curregs[5] &= ~TxN_MASK;813 switch (cflag & CSIZE) {814 case CS5:815 up->curregs[3] |= Rx5;816 up->curregs[5] |= Tx5;817 up->parity_mask = 0x1f;818 break;819 case CS6:820 up->curregs[3] |= Rx6;821 up->curregs[5] |= Tx6;822 up->parity_mask = 0x3f;823 break;824 case CS7:825 up->curregs[3] |= Rx7;826 up->curregs[5] |= Tx7;827 up->parity_mask = 0x7f;828 break;829 case CS8:830 default:831 up->curregs[3] |= Rx8;832 up->curregs[5] |= Tx8;833 up->parity_mask = 0xff;834 break;835 }836 up->curregs[4] &= ~0x0c;837 if (cflag & CSTOPB)838 up->curregs[4] |= SB2;839 else840 up->curregs[4] |= SB1;841 if (cflag & PARENB)842 up->curregs[4] |= PAR_ENAB;843 else844 up->curregs[4] &= ~PAR_ENAB;845 if (!(cflag & PARODD))846 up->curregs[4] |= PAR_EVEN;847 else848 up->curregs[4] &= ~PAR_EVEN;849 850 up->port.read_status_mask = Rx_OVR;851 if (iflag & INPCK)852 up->port.read_status_mask |= CRC_ERR | PAR_ERR;853 if (iflag & (IGNBRK | BRKINT | PARMRK))854 up->port.read_status_mask |= BRK_ABRT;855 856 up->port.ignore_status_mask = 0;857 if (iflag & IGNPAR)858 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;859 if (iflag & IGNBRK) {860 up->port.ignore_status_mask |= BRK_ABRT;861 if (iflag & IGNPAR)862 up->port.ignore_status_mask |= Rx_OVR;863 }864 865 if ((cflag & CREAD) == 0)866 up->port.ignore_status_mask = 0xff;867}868 869/* The port lock is not held. */870static void871ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,872 const struct ktermios *old)873{874 struct uart_ip22zilog_port *up =875 container_of(port, struct uart_ip22zilog_port, port);876 unsigned long flags;877 int baud, brg;878 879 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);880 881 uart_port_lock_irqsave(&up->port, &flags);882 883 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);884 885 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);886 887 if (UART_ENABLE_MS(&up->port, termios->c_cflag))888 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;889 else890 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;891 892 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));893 uart_update_timeout(port, termios->c_cflag, baud);894 895 uart_port_unlock_irqrestore(&up->port, flags);896}897 898static const char *ip22zilog_type(struct uart_port *port)899{900 return "IP22-Zilog";901}902 903/* We do not request/release mappings of the registers here, this904 * happens at early serial probe time.905 */906static void ip22zilog_release_port(struct uart_port *port)907{908}909 910static int ip22zilog_request_port(struct uart_port *port)911{912 return 0;913}914 915/* These do not need to do anything interesting either. */916static void ip22zilog_config_port(struct uart_port *port, int flags)917{918}919 920/* We do not support letting the user mess with the divisor, IRQ, etc. */921static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)922{923 return -EINVAL;924}925 926static const struct uart_ops ip22zilog_pops = {927 .tx_empty = ip22zilog_tx_empty,928 .set_mctrl = ip22zilog_set_mctrl,929 .get_mctrl = ip22zilog_get_mctrl,930 .stop_tx = ip22zilog_stop_tx,931 .start_tx = ip22zilog_start_tx,932 .stop_rx = ip22zilog_stop_rx,933 .enable_ms = ip22zilog_enable_ms,934 .break_ctl = ip22zilog_break_ctl,935 .startup = ip22zilog_startup,936 .shutdown = ip22zilog_shutdown,937 .set_termios = ip22zilog_set_termios,938 .type = ip22zilog_type,939 .release_port = ip22zilog_release_port,940 .request_port = ip22zilog_request_port,941 .config_port = ip22zilog_config_port,942 .verify_port = ip22zilog_verify_port,943};944 945static struct uart_ip22zilog_port *ip22zilog_port_table;946static struct zilog_layout **ip22zilog_chip_regs;947 948static struct uart_ip22zilog_port *ip22zilog_irq_chain;949static int zilog_irq = -1;950 951static void * __init alloc_one_table(unsigned long size)952{953 return kzalloc(size, GFP_KERNEL);954}955 956static void __init ip22zilog_alloc_tables(void)957{958 ip22zilog_port_table = (struct uart_ip22zilog_port *)959 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));960 ip22zilog_chip_regs = (struct zilog_layout **)961 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));962 963 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {964 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");965 }966}967 968/* Get the address of the registers for IP22-Zilog instance CHIP. */969static struct zilog_layout * __init get_zs(int chip)970{971 unsigned long base;972 973 if (chip < 0 || chip >= NUM_IP22ZILOG) {974 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);975 }976 977 /* Not probe-able, hard code it. */978 base = (unsigned long) &sgioc->uart;979 980 zilog_irq = SGI_SERIAL_IRQ;981 request_mem_region(base, 8, "IP22-Zilog");982 983 return (struct zilog_layout *) base;984}985 986#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */987 988#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE989static void ip22zilog_put_char(struct uart_port *port, unsigned char ch)990{991 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);992 int loops = ZS_PUT_CHAR_MAX_DELAY;993 994 /* This is a timed polling loop so do not switch the explicit995 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM996 */997 do {998 unsigned char val = readb(&channel->control);999 if (val & Tx_BUF_EMP) {1000 ZSDELAY();1001 break;1002 }1003 udelay(5);1004 } while (--loops);1005 1006 writeb(ch, &channel->data);1007 ZSDELAY();1008 ZS_WSYNC(channel);1009}1010 1011static void1012ip22zilog_console_write(struct console *con, const char *s, unsigned int count)1013{1014 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];1015 unsigned long flags;1016 1017 uart_port_lock_irqsave(&up->port, &flags);1018 uart_console_write(&up->port, s, count, ip22zilog_put_char);1019 udelay(2);1020 uart_port_unlock_irqrestore(&up->port, flags);1021}1022 1023static int __init ip22zilog_console_setup(struct console *con, char *options)1024{1025 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];1026 unsigned long flags;1027 int baud = 9600, bits = 8;1028 int parity = 'n';1029 int flow = 'n';1030 1031 up->flags |= IP22ZILOG_FLAG_IS_CONS;1032 1033 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);1034 1035 uart_port_lock_irqsave(&up->port, &flags);1036 1037 up->curregs[R15] |= BRKIE;1038 1039 __ip22zilog_startup(up);1040 1041 uart_port_unlock_irqrestore(&up->port, flags);1042 1043 if (options)1044 uart_parse_options(options, &baud, &parity, &bits, &flow);1045 return uart_set_options(&up->port, con, baud, parity, bits, flow);1046}1047 1048static struct uart_driver ip22zilog_reg;1049 1050static struct console ip22zilog_console = {1051 .name = "ttyS",1052 .write = ip22zilog_console_write,1053 .device = uart_console_device,1054 .setup = ip22zilog_console_setup,1055 .flags = CON_PRINTBUFFER,1056 .index = -1,1057 .data = &ip22zilog_reg,1058};1059#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */1060 1061static struct uart_driver ip22zilog_reg = {1062 .owner = THIS_MODULE,1063 .driver_name = "serial",1064 .dev_name = "ttyS",1065 .major = TTY_MAJOR,1066 .minor = 64,1067 .nr = NUM_CHANNELS,1068#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE1069 .cons = &ip22zilog_console,1070#endif1071};1072 1073static void __init ip22zilog_prepare(void)1074{1075 unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE);1076 struct uart_ip22zilog_port *up;1077 struct zilog_layout *rp;1078 int channel, chip;1079 1080 /*1081 * Temporary fix.1082 */1083 for (channel = 0; channel < NUM_CHANNELS; channel++)1084 spin_lock_init(&ip22zilog_port_table[channel].port.lock);1085 1086 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];1087 up = &ip22zilog_port_table[0];1088 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)1089 up[channel].next = &up[channel - 1];1090 up[channel].next = NULL;1091 1092 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {1093 if (!ip22zilog_chip_regs[chip]) {1094 ip22zilog_chip_regs[chip] = rp = get_zs(chip);1095 1096 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;1097 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;1098 1099 /* In theory mapbase is the physical address ... */1100 up[(chip * 2) + 0].port.mapbase =1101 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);1102 up[(chip * 2) + 1].port.mapbase =1103 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);1104 }1105 1106 /* Channel A */1107 up[(chip * 2) + 0].port.iotype = UPIO_MEM;1108 up[(chip * 2) + 0].port.irq = zilog_irq;1109 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;1110 up[(chip * 2) + 0].port.fifosize = 1;1111 up[(chip * 2) + 0].port.has_sysrq = sysrq_on;1112 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;1113 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;1114 up[(chip * 2) + 0].port.flags = 0;1115 up[(chip * 2) + 0].port.line = (chip * 2) + 0;1116 up[(chip * 2) + 0].flags = 0;1117 1118 /* Channel B */1119 up[(chip * 2) + 1].port.iotype = UPIO_MEM;1120 up[(chip * 2) + 1].port.irq = zilog_irq;1121 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;1122 up[(chip * 2) + 1].port.fifosize = 1;1123 up[(chip * 2) + 1].port.has_sysrq = sysrq_on;1124 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;1125 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;1126 up[(chip * 2) + 1].port.line = (chip * 2) + 1;1127 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;1128 }1129 1130 for (channel = 0; channel < NUM_CHANNELS; channel++) {1131 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];1132 int brg;1133 1134 /* Normal serial TTY. */1135 up->parity_mask = 0xff;1136 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;1137 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;1138 up->curregs[R3] = RxENAB | Rx8;1139 up->curregs[R5] = TxENAB | Tx8;1140 up->curregs[R9] = NV | MIE;1141 up->curregs[R10] = NRZ;1142 up->curregs[R11] = TCBR | RCBR;1143 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);1144 up->curregs[R12] = (brg & 0xff);1145 up->curregs[R13] = (brg >> 8) & 0xff;1146 up->curregs[R14] = BRENAB;1147 }1148}1149 1150static int __init ip22zilog_ports_init(void)1151{1152 int ret;1153 1154 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);1155 1156 ip22zilog_prepare();1157 1158 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,1159 "IP22-Zilog", ip22zilog_irq_chain)) {1160 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");1161 }1162 1163 ret = uart_register_driver(&ip22zilog_reg);1164 if (ret == 0) {1165 int i;1166 1167 for (i = 0; i < NUM_CHANNELS; i++) {1168 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];1169 1170 uart_add_one_port(&ip22zilog_reg, &up->port);1171 }1172 }1173 1174 return ret;1175}1176 1177static int __init ip22zilog_init(void)1178{1179 /* IP22 Zilog setup is hard coded, no probing to do. */1180 ip22zilog_alloc_tables();1181 ip22zilog_ports_init();1182 1183 return 0;1184}1185 1186static void __exit ip22zilog_exit(void)1187{1188 int i;1189 struct uart_ip22zilog_port *up;1190 1191 for (i = 0; i < NUM_CHANNELS; i++) {1192 up = &ip22zilog_port_table[i];1193 1194 uart_remove_one_port(&ip22zilog_reg, &up->port);1195 }1196 1197 /* Free IO mem */1198 up = &ip22zilog_port_table[0];1199 for (i = 0; i < NUM_IP22ZILOG; i++) {1200 if (up[(i * 2) + 0].port.mapbase) {1201 iounmap((void*)up[(i * 2) + 0].port.mapbase);1202 up[(i * 2) + 0].port.mapbase = 0;1203 }1204 if (up[(i * 2) + 1].port.mapbase) {1205 iounmap((void*)up[(i * 2) + 1].port.mapbase);1206 up[(i * 2) + 1].port.mapbase = 0;1207 }1208 }1209 1210 uart_unregister_driver(&ip22zilog_reg);1211}1212 1213module_init(ip22zilog_init);1214module_exit(ip22zilog_exit);1215 1216/* David wrote it but I'm to blame for the bugs ... */1217MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");1218MODULE_DESCRIPTION("SGI Zilog serial port driver");1219MODULE_LICENSE("GPL");1220