1744 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Application UART driver for:4 * Freescale STMP37XX/STMP378X5 * Alphascale ASM92606 *7 * Author: dmitry pervushin <dimka@embeddedalley.com>8 *9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>10 * Provide Alphascale ASM9260 support.11 * Copyright 2008-2010 Freescale Semiconductor, Inc.12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.13 */14 15#include <linux/kernel.h>16#include <linux/errno.h>17#include <linux/init.h>18#include <linux/console.h>19#include <linux/interrupt.h>20#include <linux/module.h>21#include <linux/slab.h>22#include <linux/wait.h>23#include <linux/tty.h>24#include <linux/tty_driver.h>25#include <linux/tty_flip.h>26#include <linux/serial.h>27#include <linux/serial_core.h>28#include <linux/platform_device.h>29#include <linux/device.h>30#include <linux/clk.h>31#include <linux/delay.h>32#include <linux/io.h>33#include <linux/of.h>34#include <linux/dma-mapping.h>35#include <linux/dmaengine.h>36 37#include <linux/gpio/consumer.h>38#include <linux/err.h>39#include <linux/irq.h>40#include "serial_mctrl_gpio.h"41 42#define MXS_AUART_PORTS 543#define MXS_AUART_FIFO_SIZE 1644 45#define SET_REG 0x446#define CLR_REG 0x847#define TOG_REG 0xc48 49#define AUART_CTRL0 0x0000000050#define AUART_CTRL1 0x0000001051#define AUART_CTRL2 0x0000002052#define AUART_LINECTRL 0x0000003053#define AUART_LINECTRL2 0x0000004054#define AUART_INTR 0x0000005055#define AUART_DATA 0x0000006056#define AUART_STAT 0x0000007057#define AUART_DEBUG 0x0000008058#define AUART_VERSION 0x0000009059#define AUART_AUTOBAUD 0x000000a060 61#define AUART_CTRL0_SFTRST (1 << 31)62#define AUART_CTRL0_CLKGATE (1 << 30)63#define AUART_CTRL0_RXTO_ENABLE (1 << 27)64#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)65#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)66 67#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)68 69#define AUART_CTRL2_DMAONERR (1 << 26)70#define AUART_CTRL2_TXDMAE (1 << 25)71#define AUART_CTRL2_RXDMAE (1 << 24)72 73#define AUART_CTRL2_CTSEN (1 << 15)74#define AUART_CTRL2_RTSEN (1 << 14)75#define AUART_CTRL2_RTS (1 << 11)76#define AUART_CTRL2_RXE (1 << 9)77#define AUART_CTRL2_TXE (1 << 8)78#define AUART_CTRL2_UARTEN (1 << 0)79 80#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc081#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec82#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 1683#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff000084#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)85#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 886#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f0087#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)88#define AUART_LINECTRL_SPS (1 << 7)89#define AUART_LINECTRL_WLEN_MASK 0x0000006090#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)91#define AUART_LINECTRL_FEN (1 << 4)92#define AUART_LINECTRL_STP2 (1 << 3)93#define AUART_LINECTRL_EPS (1 << 2)94#define AUART_LINECTRL_PEN (1 << 1)95#define AUART_LINECTRL_BRK (1 << 0)96 97#define AUART_INTR_RTIEN (1 << 22)98#define AUART_INTR_TXIEN (1 << 21)99#define AUART_INTR_RXIEN (1 << 20)100#define AUART_INTR_CTSMIEN (1 << 17)101#define AUART_INTR_RTIS (1 << 6)102#define AUART_INTR_TXIS (1 << 5)103#define AUART_INTR_RXIS (1 << 4)104#define AUART_INTR_CTSMIS (1 << 1)105 106#define AUART_STAT_BUSY (1 << 29)107#define AUART_STAT_CTS (1 << 28)108#define AUART_STAT_TXFE (1 << 27)109#define AUART_STAT_TXFF (1 << 25)110#define AUART_STAT_RXFE (1 << 24)111#define AUART_STAT_OERR (1 << 19)112#define AUART_STAT_BERR (1 << 18)113#define AUART_STAT_PERR (1 << 17)114#define AUART_STAT_FERR (1 << 16)115#define AUART_STAT_RXCOUNT_MASK 0xffff116 117/*118 * Start of Alphascale asm9260 defines119 * This list contains only differences of existing bits120 * between imx2x and asm9260121 */122#define ASM9260_HW_CTRL0 0x0000123/*124 * RW. Tell the UART to execute the RX DMA Command. The125 * UART will clear this bit at the end of receive execution.126 */127#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)128/* RW. 0 use FIFO for status register; 1 use DMA */129#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)130/*131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.132 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA133 * operation. If this bit is set to 1, a receive timeout will cause the receive134 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.135 */136#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)137/*138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before139 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX140 * input is idle, then the watchdog counter will decrement each bit-time. Note141 * 7-bit-time is added to the programmed value, so a value of zero will set142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also143 * note that the counter is reloaded at the end of each frame, so if the frame144 * is 10 bits long and the timeout counter value is zero, then timeout will145 * occur (when FIFO is not empty) even if the RX input is not idle. The default146 * value is 0x3 (31 bit-time).147 */148#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)149/* TIMEOUT = (100*7+1)*(1/BAUD) */150#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)151 152/* TX ctrl register */153#define ASM9260_HW_CTRL1 0x0010154/*155 * RW. Tell the UART to execute the TX DMA Command. The156 * UART will clear this bit at the end of transmit execution.157 */158#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)159 160#define ASM9260_HW_CTRL2 0x0020161/*162 * RW. Receive Interrupt FIFO Level Select.163 * The trigger points for the receive interrupt are as follows:164 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.165 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.166 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.167 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.168 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.169 */170#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)171#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)172/* RW. Same as RXIFLSEL */173#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)174#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)175/* RW. Set DTR. When this bit is 1, the output is 0. */176#define ASM9260_BM_CTRL2_DTR BIT(10)177/* RW. Loop Back Enable */178#define ASM9260_BM_CTRL2_LBE BIT(7)179#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)180 181#define ASM9260_HW_LINECTRL 0x0030182/*183 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the184 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,185 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this186 * bit is cleared stick parity is disabled.187 */188#define ASM9260_BM_LCTRL_SPS BIT(7)189/* RW. Word length */190#define ASM9260_BM_LCTRL_WLEN (3 << 5)191#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)192#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)193#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)194#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)195 196/*197 * Interrupt register.198 * contains the interrupt enables and the interrupt status bits199 */200#define ASM9260_HW_INTR 0x0040201/* Tx FIFO EMPTY Raw Interrupt enable */202#define ASM9260_BM_INTR_TFEIEN BIT(27)203/* Overrun Error Interrupt Enable. */204#define ASM9260_BM_INTR_OEIEN BIT(26)205/* Break Error Interrupt Enable. */206#define ASM9260_BM_INTR_BEIEN BIT(25)207/* Parity Error Interrupt Enable. */208#define ASM9260_BM_INTR_PEIEN BIT(24)209/* Framing Error Interrupt Enable. */210#define ASM9260_BM_INTR_FEIEN BIT(23)211 212/* nUARTDSR Modem Interrupt Enable. */213#define ASM9260_BM_INTR_DSRMIEN BIT(19)214/* nUARTDCD Modem Interrupt Enable. */215#define ASM9260_BM_INTR_DCDMIEN BIT(18)216/* nUARTRI Modem Interrupt Enable. */217#define ASM9260_BM_INTR_RIMIEN BIT(16)218/* Auto-Boud Timeout */219#define ASM9260_BM_INTR_ABTO BIT(13)220#define ASM9260_BM_INTR_ABEO BIT(12)221/* Tx FIFO EMPTY Raw Interrupt state */222#define ASM9260_BM_INTR_TFEIS BIT(11)223/* Overrun Error */224#define ASM9260_BM_INTR_OEIS BIT(10)225/* Break Error */226#define ASM9260_BM_INTR_BEIS BIT(9)227/* Parity Error */228#define ASM9260_BM_INTR_PEIS BIT(8)229/* Framing Error */230#define ASM9260_BM_INTR_FEIS BIT(7)231#define ASM9260_BM_INTR_DSRMIS BIT(3)232#define ASM9260_BM_INTR_DCDMIS BIT(2)233#define ASM9260_BM_INTR_RIMIS BIT(0)234 235/*236 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a237 * time. In PIO mode, only one character can be accessed at a time. The status238 * register contains the receive data flags and valid bits.239 */240#define ASM9260_HW_DATA 0x0050241 242#define ASM9260_HW_STAT 0x0060243/* RO. If 1, UARTAPP is present in this product. */244#define ASM9260_BM_STAT_PRESENT BIT(31)245/* RO. If 1, HISPEED is present in this product. */246#define ASM9260_BM_STAT_HISPEED BIT(30)247/* RO. Receive FIFO Full. */248#define ASM9260_BM_STAT_RXFULL BIT(26)249 250/* RO. The UART Debug Register contains the state of the DMA signals. */251#define ASM9260_HW_DEBUG 0x0070252/* DMA Command Run Status */253#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)254#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)255/* DMA Command End Status */256#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)257#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)258/* DMA Request Status */259#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)260#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)261 262#define ASM9260_HW_ILPR 0x0080263 264#define ASM9260_HW_RS485CTRL 0x0090265/*266 * RW. This bit reverses the polarity of the direction control signal on the RTS267 * (or DTR) pin.268 * If 0, The direction control pin will be driven to logic ‘0’ when the269 * transmitter has data to be sent. It will be driven to logic ‘1’ after the270 * last bit of data has been transmitted.271 */272#define ASM9260_BM_RS485CTRL_ONIV BIT(5)273/* RW. Enable Auto Direction Control. */274#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)275/*276 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.277 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.278 */279#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)280/* RW. Enable Auto Address Detect (AAD). */281#define ASM9260_BM_RS485CTRL_AADEN BIT(2)282/* RW. Disable receiver. */283#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)284/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */285#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)286 287#define ASM9260_HW_RS485ADRMATCH 0x00a0288/* Contains the address match value. */289#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)290 291#define ASM9260_HW_RS485DLY 0x00b0292/*293 * RW. Contains the direction control (RTS or DTR) delay value. This delay time294 * is in periods of the baud clock.295 */296#define ASM9260_BM_RS485DLY_MASK (0xff << 0)297 298#define ASM9260_HW_AUTOBAUD 0x00c0299/* WO. Auto-baud time-out interrupt clear bit. */300#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)301/* WO. End of auto-baud interrupt clear bit. */302#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)303/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */304#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)305/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */306#define ASM9260_BM_AUTOBAUD_MODE BIT(1)307/*308 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is309 * automatically cleared after auto-baud completion.310 */311#define ASM9260_BM_AUTOBAUD_START BIT(0)312 313#define ASM9260_HW_CTRL3 0x00d0314#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)315/*316 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on317 * pins 137 and 144.318 */319#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)320/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */321#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)322/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */323#define ASM9260_BM_CTRL3_MSBF BIT(2)324/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */325#define ASM9260_BM_CTRL3_BAUD8 BIT(1)326/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */327#define ASM9260_BM_CTRL3_9BIT BIT(0)328 329#define ASM9260_HW_ISO7816_CTRL 0x00e0330/* RW. Enable High Speed mode. */331#define ASM9260_BM_ISO7816CTRL_HS BIT(12)332/* Disable Successive Receive NACK */333#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)334#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)335/* Receive NACK Inhibit */336#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)337#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)338/* RW. 1 - ISO7816 mode; 0 - USART mode */339#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)340 341#define ASM9260_HW_ISO7816_ERRCNT 0x00f0342/* Parity error counter. Will be cleared after reading */343#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)344 345#define ASM9260_HW_ISO7816_STATUS 0x0100346/* Max number of Repetitions Reached */347#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)348 349/* End of Alphascale asm9260 defines */350 351static struct uart_driver auart_driver;352 353enum mxs_auart_type {354 IMX23_AUART,355 IMX28_AUART,356 ASM9260_AUART,357};358 359struct vendor_data {360 const u16 *reg_offset;361};362 363enum {364 REG_CTRL0,365 REG_CTRL1,366 REG_CTRL2,367 REG_LINECTRL,368 REG_LINECTRL2,369 REG_INTR,370 REG_DATA,371 REG_STAT,372 REG_DEBUG,373 REG_VERSION,374 REG_AUTOBAUD,375 376 /* The size of the array - must be last */377 REG_ARRAY_SIZE,378};379 380static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {381 [REG_CTRL0] = ASM9260_HW_CTRL0,382 [REG_CTRL1] = ASM9260_HW_CTRL1,383 [REG_CTRL2] = ASM9260_HW_CTRL2,384 [REG_LINECTRL] = ASM9260_HW_LINECTRL,385 [REG_INTR] = ASM9260_HW_INTR,386 [REG_DATA] = ASM9260_HW_DATA,387 [REG_STAT] = ASM9260_HW_STAT,388 [REG_DEBUG] = ASM9260_HW_DEBUG,389 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,390};391 392static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {393 [REG_CTRL0] = AUART_CTRL0,394 [REG_CTRL1] = AUART_CTRL1,395 [REG_CTRL2] = AUART_CTRL2,396 [REG_LINECTRL] = AUART_LINECTRL,397 [REG_LINECTRL2] = AUART_LINECTRL2,398 [REG_INTR] = AUART_INTR,399 [REG_DATA] = AUART_DATA,400 [REG_STAT] = AUART_STAT,401 [REG_DEBUG] = AUART_DEBUG,402 [REG_VERSION] = AUART_VERSION,403 [REG_AUTOBAUD] = AUART_AUTOBAUD,404};405 406static const struct vendor_data vendor_alphascale_asm9260 = {407 .reg_offset = mxs_asm9260_offsets,408};409 410static const struct vendor_data vendor_freescale_stmp37xx = {411 .reg_offset = mxs_stmp37xx_offsets,412};413 414struct mxs_auart_port {415 struct uart_port port;416 417#define MXS_AUART_DMA_ENABLED 0x2418#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */419#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */420#define MXS_AUART_RTSCTS 4 /* bit 4 */421 unsigned long flags;422 unsigned int mctrl_prev;423 enum mxs_auart_type devtype;424 const struct vendor_data *vendor;425 426 struct clk *clk;427 struct clk *clk_ahb;428 struct device *dev;429 430 /* for DMA */431 struct scatterlist tx_sgl;432 struct dma_chan *tx_dma_chan;433 void *tx_dma_buf;434 435 struct scatterlist rx_sgl;436 struct dma_chan *rx_dma_chan;437 void *rx_dma_buf;438 439 struct mctrl_gpios *gpios;440 int gpio_irq[UART_GPIO_MAX];441 bool ms_irq_enabled;442};443 444static const struct of_device_id mxs_auart_dt_ids[] = {445 {446 .compatible = "fsl,imx28-auart",447 .data = (const void *)IMX28_AUART448 }, {449 .compatible = "fsl,imx23-auart",450 .data = (const void *)IMX23_AUART451 }, {452 .compatible = "alphascale,asm9260-auart",453 .data = (const void *)ASM9260_AUART454 }, { /* sentinel */ }455};456MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);457 458static inline int is_imx28_auart(struct mxs_auart_port *s)459{460 return s->devtype == IMX28_AUART;461}462 463static inline int is_asm9260_auart(struct mxs_auart_port *s)464{465 return s->devtype == ASM9260_AUART;466}467 468static inline bool auart_dma_enabled(struct mxs_auart_port *s)469{470 return s->flags & MXS_AUART_DMA_ENABLED;471}472 473static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,474 unsigned int reg)475{476 return uap->vendor->reg_offset[reg];477}478 479static unsigned int mxs_read(const struct mxs_auart_port *uap,480 unsigned int reg)481{482 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);483 484 return readl_relaxed(addr);485}486 487static void mxs_write(unsigned int val, struct mxs_auart_port *uap,488 unsigned int reg)489{490 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);491 492 writel_relaxed(val, addr);493}494 495static void mxs_set(unsigned int val, struct mxs_auart_port *uap,496 unsigned int reg)497{498 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);499 500 writel_relaxed(val, addr + SET_REG);501}502 503static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,504 unsigned int reg)505{506 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);507 508 writel_relaxed(val, addr + CLR_REG);509}510 511static void mxs_auart_stop_tx(struct uart_port *u);512 513#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)514 515static void mxs_auart_tx_chars(struct mxs_auart_port *s);516 517static void dma_tx_callback(void *param)518{519 struct mxs_auart_port *s = param;520 struct tty_port *tport = &s->port.state->port;521 522 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);523 524 /* clear the bit used to serialize the DMA tx. */525 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);526 smp_mb__after_atomic();527 528 /* wake up the possible processes. */529 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)530 uart_write_wakeup(&s->port);531 532 mxs_auart_tx_chars(s);533}534 535static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)536{537 struct dma_async_tx_descriptor *desc;538 struct scatterlist *sgl = &s->tx_sgl;539 struct dma_chan *channel = s->tx_dma_chan;540 u32 pio;541 542 /* [1] : send PIO. Note, the first pio word is CTRL1. */543 pio = AUART_CTRL1_XFER_COUNT(size);544 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,545 1, DMA_TRANS_NONE, 0);546 if (!desc) {547 dev_err(s->dev, "step 1 error\n");548 return -EINVAL;549 }550 551 /* [2] : set DMA buffer. */552 sg_init_one(sgl, s->tx_dma_buf, size);553 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);554 desc = dmaengine_prep_slave_sg(channel, sgl,555 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);556 if (!desc) {557 dev_err(s->dev, "step 2 error\n");558 return -EINVAL;559 }560 561 /* [3] : submit the DMA */562 desc->callback = dma_tx_callback;563 desc->callback_param = s;564 dmaengine_submit(desc);565 dma_async_issue_pending(channel);566 return 0;567}568 569static void mxs_auart_tx_chars(struct mxs_auart_port *s)570{571 struct tty_port *tport = &s->port.state->port;572 bool pending;573 u8 ch;574 575 if (auart_dma_enabled(s)) {576 u32 i = 0;577 void *buffer = s->tx_dma_buf;578 579 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))580 return;581 582 if (uart_tx_stopped(&s->port))583 mxs_auart_stop_tx(&s->port);584 else585 i = kfifo_out(&tport->xmit_fifo, buffer,586 UART_XMIT_SIZE);587 588 if (i) {589 mxs_auart_dma_tx(s, i);590 } else {591 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);592 smp_mb__after_atomic();593 }594 return;595 }596 597 pending = uart_port_tx_flags(&s->port, ch, UART_TX_NOSTOP,598 !(mxs_read(s, REG_STAT) & AUART_STAT_TXFF),599 mxs_write(ch, s, REG_DATA));600 if (pending)601 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);602 else603 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);604 605 if (uart_tx_stopped(&s->port))606 mxs_auart_stop_tx(&s->port);607}608 609static void mxs_auart_rx_char(struct mxs_auart_port *s)610{611 u32 stat;612 u8 c, flag;613 614 c = mxs_read(s, REG_DATA);615 stat = mxs_read(s, REG_STAT);616 617 flag = TTY_NORMAL;618 s->port.icount.rx++;619 620 if (stat & AUART_STAT_BERR) {621 s->port.icount.brk++;622 if (uart_handle_break(&s->port))623 goto out;624 } else if (stat & AUART_STAT_PERR) {625 s->port.icount.parity++;626 } else if (stat & AUART_STAT_FERR) {627 s->port.icount.frame++;628 }629 630 /*631 * Mask off conditions which should be ingored.632 */633 stat &= s->port.read_status_mask;634 635 if (stat & AUART_STAT_BERR) {636 flag = TTY_BREAK;637 } else if (stat & AUART_STAT_PERR)638 flag = TTY_PARITY;639 else if (stat & AUART_STAT_FERR)640 flag = TTY_FRAME;641 642 if (stat & AUART_STAT_OERR)643 s->port.icount.overrun++;644 645 if (uart_handle_sysrq_char(&s->port, c))646 goto out;647 648 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);649out:650 mxs_write(stat, s, REG_STAT);651}652 653static void mxs_auart_rx_chars(struct mxs_auart_port *s)654{655 u32 stat = 0;656 657 for (;;) {658 stat = mxs_read(s, REG_STAT);659 if (stat & AUART_STAT_RXFE)660 break;661 mxs_auart_rx_char(s);662 }663 664 mxs_write(stat, s, REG_STAT);665 tty_flip_buffer_push(&s->port.state->port);666}667 668static int mxs_auart_request_port(struct uart_port *u)669{670 return 0;671}672 673static int mxs_auart_verify_port(struct uart_port *u,674 struct serial_struct *ser)675{676 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)677 return -EINVAL;678 return 0;679}680 681static void mxs_auart_config_port(struct uart_port *u, int flags)682{683}684 685static const char *mxs_auart_type(struct uart_port *u)686{687 struct mxs_auart_port *s = to_auart_port(u);688 689 return dev_name(s->dev);690}691 692static void mxs_auart_release_port(struct uart_port *u)693{694}695 696static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)697{698 struct mxs_auart_port *s = to_auart_port(u);699 700 u32 ctrl = mxs_read(s, REG_CTRL2);701 702 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);703 if (mctrl & TIOCM_RTS) {704 if (uart_cts_enabled(u))705 ctrl |= AUART_CTRL2_RTSEN;706 else707 ctrl |= AUART_CTRL2_RTS;708 }709 710 mxs_write(ctrl, s, REG_CTRL2);711 712 mctrl_gpio_set(s->gpios, mctrl);713}714 715#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)716static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)717{718 u32 mctrl_diff;719 720 mctrl_diff = mctrl ^ s->mctrl_prev;721 s->mctrl_prev = mctrl;722 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&723 s->port.state != NULL) {724 if (mctrl_diff & TIOCM_RI)725 s->port.icount.rng++;726 if (mctrl_diff & TIOCM_DSR)727 s->port.icount.dsr++;728 if (mctrl_diff & TIOCM_CD)729 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);730 if (mctrl_diff & TIOCM_CTS)731 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);732 733 wake_up_interruptible(&s->port.state->port.delta_msr_wait);734 }735 return mctrl;736}737 738static u32 mxs_auart_get_mctrl(struct uart_port *u)739{740 struct mxs_auart_port *s = to_auart_port(u);741 u32 stat = mxs_read(s, REG_STAT);742 u32 mctrl = 0;743 744 if (stat & AUART_STAT_CTS)745 mctrl |= TIOCM_CTS;746 747 return mctrl_gpio_get(s->gpios, &mctrl);748}749 750/*751 * Enable modem status interrupts752 */753static void mxs_auart_enable_ms(struct uart_port *port)754{755 struct mxs_auart_port *s = to_auart_port(port);756 757 /*758 * Interrupt should not be enabled twice759 */760 if (s->ms_irq_enabled)761 return;762 763 s->ms_irq_enabled = true;764 765 if (s->gpio_irq[UART_GPIO_CTS] >= 0)766 enable_irq(s->gpio_irq[UART_GPIO_CTS]);767 /* TODO: enable AUART_INTR_CTSMIEN otherwise */768 769 if (s->gpio_irq[UART_GPIO_DSR] >= 0)770 enable_irq(s->gpio_irq[UART_GPIO_DSR]);771 772 if (s->gpio_irq[UART_GPIO_RI] >= 0)773 enable_irq(s->gpio_irq[UART_GPIO_RI]);774 775 if (s->gpio_irq[UART_GPIO_DCD] >= 0)776 enable_irq(s->gpio_irq[UART_GPIO_DCD]);777}778 779/*780 * Disable modem status interrupts781 */782static void mxs_auart_disable_ms(struct uart_port *port)783{784 struct mxs_auart_port *s = to_auart_port(port);785 786 /*787 * Interrupt should not be disabled twice788 */789 if (!s->ms_irq_enabled)790 return;791 792 s->ms_irq_enabled = false;793 794 if (s->gpio_irq[UART_GPIO_CTS] >= 0)795 disable_irq(s->gpio_irq[UART_GPIO_CTS]);796 /* TODO: disable AUART_INTR_CTSMIEN otherwise */797 798 if (s->gpio_irq[UART_GPIO_DSR] >= 0)799 disable_irq(s->gpio_irq[UART_GPIO_DSR]);800 801 if (s->gpio_irq[UART_GPIO_RI] >= 0)802 disable_irq(s->gpio_irq[UART_GPIO_RI]);803 804 if (s->gpio_irq[UART_GPIO_DCD] >= 0)805 disable_irq(s->gpio_irq[UART_GPIO_DCD]);806}807 808static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);809static void dma_rx_callback(void *arg)810{811 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;812 struct tty_port *port = &s->port.state->port;813 int count;814 u32 stat;815 816 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);817 818 stat = mxs_read(s, REG_STAT);819 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |820 AUART_STAT_PERR | AUART_STAT_FERR);821 822 count = stat & AUART_STAT_RXCOUNT_MASK;823 tty_insert_flip_string(port, s->rx_dma_buf, count);824 825 mxs_write(stat, s, REG_STAT);826 tty_flip_buffer_push(port);827 828 /* start the next DMA for RX. */829 mxs_auart_dma_prep_rx(s);830}831 832static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)833{834 struct dma_async_tx_descriptor *desc;835 struct scatterlist *sgl = &s->rx_sgl;836 struct dma_chan *channel = s->rx_dma_chan;837 u32 pio[1];838 839 /* [1] : send PIO */840 pio[0] = AUART_CTRL0_RXTO_ENABLE841 | AUART_CTRL0_RXTIMEOUT(0x80)842 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);843 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,844 1, DMA_TRANS_NONE, 0);845 if (!desc) {846 dev_err(s->dev, "step 1 error\n");847 return -EINVAL;848 }849 850 /* [2] : send DMA request */851 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);852 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);853 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,854 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);855 if (!desc) {856 dev_err(s->dev, "step 2 error\n");857 return -1;858 }859 860 /* [3] : submit the DMA, but do not issue it. */861 desc->callback = dma_rx_callback;862 desc->callback_param = s;863 dmaengine_submit(desc);864 dma_async_issue_pending(channel);865 return 0;866}867 868static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)869{870 if (s->tx_dma_chan) {871 dma_release_channel(s->tx_dma_chan);872 s->tx_dma_chan = NULL;873 }874 if (s->rx_dma_chan) {875 dma_release_channel(s->rx_dma_chan);876 s->rx_dma_chan = NULL;877 }878 879 kfree(s->tx_dma_buf);880 kfree(s->rx_dma_buf);881 s->tx_dma_buf = NULL;882 s->rx_dma_buf = NULL;883}884 885static void mxs_auart_dma_exit(struct mxs_auart_port *s)886{887 888 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,889 s, REG_CTRL2);890 891 mxs_auart_dma_exit_channel(s);892 s->flags &= ~MXS_AUART_DMA_ENABLED;893 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);894 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);895}896 897static int mxs_auart_dma_init(struct mxs_auart_port *s)898{899 struct dma_chan *chan;900 901 if (auart_dma_enabled(s))902 return 0;903 904 /* init for RX */905 chan = dma_request_chan(s->dev, "rx");906 if (IS_ERR(chan))907 goto err_out;908 s->rx_dma_chan = chan;909 910 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);911 if (!s->rx_dma_buf)912 goto err_out;913 914 /* init for TX */915 chan = dma_request_chan(s->dev, "tx");916 if (IS_ERR(chan))917 goto err_out;918 s->tx_dma_chan = chan;919 920 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);921 if (!s->tx_dma_buf)922 goto err_out;923 924 /* set the flags */925 s->flags |= MXS_AUART_DMA_ENABLED;926 dev_dbg(s->dev, "enabled the DMA support.");927 928 /* The DMA buffer is now the FIFO the TTY subsystem can use */929 s->port.fifosize = UART_XMIT_SIZE;930 931 return 0;932 933err_out:934 mxs_auart_dma_exit_channel(s);935 return -EINVAL;936 937}938 939#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)940#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)941static void mxs_auart_settermios(struct uart_port *u,942 struct ktermios *termios,943 const struct ktermios *old)944{945 struct mxs_auart_port *s = to_auart_port(u);946 u32 ctrl, ctrl2, div;947 unsigned int cflag, baud, baud_min, baud_max;948 949 cflag = termios->c_cflag;950 951 ctrl = AUART_LINECTRL_FEN;952 ctrl2 = mxs_read(s, REG_CTRL2);953 954 ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag));955 956 /* parity */957 if (cflag & PARENB) {958 ctrl |= AUART_LINECTRL_PEN;959 if ((cflag & PARODD) == 0)960 ctrl |= AUART_LINECTRL_EPS;961 if (cflag & CMSPAR)962 ctrl |= AUART_LINECTRL_SPS;963 }964 965 u->read_status_mask = AUART_STAT_OERR;966 967 if (termios->c_iflag & INPCK)968 u->read_status_mask |= AUART_STAT_PERR;969 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))970 u->read_status_mask |= AUART_STAT_BERR;971 972 /*973 * Characters to ignore974 */975 u->ignore_status_mask = 0;976 if (termios->c_iflag & IGNPAR)977 u->ignore_status_mask |= AUART_STAT_PERR;978 if (termios->c_iflag & IGNBRK) {979 u->ignore_status_mask |= AUART_STAT_BERR;980 /*981 * If we're ignoring parity and break indicators,982 * ignore overruns too (for real raw support).983 */984 if (termios->c_iflag & IGNPAR)985 u->ignore_status_mask |= AUART_STAT_OERR;986 }987 988 /*989 * ignore all characters if CREAD is not set990 */991 if (cflag & CREAD)992 ctrl2 |= AUART_CTRL2_RXE;993 else994 ctrl2 &= ~AUART_CTRL2_RXE;995 996 /* figure out the stop bits requested */997 if (cflag & CSTOPB)998 ctrl |= AUART_LINECTRL_STP2;999 1000 /* figure out the hardware flow control settings */1001 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);1002 if (cflag & CRTSCTS) {1003 /*1004 * The DMA has a bug(see errata:2836) in mx23.1005 * So we can not implement the DMA for auart in mx23,1006 * we can only implement the DMA support for auart1007 * in mx28.1008 */1009 if (is_imx28_auart(s)1010 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {1011 if (!mxs_auart_dma_init(s))1012 /* enable DMA tranfer */1013 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE1014 | AUART_CTRL2_DMAONERR;1015 }1016 /* Even if RTS is GPIO line RTSEN can be enabled because1017 * the pinctrl configuration decides about RTS pin function */1018 ctrl2 |= AUART_CTRL2_RTSEN;1019 if (CTS_AT_AUART())1020 ctrl2 |= AUART_CTRL2_CTSEN;1021 }1022 1023 /* set baud rate */1024 if (is_asm9260_auart(s)) {1025 baud = uart_get_baud_rate(u, termios, old,1026 u->uartclk * 4 / 0x3FFFFF,1027 u->uartclk / 16);1028 div = u->uartclk * 4 / baud;1029 } else {1030 baud_min = DIV_ROUND_UP(u->uartclk * 32,1031 AUART_LINECTRL_BAUD_DIV_MAX);1032 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;1033 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);1034 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);1035 }1036 1037 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);1038 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);1039 mxs_write(ctrl, s, REG_LINECTRL);1040 1041 mxs_write(ctrl2, s, REG_CTRL2);1042 1043 uart_update_timeout(u, termios->c_cflag, baud);1044 1045 /* prepare for the DMA RX. */1046 if (auart_dma_enabled(s) &&1047 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {1048 if (!mxs_auart_dma_prep_rx(s)) {1049 /* Disable the normal RX interrupt. */1050 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,1051 s, REG_INTR);1052 } else {1053 mxs_auart_dma_exit(s);1054 dev_err(s->dev, "We can not start up the DMA.\n");1055 }1056 }1057 1058 /* CTS flow-control and modem-status interrupts */1059 if (UART_ENABLE_MS(u, termios->c_cflag))1060 mxs_auart_enable_ms(u);1061 else1062 mxs_auart_disable_ms(u);1063}1064 1065static void mxs_auart_set_ldisc(struct uart_port *port,1066 struct ktermios *termios)1067{1068 if (termios->c_line == N_PPS) {1069 port->flags |= UPF_HARDPPS_CD;1070 mxs_auart_enable_ms(port);1071 } else {1072 port->flags &= ~UPF_HARDPPS_CD;1073 }1074}1075 1076static irqreturn_t mxs_auart_irq_handle(int irq, void *context)1077{1078 u32 istat, stat;1079 struct mxs_auart_port *s = context;1080 u32 mctrl_temp = s->mctrl_prev;1081 1082 uart_port_lock(&s->port);1083 1084 stat = mxs_read(s, REG_STAT);1085 istat = mxs_read(s, REG_INTR);1086 1087 /* ack irq */1088 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS1089 | AUART_INTR_CTSMIS), s, REG_INTR);1090 1091 /*1092 * Dealing with GPIO interrupt1093 */1094 if (irq == s->gpio_irq[UART_GPIO_CTS] ||1095 irq == s->gpio_irq[UART_GPIO_DCD] ||1096 irq == s->gpio_irq[UART_GPIO_DSR] ||1097 irq == s->gpio_irq[UART_GPIO_RI])1098 mxs_auart_modem_status(s,1099 mctrl_gpio_get(s->gpios, &mctrl_temp));1100 1101 if (istat & AUART_INTR_CTSMIS) {1102 if (CTS_AT_AUART() && s->ms_irq_enabled)1103 uart_handle_cts_change(&s->port,1104 stat & AUART_STAT_CTS);1105 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);1106 istat &= ~AUART_INTR_CTSMIS;1107 }1108 1109 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {1110 if (!auart_dma_enabled(s))1111 mxs_auart_rx_chars(s);1112 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);1113 }1114 1115 if (istat & AUART_INTR_TXIS) {1116 mxs_auart_tx_chars(s);1117 istat &= ~AUART_INTR_TXIS;1118 }1119 1120 uart_port_unlock(&s->port);1121 1122 return IRQ_HANDLED;1123}1124 1125static void mxs_auart_reset_deassert(struct mxs_auart_port *s)1126{1127 int i;1128 unsigned int reg;1129 1130 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);1131 1132 for (i = 0; i < 10000; i++) {1133 reg = mxs_read(s, REG_CTRL0);1134 if (!(reg & AUART_CTRL0_SFTRST))1135 break;1136 udelay(3);1137 }1138 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);1139}1140 1141static void mxs_auart_reset_assert(struct mxs_auart_port *s)1142{1143 int i;1144 u32 reg;1145 1146 reg = mxs_read(s, REG_CTRL0);1147 /* if already in reset state, keep it untouched */1148 if (reg & AUART_CTRL0_SFTRST)1149 return;1150 1151 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);1152 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);1153 1154 for (i = 0; i < 1000; i++) {1155 reg = mxs_read(s, REG_CTRL0);1156 /* reset is finished when the clock is gated */1157 if (reg & AUART_CTRL0_CLKGATE)1158 return;1159 udelay(10);1160 }1161 1162 dev_err(s->dev, "Failed to reset the unit.");1163}1164 1165static int mxs_auart_startup(struct uart_port *u)1166{1167 int ret;1168 struct mxs_auart_port *s = to_auart_port(u);1169 1170 ret = clk_prepare_enable(s->clk);1171 if (ret)1172 return ret;1173 1174 if (uart_console(u)) {1175 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);1176 } else {1177 /* reset the unit to a well known state */1178 mxs_auart_reset_assert(s);1179 mxs_auart_reset_deassert(s);1180 }1181 1182 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);1183 1184 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,1185 s, REG_INTR);1186 1187 /* Reset FIFO size (it could have changed if DMA was enabled) */1188 u->fifosize = MXS_AUART_FIFO_SIZE;1189 1190 /*1191 * Enable fifo so all four bytes of a DMA word are written to1192 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)1193 */1194 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);1195 1196 /* get initial status of modem lines */1197 mctrl_gpio_get(s->gpios, &s->mctrl_prev);1198 1199 s->ms_irq_enabled = false;1200 return 0;1201}1202 1203static void mxs_auart_shutdown(struct uart_port *u)1204{1205 struct mxs_auart_port *s = to_auart_port(u);1206 1207 mxs_auart_disable_ms(u);1208 1209 if (auart_dma_enabled(s))1210 mxs_auart_dma_exit(s);1211 1212 if (uart_console(u)) {1213 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);1214 1215 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |1216 AUART_INTR_CTSMIEN, s, REG_INTR);1217 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);1218 } else {1219 mxs_auart_reset_assert(s);1220 }1221 1222 clk_disable_unprepare(s->clk);1223}1224 1225static unsigned int mxs_auart_tx_empty(struct uart_port *u)1226{1227 struct mxs_auart_port *s = to_auart_port(u);1228 1229 if ((mxs_read(s, REG_STAT) &1230 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)1231 return TIOCSER_TEMT;1232 1233 return 0;1234}1235 1236static void mxs_auart_start_tx(struct uart_port *u)1237{1238 struct mxs_auart_port *s = to_auart_port(u);1239 1240 /* enable transmitter */1241 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);1242 1243 mxs_auart_tx_chars(s);1244}1245 1246static void mxs_auart_stop_tx(struct uart_port *u)1247{1248 struct mxs_auart_port *s = to_auart_port(u);1249 1250 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);1251}1252 1253static void mxs_auart_stop_rx(struct uart_port *u)1254{1255 struct mxs_auart_port *s = to_auart_port(u);1256 1257 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);1258}1259 1260static void mxs_auart_break_ctl(struct uart_port *u, int ctl)1261{1262 struct mxs_auart_port *s = to_auart_port(u);1263 1264 if (ctl)1265 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);1266 else1267 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);1268}1269 1270static const struct uart_ops mxs_auart_ops = {1271 .tx_empty = mxs_auart_tx_empty,1272 .start_tx = mxs_auart_start_tx,1273 .stop_tx = mxs_auart_stop_tx,1274 .stop_rx = mxs_auart_stop_rx,1275 .enable_ms = mxs_auart_enable_ms,1276 .break_ctl = mxs_auart_break_ctl,1277 .set_mctrl = mxs_auart_set_mctrl,1278 .get_mctrl = mxs_auart_get_mctrl,1279 .startup = mxs_auart_startup,1280 .shutdown = mxs_auart_shutdown,1281 .set_termios = mxs_auart_settermios,1282 .set_ldisc = mxs_auart_set_ldisc,1283 .type = mxs_auart_type,1284 .release_port = mxs_auart_release_port,1285 .request_port = mxs_auart_request_port,1286 .config_port = mxs_auart_config_port,1287 .verify_port = mxs_auart_verify_port,1288};1289 1290static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];1291 1292#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE1293static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch)1294{1295 struct mxs_auart_port *s = to_auart_port(port);1296 unsigned int to = 1000;1297 1298 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {1299 if (!to--)1300 break;1301 udelay(1);1302 }1303 1304 mxs_write(ch, s, REG_DATA);1305}1306 1307static void1308auart_console_write(struct console *co, const char *str, unsigned int count)1309{1310 struct mxs_auart_port *s;1311 struct uart_port *port;1312 unsigned int old_ctrl0, old_ctrl2;1313 unsigned int to = 20000;1314 1315 if (co->index >= MXS_AUART_PORTS || co->index < 0)1316 return;1317 1318 s = auart_port[co->index];1319 port = &s->port;1320 1321 clk_enable(s->clk);1322 1323 /* First save the CR then disable the interrupts */1324 old_ctrl2 = mxs_read(s, REG_CTRL2);1325 old_ctrl0 = mxs_read(s, REG_CTRL0);1326 1327 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);1328 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);1329 1330 uart_console_write(port, str, count, mxs_auart_console_putchar);1331 1332 /* Finally, wait for transmitter to become empty ... */1333 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {1334 udelay(1);1335 if (!to--)1336 break;1337 }1338 1339 /*1340 * ... and restore the TCR if we waited long enough for the transmitter1341 * to be idle. This might keep the transmitter enabled although it is1342 * unused, but that is better than to disable it while it is still1343 * transmitting.1344 */1345 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {1346 mxs_write(old_ctrl0, s, REG_CTRL0);1347 mxs_write(old_ctrl2, s, REG_CTRL2);1348 }1349 1350 clk_disable(s->clk);1351}1352 1353static void __init1354auart_console_get_options(struct mxs_auart_port *s, int *baud,1355 int *parity, int *bits)1356{1357 struct uart_port *port = &s->port;1358 unsigned int lcr_h, quot;1359 1360 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))1361 return;1362 1363 lcr_h = mxs_read(s, REG_LINECTRL);1364 1365 *parity = 'n';1366 if (lcr_h & AUART_LINECTRL_PEN) {1367 if (lcr_h & AUART_LINECTRL_EPS)1368 *parity = 'e';1369 else1370 *parity = 'o';1371 }1372 1373 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7))1374 *bits = 7;1375 else1376 *bits = 8;1377 1378 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))1379 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);1380 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))1381 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;1382 if (quot == 0)1383 quot = 1;1384 1385 *baud = (port->uartclk << 2) / quot;1386}1387 1388static int __init1389auart_console_setup(struct console *co, char *options)1390{1391 struct mxs_auart_port *s;1392 int baud = 9600;1393 int bits = 8;1394 int parity = 'n';1395 int flow = 'n';1396 int ret;1397 1398 /*1399 * Check whether an invalid uart number has been specified, and1400 * if so, search for the first available port that does have1401 * console support.1402 */1403 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))1404 co->index = 0;1405 s = auart_port[co->index];1406 if (!s)1407 return -ENODEV;1408 1409 ret = clk_prepare_enable(s->clk);1410 if (ret)1411 return ret;1412 1413 if (options)1414 uart_parse_options(options, &baud, &parity, &bits, &flow);1415 else1416 auart_console_get_options(s, &baud, &parity, &bits);1417 1418 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);1419 1420 clk_disable_unprepare(s->clk);1421 1422 return ret;1423}1424 1425static struct console auart_console = {1426 .name = "ttyAPP",1427 .write = auart_console_write,1428 .device = uart_console_device,1429 .setup = auart_console_setup,1430 .flags = CON_PRINTBUFFER,1431 .index = -1,1432 .data = &auart_driver,1433};1434#endif1435 1436static struct uart_driver auart_driver = {1437 .owner = THIS_MODULE,1438 .driver_name = "ttyAPP",1439 .dev_name = "ttyAPP",1440 .major = 0,1441 .minor = 0,1442 .nr = MXS_AUART_PORTS,1443#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE1444 .cons = &auart_console,1445#endif1446};1447 1448static void mxs_init_regs(struct mxs_auart_port *s)1449{1450 if (is_asm9260_auart(s))1451 s->vendor = &vendor_alphascale_asm9260;1452 else1453 s->vendor = &vendor_freescale_stmp37xx;1454}1455 1456static int mxs_get_clks(struct mxs_auart_port *s,1457 struct platform_device *pdev)1458{1459 int err;1460 1461 if (!is_asm9260_auart(s)) {1462 s->clk = devm_clk_get(&pdev->dev, NULL);1463 return PTR_ERR_OR_ZERO(s->clk);1464 }1465 1466 s->clk = devm_clk_get(s->dev, "mod");1467 if (IS_ERR(s->clk)) {1468 dev_err(s->dev, "Failed to get \"mod\" clk\n");1469 return PTR_ERR(s->clk);1470 }1471 1472 s->clk_ahb = devm_clk_get(s->dev, "ahb");1473 if (IS_ERR(s->clk_ahb)) {1474 dev_err(s->dev, "Failed to get \"ahb\" clk\n");1475 return PTR_ERR(s->clk_ahb);1476 }1477 1478 err = clk_prepare_enable(s->clk_ahb);1479 if (err) {1480 dev_err(s->dev, "Failed to enable ahb_clk!\n");1481 return err;1482 }1483 1484 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));1485 if (err) {1486 dev_err(s->dev, "Failed to set rate!\n");1487 goto disable_clk_ahb;1488 }1489 1490 err = clk_prepare_enable(s->clk);1491 if (err) {1492 dev_err(s->dev, "Failed to enable clk!\n");1493 goto disable_clk_ahb;1494 }1495 1496 return 0;1497 1498disable_clk_ahb:1499 clk_disable_unprepare(s->clk_ahb);1500 return err;1501}1502 1503static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)1504{1505 enum mctrl_gpio_idx i;1506 struct gpio_desc *gpiod;1507 1508 s->gpios = mctrl_gpio_init_noauto(dev, 0);1509 if (IS_ERR(s->gpios))1510 return PTR_ERR(s->gpios);1511 1512 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */1513 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {1514 if (test_bit(MXS_AUART_RTSCTS, &s->flags))1515 dev_warn(dev,1516 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");1517 clear_bit(MXS_AUART_RTSCTS, &s->flags);1518 }1519 1520 for (i = 0; i < UART_GPIO_MAX; i++) {1521 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);1522 if (gpiod && (gpiod_get_direction(gpiod) == 1))1523 s->gpio_irq[i] = gpiod_to_irq(gpiod);1524 else1525 s->gpio_irq[i] = -EINVAL;1526 }1527 1528 return 0;1529}1530 1531static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)1532{1533 enum mctrl_gpio_idx i;1534 1535 for (i = 0; i < UART_GPIO_MAX; i++)1536 if (s->gpio_irq[i] >= 0)1537 free_irq(s->gpio_irq[i], s);1538}1539 1540static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)1541{1542 int *irq = s->gpio_irq;1543 enum mctrl_gpio_idx i;1544 int err = 0;1545 1546 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {1547 if (irq[i] < 0)1548 continue;1549 1550 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);1551 err = request_irq(irq[i], mxs_auart_irq_handle,1552 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);1553 if (err)1554 dev_err(s->dev, "%s - Can't get %d irq\n",1555 __func__, irq[i]);1556 }1557 1558 /*1559 * If something went wrong, rollback.1560 * Be careful: i may be unsigned.1561 */1562 while (err && (i-- > 0))1563 if (irq[i] >= 0)1564 free_irq(irq[i], s);1565 1566 return err;1567}1568 1569static int mxs_auart_probe(struct platform_device *pdev)1570{1571 struct device_node *np = pdev->dev.of_node;1572 struct mxs_auart_port *s;1573 u32 version;1574 int ret, irq;1575 struct resource *r;1576 1577 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);1578 if (!s)1579 return -ENOMEM;1580 1581 s->port.dev = &pdev->dev;1582 s->dev = &pdev->dev;1583 1584 ret = of_alias_get_id(np, "serial");1585 if (ret < 0) {1586 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);1587 return ret;1588 }1589 s->port.line = ret;1590 1591 if (of_property_read_bool(np, "uart-has-rtscts") ||1592 of_property_read_bool(np, "fsl,uart-has-rtscts") /* deprecated */)1593 set_bit(MXS_AUART_RTSCTS, &s->flags);1594 1595 if (s->port.line >= ARRAY_SIZE(auart_port)) {1596 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);1597 return -EINVAL;1598 }1599 1600 s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);1601 1602 ret = mxs_get_clks(s, pdev);1603 if (ret)1604 return ret;1605 1606 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);1607 if (!r) {1608 ret = -ENXIO;1609 goto out_disable_clks;1610 }1611 1612 s->port.mapbase = r->start;1613 s->port.membase = ioremap(r->start, resource_size(r));1614 if (!s->port.membase) {1615 ret = -ENOMEM;1616 goto out_disable_clks;1617 }1618 s->port.ops = &mxs_auart_ops;1619 s->port.iotype = UPIO_MEM;1620 s->port.fifosize = MXS_AUART_FIFO_SIZE;1621 s->port.uartclk = clk_get_rate(s->clk);1622 s->port.type = PORT_IMX;1623 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);1624 1625 mxs_init_regs(s);1626 1627 s->mctrl_prev = 0;1628 1629 irq = platform_get_irq(pdev, 0);1630 if (irq < 0) {1631 ret = irq;1632 goto out_iounmap;1633 }1634 1635 s->port.irq = irq;1636 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,1637 dev_name(&pdev->dev), s);1638 if (ret)1639 goto out_iounmap;1640 1641 platform_set_drvdata(pdev, s);1642 1643 ret = mxs_auart_init_gpios(s, &pdev->dev);1644 if (ret) {1645 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");1646 goto out_iounmap;1647 }1648 1649 /*1650 * Get the GPIO lines IRQ1651 */1652 ret = mxs_auart_request_gpio_irq(s);1653 if (ret)1654 goto out_iounmap;1655 1656 auart_port[s->port.line] = s;1657 1658 mxs_auart_reset_deassert(s);1659 1660 ret = uart_add_one_port(&auart_driver, &s->port);1661 if (ret)1662 goto out_free_qpio_irq;1663 1664 /* ASM9260 don't have version reg */1665 if (is_asm9260_auart(s)) {1666 dev_info(&pdev->dev, "Found APPUART ASM9260\n");1667 } else {1668 version = mxs_read(s, REG_VERSION);1669 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",1670 (version >> 24) & 0xff,1671 (version >> 16) & 0xff, version & 0xffff);1672 }1673 1674 return 0;1675 1676out_free_qpio_irq:1677 mxs_auart_free_gpio_irq(s);1678 auart_port[pdev->id] = NULL;1679 1680out_iounmap:1681 iounmap(s->port.membase);1682 1683out_disable_clks:1684 if (is_asm9260_auart(s)) {1685 clk_disable_unprepare(s->clk);1686 clk_disable_unprepare(s->clk_ahb);1687 }1688 return ret;1689}1690 1691static void mxs_auart_remove(struct platform_device *pdev)1692{1693 struct mxs_auart_port *s = platform_get_drvdata(pdev);1694 1695 uart_remove_one_port(&auart_driver, &s->port);1696 auart_port[pdev->id] = NULL;1697 mxs_auart_free_gpio_irq(s);1698 iounmap(s->port.membase);1699 if (is_asm9260_auart(s)) {1700 clk_disable_unprepare(s->clk);1701 clk_disable_unprepare(s->clk_ahb);1702 }1703}1704 1705static struct platform_driver mxs_auart_driver = {1706 .probe = mxs_auart_probe,1707 .remove_new = mxs_auart_remove,1708 .driver = {1709 .name = "mxs-auart",1710 .of_match_table = mxs_auart_dt_ids,1711 },1712};1713 1714static int __init mxs_auart_init(void)1715{1716 int r;1717 1718 r = uart_register_driver(&auart_driver);1719 if (r)1720 goto out;1721 1722 r = platform_driver_register(&mxs_auart_driver);1723 if (r)1724 goto out_err;1725 1726 return 0;1727out_err:1728 uart_unregister_driver(&auart_driver);1729out:1730 return r;1731}1732 1733static void __exit mxs_auart_exit(void)1734{1735 platform_driver_unregister(&mxs_auart_driver);1736 uart_unregister_driver(&auart_driver);1737}1738 1739module_init(mxs_auart_init);1740module_exit(mxs_auart_exit);1741MODULE_LICENSE("GPL");1742MODULE_DESCRIPTION("Freescale MXS application uart driver");1743MODULE_ALIAS("platform:mxs-auart");1744