1838 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Driver for OMAP-UART controller.4 * Based on drivers/serial/8250.c5 *6 * Copyright (C) 2010 Texas Instruments.7 *8 * Authors:9 * Govindraj R <govindraj.raja@ti.com>10 * Thara Gopinath <thara@ti.com>11 *12 * Note: This driver is made separate from 8250 driver as we cannot13 * over load 8250 driver with omap platform specific configuration for14 * features like DMA, it makes easier to implement features like DMA and15 * hardware flow control and software flow control configuration with16 * this driver as required for the omap-platform.17 */18 19#include <linux/module.h>20#include <linux/init.h>21#include <linux/console.h>22#include <linux/serial.h>23#include <linux/serial_reg.h>24#include <linux/delay.h>25#include <linux/slab.h>26#include <linux/tty.h>27#include <linux/tty_flip.h>28#include <linux/platform_device.h>29#include <linux/io.h>30#include <linux/clk.h>31#include <linux/serial_core.h>32#include <linux/irq.h>33#include <linux/pm_runtime.h>34#include <linux/pm_wakeirq.h>35#include <linux/of.h>36#include <linux/of_irq.h>37#include <linux/gpio/consumer.h>38#include <linux/platform_data/serial-omap.h>39 40#define OMAP_MAX_HSUART_PORTS 1041 42#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))43 44#define OMAP_UART_REV_42 0x040245#define OMAP_UART_REV_46 0x040646#define OMAP_UART_REV_52 0x050247#define OMAP_UART_REV_63 0x060348 49#define OMAP_UART_TX_WAKEUP_EN BIT(7)50 51/* Feature flags */52#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)53 54#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)55#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)56 57#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */58 59/* SCR register bitmasks */60#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)61#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)62#define OMAP_UART_SCR_TX_EMPTY (1 << 3)63 64/* FCR register bitmasks */65#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)66#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)67 68/* MVR register bitmasks */69#define OMAP_UART_MVR_SCHEME_SHIFT 3070 71#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf072#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 473#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f74 75#define OMAP_UART_MVR_MAJ_MASK 0x70076#define OMAP_UART_MVR_MAJ_SHIFT 877#define OMAP_UART_MVR_MIN_MASK 0x3f78 79#define OMAP_UART_DMA_CH_FREE -180 81#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA82#define OMAP_MODE13X_SPEED 23040083 84/* WER = 0x7F85 * Enable module level wakeup in WER reg86 */87#define OMAP_UART_WER_MOD_WKUP 0x7F88 89/* Enable XON/XOFF flow control on output */90#define OMAP_UART_SW_TX 0x0891 92/* Enable XON/XOFF flow control on input */93#define OMAP_UART_SW_RX 0x0294 95#define OMAP_UART_SW_CLR 0xF096 97#define OMAP_UART_TCR_TRIG 0x0F98 99struct uart_omap_dma {100 u8 uart_dma_tx;101 u8 uart_dma_rx;102 int rx_dma_channel;103 int tx_dma_channel;104 dma_addr_t rx_buf_dma_phys;105 dma_addr_t tx_buf_dma_phys;106 unsigned int uart_base;107 /*108 * Buffer for rx dma. It is not required for tx because the buffer109 * comes from port structure.110 */111 unsigned char *rx_buf;112 unsigned int prev_rx_dma_pos;113 int tx_buf_size;114 int tx_dma_used;115 int rx_dma_used;116 spinlock_t tx_lock;117 spinlock_t rx_lock;118 /* timer to poll activity on rx dma */119 struct timer_list rx_timer;120 unsigned int rx_buf_size;121 unsigned int rx_poll_rate;122 unsigned int rx_timeout;123};124 125struct uart_omap_port {126 struct uart_port port;127 struct uart_omap_dma uart_dma;128 struct device *dev;129 int wakeirq;130 131 unsigned char ier;132 unsigned char lcr;133 unsigned char mcr;134 unsigned char fcr;135 unsigned char efr;136 unsigned char dll;137 unsigned char dlh;138 unsigned char mdr1;139 unsigned char scr;140 unsigned char wer;141 142 int use_dma;143 /*144 * Some bits in registers are cleared on a read, so they must145 * be saved whenever the register is read, but the bits will not146 * be immediately processed.147 */148 unsigned int lsr_break_flag;149 unsigned char msr_saved_flags;150 char name[20];151 unsigned long port_activity;152 int context_loss_cnt;153 u32 errata;154 u32 features;155 156 struct gpio_desc *rts_gpiod;157 158 struct pm_qos_request pm_qos_request;159 u32 latency;160 u32 calc_latency;161 struct work_struct qos_work;162 bool is_suspending;163 164 unsigned int rs485_tx_filter_count;165};166 167#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))168 169static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];170 171/* Forward declaration of functions */172static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);173 174static inline unsigned int serial_in(struct uart_omap_port *up, int offset)175{176 offset <<= up->port.regshift;177 return readw(up->port.membase + offset);178}179 180static inline void serial_out(struct uart_omap_port *up, int offset, int value)181{182 offset <<= up->port.regshift;183 writew(value, up->port.membase + offset);184}185 186static inline void serial_omap_clear_fifos(struct uart_omap_port *up)187{188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);191 serial_out(up, UART_FCR, 0);192}193 194#ifdef CONFIG_PM195static int serial_omap_get_context_loss_count(struct uart_omap_port *up)196{197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);198 199 if (!pdata || !pdata->get_context_loss_count)200 return -EINVAL;201 202 return pdata->get_context_loss_count(up->dev);203}204 205/* REVISIT: Remove this when omap3 boots in device tree only mode */206static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)207{208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);209 210 if (!pdata || !pdata->enable_wakeup)211 return;212 213 pdata->enable_wakeup(up->dev, enable);214}215#endif /* CONFIG_PM */216 217/*218 * Calculate the absolute difference between the desired and actual baud219 * rate for the given mode.220 */221static inline int calculate_baud_abs_diff(struct uart_port *port,222 unsigned int baud, unsigned int mode)223{224 unsigned int n = port->uartclk / (mode * baud);225 226 if (n == 0)227 n = 1;228 229 return abs_diff(baud, port->uartclk / (mode * n));230}231 232/*233 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X234 * @port: uart port info235 * @baud: baudrate for which mode needs to be determined236 *237 * Returns true if baud rate is MODE16X and false if MODE13X238 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,239 * and Error Rates" determines modes not for all common baud rates.240 * E.g. for 1000000 baud rate mode must be 16x, but according to that241 * table it's determined as 13x.242 */243static bool244serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)245{246 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);247 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);248 249 return (abs_diff_13 >= abs_diff_16);250}251 252/*253 * serial_omap_get_divisor - calculate divisor value254 * @port: uart port info255 * @baud: baudrate for which divisor needs to be calculated.256 */257static unsigned int258serial_omap_get_divisor(struct uart_port *port, unsigned int baud)259{260 unsigned int mode;261 262 if (!serial_omap_baud_is_mode16(port, baud))263 mode = 13;264 else265 mode = 16;266 return port->uartclk/(mode * baud);267}268 269static void serial_omap_enable_ms(struct uart_port *port)270{271 struct uart_omap_port *up = to_uart_omap_port(port);272 273 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);274 275 up->ier |= UART_IER_MSI;276 serial_out(up, UART_IER, up->ier);277}278 279static void serial_omap_stop_tx(struct uart_port *port)280{281 struct uart_omap_port *up = to_uart_omap_port(port);282 int res;283 284 /* Handle RS-485 */285 if (port->rs485.flags & SER_RS485_ENABLED) {286 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {287 /* THR interrupt is fired when both TX FIFO and TX288 * shift register are empty. This means there's nothing289 * left to transmit now, so make sure the THR interrupt290 * is fired when TX FIFO is below the trigger level,291 * disable THR interrupts and toggle the RS-485 GPIO292 * data direction pin if needed.293 */294 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;295 serial_out(up, UART_OMAP_SCR, up->scr);296 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?297 1 : 0;298 if (gpiod_get_value(up->rts_gpiod) != res) {299 if (port->rs485.delay_rts_after_send > 0)300 mdelay(301 port->rs485.delay_rts_after_send);302 gpiod_set_value(up->rts_gpiod, res);303 }304 } else {305 /* We're asked to stop, but there's still stuff in the306 * UART FIFO, so make sure the THR interrupt is fired307 * when both TX FIFO and TX shift register are empty.308 * The next THR interrupt (if no transmission is started309 * in the meantime) will indicate the end of a310 * transmission. Therefore we _don't_ disable THR311 * interrupts in this situation.312 */313 up->scr |= OMAP_UART_SCR_TX_EMPTY;314 serial_out(up, UART_OMAP_SCR, up->scr);315 return;316 }317 }318 319 if (up->ier & UART_IER_THRI) {320 up->ier &= ~UART_IER_THRI;321 serial_out(up, UART_IER, up->ier);322 }323}324 325static void serial_omap_stop_rx(struct uart_port *port)326{327 struct uart_omap_port *up = to_uart_omap_port(port);328 329 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);330 up->port.read_status_mask &= ~UART_LSR_DR;331 serial_out(up, UART_IER, up->ier);332}333 334static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch)335{336 serial_out(up, UART_TX, ch);337 338 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&339 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))340 up->rs485_tx_filter_count++;341}342 343static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)344{345 u8 ch;346 347 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4,348 true,349 serial_omap_put_char(up, ch),350 ({}));351}352 353static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)354{355 if (!(up->ier & UART_IER_THRI)) {356 up->ier |= UART_IER_THRI;357 serial_out(up, UART_IER, up->ier);358 }359}360 361static void serial_omap_start_tx(struct uart_port *port)362{363 struct uart_omap_port *up = to_uart_omap_port(port);364 int res;365 366 /* Handle RS-485 */367 if (port->rs485.flags & SER_RS485_ENABLED) {368 /* Fire THR interrupts when FIFO is below trigger level */369 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;370 serial_out(up, UART_OMAP_SCR, up->scr);371 372 /* if rts not already enabled */373 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;374 if (gpiod_get_value(up->rts_gpiod) != res) {375 gpiod_set_value(up->rts_gpiod, res);376 if (port->rs485.delay_rts_before_send > 0)377 mdelay(port->rs485.delay_rts_before_send);378 }379 }380 381 if ((port->rs485.flags & SER_RS485_ENABLED) &&382 !(port->rs485.flags & SER_RS485_RX_DURING_TX))383 up->rs485_tx_filter_count = 0;384 385 serial_omap_enable_ier_thri(up);386}387 388static void serial_omap_throttle(struct uart_port *port)389{390 struct uart_omap_port *up = to_uart_omap_port(port);391 unsigned long flags;392 393 uart_port_lock_irqsave(&up->port, &flags);394 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);395 serial_out(up, UART_IER, up->ier);396 uart_port_unlock_irqrestore(&up->port, flags);397}398 399static void serial_omap_unthrottle(struct uart_port *port)400{401 struct uart_omap_port *up = to_uart_omap_port(port);402 unsigned long flags;403 404 uart_port_lock_irqsave(&up->port, &flags);405 up->ier |= UART_IER_RLSI | UART_IER_RDI;406 serial_out(up, UART_IER, up->ier);407 uart_port_unlock_irqrestore(&up->port, flags);408}409 410static unsigned int check_modem_status(struct uart_omap_port *up)411{412 unsigned int status;413 414 status = serial_in(up, UART_MSR);415 status |= up->msr_saved_flags;416 up->msr_saved_flags = 0;417 if ((status & UART_MSR_ANY_DELTA) == 0)418 return status;419 420 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&421 up->port.state != NULL) {422 if (status & UART_MSR_TERI)423 up->port.icount.rng++;424 if (status & UART_MSR_DDSR)425 up->port.icount.dsr++;426 if (status & UART_MSR_DDCD)427 uart_handle_dcd_change428 (&up->port, status & UART_MSR_DCD);429 if (status & UART_MSR_DCTS)430 uart_handle_cts_change431 (&up->port, status & UART_MSR_CTS);432 wake_up_interruptible(&up->port.state->port.delta_msr_wait);433 }434 435 return status;436}437 438static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)439{440 u8 flag;441 442 /*443 * Read one data character out to avoid stalling the receiver according444 * to the table 23-246 of the omap4 TRM.445 */446 if (likely(lsr & UART_LSR_DR)) {447 serial_in(up, UART_RX);448 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&449 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&450 up->rs485_tx_filter_count)451 up->rs485_tx_filter_count--;452 }453 454 up->port.icount.rx++;455 flag = TTY_NORMAL;456 457 if (lsr & UART_LSR_BI) {458 flag = TTY_BREAK;459 lsr &= ~(UART_LSR_FE | UART_LSR_PE);460 up->port.icount.brk++;461 /*462 * We do the SysRQ and SAK checking463 * here because otherwise the break464 * may get masked by ignore_status_mask465 * or read_status_mask.466 */467 if (uart_handle_break(&up->port))468 return;469 470 }471 472 if (lsr & UART_LSR_PE) {473 flag = TTY_PARITY;474 up->port.icount.parity++;475 }476 477 if (lsr & UART_LSR_FE) {478 flag = TTY_FRAME;479 up->port.icount.frame++;480 }481 482 if (lsr & UART_LSR_OE)483 up->port.icount.overrun++;484 485#ifdef CONFIG_SERIAL_OMAP_CONSOLE486 if (up->port.line == up->port.cons->index) {487 /* Recover the break flag from console xmit */488 lsr |= up->lsr_break_flag;489 }490#endif491 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);492}493 494static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)495{496 u8 ch;497 498 if (!(lsr & UART_LSR_DR))499 return;500 501 ch = serial_in(up, UART_RX);502 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&503 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&504 up->rs485_tx_filter_count) {505 up->rs485_tx_filter_count--;506 return;507 }508 509 up->port.icount.rx++;510 511 if (uart_prepare_sysrq_char(&up->port, ch))512 return;513 514 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, TTY_NORMAL);515}516 517/**518 * serial_omap_irq() - This handles the interrupt from one port519 * @irq: uart port irq number520 * @dev_id: uart port info521 */522static irqreturn_t serial_omap_irq(int irq, void *dev_id)523{524 struct uart_omap_port *up = dev_id;525 unsigned int iir, lsr;526 unsigned int type;527 irqreturn_t ret = IRQ_NONE;528 int max_count = 256;529 530 uart_port_lock(&up->port);531 532 do {533 iir = serial_in(up, UART_IIR);534 if (iir & UART_IIR_NO_INT)535 break;536 537 ret = IRQ_HANDLED;538 lsr = serial_in(up, UART_LSR);539 540 /* extract IRQ type from IIR register */541 type = iir & 0x3e;542 543 switch (type) {544 case UART_IIR_MSI:545 check_modem_status(up);546 break;547 case UART_IIR_THRI:548 transmit_chars(up, lsr);549 break;550 case UART_IIR_RX_TIMEOUT:551 case UART_IIR_RDI:552 serial_omap_rdi(up, lsr);553 break;554 case UART_IIR_RLSI:555 serial_omap_rlsi(up, lsr);556 break;557 case UART_IIR_CTS_RTS_DSR:558 /* simply try again */559 break;560 case UART_IIR_XOFF:561 default:562 break;563 }564 } while (max_count--);565 566 uart_unlock_and_check_sysrq(&up->port);567 568 tty_flip_buffer_push(&up->port.state->port);569 570 up->port_activity = jiffies;571 572 return ret;573}574 575static unsigned int serial_omap_tx_empty(struct uart_port *port)576{577 struct uart_omap_port *up = to_uart_omap_port(port);578 unsigned long flags;579 unsigned int ret = 0;580 581 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);582 uart_port_lock_irqsave(&up->port, &flags);583 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;584 uart_port_unlock_irqrestore(&up->port, flags);585 586 return ret;587}588 589static unsigned int serial_omap_get_mctrl(struct uart_port *port)590{591 struct uart_omap_port *up = to_uart_omap_port(port);592 unsigned int status;593 unsigned int ret = 0;594 595 status = check_modem_status(up);596 597 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);598 599 if (status & UART_MSR_DCD)600 ret |= TIOCM_CAR;601 if (status & UART_MSR_RI)602 ret |= TIOCM_RNG;603 if (status & UART_MSR_DSR)604 ret |= TIOCM_DSR;605 if (status & UART_MSR_CTS)606 ret |= TIOCM_CTS;607 return ret;608}609 610static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)611{612 struct uart_omap_port *up = to_uart_omap_port(port);613 unsigned char mcr = 0, old_mcr, lcr;614 615 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);616 if (mctrl & TIOCM_RTS)617 mcr |= UART_MCR_RTS;618 if (mctrl & TIOCM_DTR)619 mcr |= UART_MCR_DTR;620 if (mctrl & TIOCM_OUT1)621 mcr |= UART_MCR_OUT1;622 if (mctrl & TIOCM_OUT2)623 mcr |= UART_MCR_OUT2;624 if (mctrl & TIOCM_LOOP)625 mcr |= UART_MCR_LOOP;626 627 old_mcr = serial_in(up, UART_MCR);628 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |629 UART_MCR_DTR | UART_MCR_RTS);630 up->mcr = old_mcr | mcr;631 serial_out(up, UART_MCR, up->mcr);632 633 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */634 lcr = serial_in(up, UART_LCR);635 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);636 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))637 up->efr |= UART_EFR_RTS;638 else639 up->efr &= ~UART_EFR_RTS;640 serial_out(up, UART_EFR, up->efr);641 serial_out(up, UART_LCR, lcr);642}643 644static void serial_omap_break_ctl(struct uart_port *port, int break_state)645{646 struct uart_omap_port *up = to_uart_omap_port(port);647 unsigned long flags;648 649 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);650 uart_port_lock_irqsave(&up->port, &flags);651 if (break_state == -1)652 up->lcr |= UART_LCR_SBC;653 else654 up->lcr &= ~UART_LCR_SBC;655 serial_out(up, UART_LCR, up->lcr);656 uart_port_unlock_irqrestore(&up->port, flags);657}658 659static int serial_omap_startup(struct uart_port *port)660{661 struct uart_omap_port *up = to_uart_omap_port(port);662 unsigned long flags;663 int retval;664 665 /*666 * Allocate the IRQ667 */668 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,669 up->name, up);670 if (retval)671 return retval;672 673 /* Optional wake-up IRQ */674 if (up->wakeirq) {675 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);676 if (retval) {677 free_irq(up->port.irq, up);678 return retval;679 }680 }681 682 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);683 684 pm_runtime_get_sync(up->dev);685 /*686 * Clear the FIFO buffers and disable them.687 * (they will be reenabled in set_termios())688 */689 serial_omap_clear_fifos(up);690 691 /*692 * Clear the interrupt registers.693 */694 (void) serial_in(up, UART_LSR);695 if (serial_in(up, UART_LSR) & UART_LSR_DR)696 (void) serial_in(up, UART_RX);697 (void) serial_in(up, UART_IIR);698 (void) serial_in(up, UART_MSR);699 700 /*701 * Now, initialize the UART702 */703 serial_out(up, UART_LCR, UART_LCR_WLEN8);704 uart_port_lock_irqsave(&up->port, &flags);705 /*706 * Most PC uarts need OUT2 raised to enable interrupts.707 */708 up->port.mctrl |= TIOCM_OUT2;709 serial_omap_set_mctrl(&up->port, up->port.mctrl);710 uart_port_unlock_irqrestore(&up->port, flags);711 712 up->msr_saved_flags = 0;713 /*714 * Finally, enable interrupts. Note: Modem status interrupts715 * are set via set_termios(), which will be occurring imminently716 * anyway, so we don't enable them here.717 */718 up->ier = UART_IER_RLSI | UART_IER_RDI;719 serial_out(up, UART_IER, up->ier);720 721 /* Enable module level wake up */722 up->wer = OMAP_UART_WER_MOD_WKUP;723 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)724 up->wer |= OMAP_UART_TX_WAKEUP_EN;725 726 serial_out(up, UART_OMAP_WER, up->wer);727 728 up->port_activity = jiffies;729 return 0;730}731 732static void serial_omap_shutdown(struct uart_port *port)733{734 struct uart_omap_port *up = to_uart_omap_port(port);735 unsigned long flags;736 737 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);738 739 /*740 * Disable interrupts from this port741 */742 up->ier = 0;743 serial_out(up, UART_IER, 0);744 745 uart_port_lock_irqsave(&up->port, &flags);746 up->port.mctrl &= ~TIOCM_OUT2;747 serial_omap_set_mctrl(&up->port, up->port.mctrl);748 uart_port_unlock_irqrestore(&up->port, flags);749 750 /*751 * Disable break condition and FIFOs752 */753 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);754 serial_omap_clear_fifos(up);755 756 /*757 * Read data port to reset things, and then free the irq758 */759 if (serial_in(up, UART_LSR) & UART_LSR_DR)760 (void) serial_in(up, UART_RX);761 762 pm_runtime_put_sync(up->dev);763 free_irq(up->port.irq, up);764 dev_pm_clear_wake_irq(up->dev);765}766 767static void serial_omap_uart_qos_work(struct work_struct *work)768{769 struct uart_omap_port *up = container_of(work, struct uart_omap_port,770 qos_work);771 772 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);773}774 775static void776serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,777 const struct ktermios *old)778{779 struct uart_omap_port *up = to_uart_omap_port(port);780 unsigned char cval = 0;781 unsigned long flags;782 unsigned int baud, quot;783 784 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));785 786 if (termios->c_cflag & CSTOPB)787 cval |= UART_LCR_STOP;788 if (termios->c_cflag & PARENB)789 cval |= UART_LCR_PARITY;790 if (!(termios->c_cflag & PARODD))791 cval |= UART_LCR_EPAR;792 if (termios->c_cflag & CMSPAR)793 cval |= UART_LCR_SPAR;794 795 /*796 * Ask the core to calculate the divisor for us.797 */798 799 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);800 quot = serial_omap_get_divisor(port, baud);801 802 /* calculate wakeup latency constraint */803 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);804 up->latency = up->calc_latency;805 schedule_work(&up->qos_work);806 807 up->dll = quot & 0xff;808 up->dlh = quot >> 8;809 up->mdr1 = UART_OMAP_MDR1_DISABLE;810 811 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |812 UART_FCR_ENABLE_FIFO;813 814 /*815 * Ok, we're now changing the port state. Do it with816 * interrupts disabled.817 */818 uart_port_lock_irqsave(&up->port, &flags);819 820 /*821 * Update the per-port timeout.822 */823 uart_update_timeout(port, termios->c_cflag, baud);824 825 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;826 if (termios->c_iflag & INPCK)827 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;828 if (termios->c_iflag & (BRKINT | PARMRK))829 up->port.read_status_mask |= UART_LSR_BI;830 831 /*832 * Characters to ignore833 */834 up->port.ignore_status_mask = 0;835 if (termios->c_iflag & IGNPAR)836 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;837 if (termios->c_iflag & IGNBRK) {838 up->port.ignore_status_mask |= UART_LSR_BI;839 /*840 * If we're ignoring parity and break indicators,841 * ignore overruns too (for real raw support).842 */843 if (termios->c_iflag & IGNPAR)844 up->port.ignore_status_mask |= UART_LSR_OE;845 }846 847 /*848 * ignore all characters if CREAD is not set849 */850 if ((termios->c_cflag & CREAD) == 0)851 up->port.ignore_status_mask |= UART_LSR_DR;852 853 /*854 * Modem status interrupts855 */856 up->ier &= ~UART_IER_MSI;857 if (UART_ENABLE_MS(&up->port, termios->c_cflag))858 up->ier |= UART_IER_MSI;859 serial_out(up, UART_IER, up->ier);860 serial_out(up, UART_LCR, cval); /* reset DLAB */861 up->lcr = cval;862 up->scr = 0;863 864 /* FIFOs and DMA Settings */865 866 /* FCR can be changed only when the867 * baud clock is not running868 * DLL_REG and DLH_REG set to 0.869 */870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);871 serial_out(up, UART_DLL, 0);872 serial_out(up, UART_DLM, 0);873 serial_out(up, UART_LCR, 0);874 875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);876 877 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;878 up->efr &= ~UART_EFR_SCD;879 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);880 881 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);882 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;883 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);884 /* FIFO ENABLE, DMA MODE */885 886 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;887 /*888 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK889 * sets Enables the granularity of 1 for TRIGGER RX890 * level. Along with setting RX FIFO trigger level891 * to 1 (as noted below, 16 characters) and TLR[3:0]892 * to zero this will result RX FIFO threshold level893 * to 1 character, instead of 16 as noted in comment894 * below.895 */896 897 /* Set receive FIFO threshold to 16 characters and898 * transmit FIFO threshold to 32 spaces899 */900 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;901 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;902 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |903 UART_FCR_ENABLE_FIFO;904 905 serial_out(up, UART_FCR, up->fcr);906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);907 908 serial_out(up, UART_OMAP_SCR, up->scr);909 910 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);912 serial_out(up, UART_MCR, up->mcr);913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);914 serial_out(up, UART_EFR, up->efr);915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);916 917 /* Protocol, Baud Rate, and Interrupt Settings */918 919 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)920 serial_omap_mdr1_errataset(up, up->mdr1);921 else922 serial_out(up, UART_OMAP_MDR1, up->mdr1);923 924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);925 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);926 927 serial_out(up, UART_LCR, 0);928 serial_out(up, UART_IER, 0);929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);930 931 serial_out(up, UART_DLL, up->dll); /* LS of divisor */932 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */933 934 serial_out(up, UART_LCR, 0);935 serial_out(up, UART_IER, up->ier);936 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);937 938 serial_out(up, UART_EFR, up->efr);939 serial_out(up, UART_LCR, cval);940 941 if (!serial_omap_baud_is_mode16(port, baud))942 up->mdr1 = UART_OMAP_MDR1_13X_MODE;943 else944 up->mdr1 = UART_OMAP_MDR1_16X_MODE;945 946 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)947 serial_omap_mdr1_errataset(up, up->mdr1);948 else949 serial_out(up, UART_OMAP_MDR1, up->mdr1);950 951 /* Configure flow control */952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);953 954 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */955 serial_out(up, UART_XON1, termios->c_cc[VSTART]);956 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);957 958 /* Enable access to TCR/TLR */959 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);960 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);961 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);962 963 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);964 965 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);966 967 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {968 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */969 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;970 up->efr |= UART_EFR_CTS;971 } else {972 /* Disable AUTORTS and AUTOCTS */973 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);974 }975 976 if (up->port.flags & UPF_SOFT_FLOW) {977 /* clear SW control mode bits */978 up->efr &= OMAP_UART_SW_CLR;979 980 /*981 * IXON Flag:982 * Enable XON/XOFF flow control on input.983 * Receiver compares XON1, XOFF1.984 */985 if (termios->c_iflag & IXON)986 up->efr |= OMAP_UART_SW_RX;987 988 /*989 * IXOFF Flag:990 * Enable XON/XOFF flow control on output.991 * Transmit XON1, XOFF1992 */993 if (termios->c_iflag & IXOFF) {994 up->port.status |= UPSTAT_AUTOXOFF;995 up->efr |= OMAP_UART_SW_TX;996 }997 998 /*999 * IXANY Flag:1000 * Enable any character to restart output.1001 * Operation resumes after receiving any1002 * character after recognition of the XOFF character1003 */1004 if (termios->c_iflag & IXANY)1005 up->mcr |= UART_MCR_XONANY;1006 else1007 up->mcr &= ~UART_MCR_XONANY;1008 }1009 serial_out(up, UART_MCR, up->mcr);1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);1011 serial_out(up, UART_EFR, up->efr);1012 serial_out(up, UART_LCR, up->lcr);1013 1014 serial_omap_set_mctrl(&up->port, up->port.mctrl);1015 1016 uart_port_unlock_irqrestore(&up->port, flags);1017 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);1018}1019 1020static void1021serial_omap_pm(struct uart_port *port, unsigned int state,1022 unsigned int oldstate)1023{1024 struct uart_omap_port *up = to_uart_omap_port(port);1025 unsigned char efr;1026 1027 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);1028 1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);1030 efr = serial_in(up, UART_EFR);1031 serial_out(up, UART_EFR, efr | UART_EFR_ECB);1032 serial_out(up, UART_LCR, 0);1033 1034 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);1036 serial_out(up, UART_EFR, efr);1037 serial_out(up, UART_LCR, 0);1038}1039 1040static void serial_omap_release_port(struct uart_port *port)1041{1042 dev_dbg(port->dev, "serial_omap_release_port+\n");1043}1044 1045static int serial_omap_request_port(struct uart_port *port)1046{1047 dev_dbg(port->dev, "serial_omap_request_port+\n");1048 return 0;1049}1050 1051static void serial_omap_config_port(struct uart_port *port, int flags)1052{1053 struct uart_omap_port *up = to_uart_omap_port(port);1054 1055 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",1056 up->port.line);1057 up->port.type = PORT_OMAP;1058 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;1059}1060 1061static int1062serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)1063{1064 /* we don't want the core code to modify any port params */1065 dev_dbg(port->dev, "serial_omap_verify_port+\n");1066 return -EINVAL;1067}1068 1069static const char *1070serial_omap_type(struct uart_port *port)1071{1072 struct uart_omap_port *up = to_uart_omap_port(port);1073 1074 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);1075 return up->name;1076}1077 1078static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)1079{1080 unsigned int status, tmout = 10000;1081 1082 /* Wait up to 10ms for the character(s) to be sent. */1083 do {1084 status = serial_in(up, UART_LSR);1085 1086 if (status & UART_LSR_BI)1087 up->lsr_break_flag = UART_LSR_BI;1088 1089 if (--tmout == 0)1090 break;1091 udelay(1);1092 } while (!uart_lsr_tx_empty(status));1093 1094 /* Wait up to 1s for flow control if necessary */1095 if (up->port.flags & UPF_CONS_FLOW) {1096 for (tmout = 1000000; tmout; tmout--) {1097 unsigned int msr = serial_in(up, UART_MSR);1098 1099 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;1100 if (msr & UART_MSR_CTS)1101 break;1102 1103 udelay(1);1104 }1105 }1106}1107 1108#ifdef CONFIG_CONSOLE_POLL1109 1110static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)1111{1112 struct uart_omap_port *up = to_uart_omap_port(port);1113 1114 wait_for_xmitr(up);1115 serial_out(up, UART_TX, ch);1116}1117 1118static int serial_omap_poll_get_char(struct uart_port *port)1119{1120 struct uart_omap_port *up = to_uart_omap_port(port);1121 unsigned int status;1122 1123 status = serial_in(up, UART_LSR);1124 if (!(status & UART_LSR_DR)) {1125 status = NO_POLL_CHAR;1126 goto out;1127 }1128 1129 status = serial_in(up, UART_RX);1130 1131out:1132 return status;1133}1134 1135#endif /* CONFIG_CONSOLE_POLL */1136 1137#ifdef CONFIG_SERIAL_OMAP_CONSOLE1138 1139#ifdef CONFIG_SERIAL_EARLYCON1140static unsigned int omap_serial_early_in(struct uart_port *port, int offset)1141{1142 offset <<= port->regshift;1143 return readw(port->membase + offset);1144}1145 1146static void omap_serial_early_out(struct uart_port *port, int offset,1147 int value)1148{1149 offset <<= port->regshift;1150 writew(value, port->membase + offset);1151}1152 1153static void omap_serial_early_putc(struct uart_port *port, unsigned char c)1154{1155 unsigned int status;1156 1157 for (;;) {1158 status = omap_serial_early_in(port, UART_LSR);1159 if (uart_lsr_tx_empty(status))1160 break;1161 cpu_relax();1162 }1163 omap_serial_early_out(port, UART_TX, c);1164}1165 1166static void early_omap_serial_write(struct console *console, const char *s,1167 unsigned int count)1168{1169 struct earlycon_device *device = console->data;1170 struct uart_port *port = &device->port;1171 1172 uart_console_write(port, s, count, omap_serial_early_putc);1173}1174 1175static int __init early_omap_serial_setup(struct earlycon_device *device,1176 const char *options)1177{1178 struct uart_port *port = &device->port;1179 1180 if (!(device->port.membase || device->port.iobase))1181 return -ENODEV;1182 1183 port->regshift = 2;1184 device->con->write = early_omap_serial_write;1185 return 0;1186}1187 1188OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);1189OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);1190OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);1191#endif /* CONFIG_SERIAL_EARLYCON */1192 1193static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];1194 1195static struct uart_driver serial_omap_reg;1196 1197static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch)1198{1199 struct uart_omap_port *up = to_uart_omap_port(port);1200 1201 wait_for_xmitr(up);1202 serial_out(up, UART_TX, ch);1203}1204 1205static void1206serial_omap_console_write(struct console *co, const char *s,1207 unsigned int count)1208{1209 struct uart_omap_port *up = serial_omap_console_ports[co->index];1210 unsigned long flags;1211 unsigned int ier;1212 int locked = 1;1213 1214 if (oops_in_progress)1215 locked = uart_port_trylock_irqsave(&up->port, &flags);1216 else1217 uart_port_lock_irqsave(&up->port, &flags);1218 1219 /*1220 * First save the IER then disable the interrupts1221 */1222 ier = serial_in(up, UART_IER);1223 serial_out(up, UART_IER, 0);1224 1225 uart_console_write(&up->port, s, count, serial_omap_console_putchar);1226 1227 /*1228 * Finally, wait for transmitter to become empty1229 * and restore the IER1230 */1231 wait_for_xmitr(up);1232 serial_out(up, UART_IER, ier);1233 /*1234 * The receive handling will happen properly because the1235 * receive ready bit will still be set; it is not cleared1236 * on read. However, modem control will not, we must1237 * call it if we have saved something in the saved flags1238 * while processing with interrupts off.1239 */1240 if (up->msr_saved_flags)1241 check_modem_status(up);1242 1243 if (locked)1244 uart_port_unlock_irqrestore(&up->port, flags);1245}1246 1247static int __init1248serial_omap_console_setup(struct console *co, char *options)1249{1250 struct uart_omap_port *up;1251 int baud = 115200;1252 int bits = 8;1253 int parity = 'n';1254 int flow = 'n';1255 1256 if (serial_omap_console_ports[co->index] == NULL)1257 return -ENODEV;1258 up = serial_omap_console_ports[co->index];1259 1260 if (options)1261 uart_parse_options(options, &baud, &parity, &bits, &flow);1262 1263 return uart_set_options(&up->port, co, baud, parity, bits, flow);1264}1265 1266static struct console serial_omap_console = {1267 .name = OMAP_SERIAL_NAME,1268 .write = serial_omap_console_write,1269 .device = uart_console_device,1270 .setup = serial_omap_console_setup,1271 .flags = CON_PRINTBUFFER,1272 .index = -1,1273 .data = &serial_omap_reg,1274};1275 1276static void serial_omap_add_console_port(struct uart_omap_port *up)1277{1278 serial_omap_console_ports[up->port.line] = up;1279}1280 1281#define OMAP_CONSOLE (&serial_omap_console)1282 1283#else1284 1285#define OMAP_CONSOLE NULL1286 1287static inline void serial_omap_add_console_port(struct uart_omap_port *up)1288{}1289 1290#endif1291 1292/* Enable or disable the rs485 support */1293static int1294serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios,1295 struct serial_rs485 *rs485)1296{1297 struct uart_omap_port *up = to_uart_omap_port(port);1298 unsigned int mode;1299 int val;1300 1301 /* Disable interrupts from this port */1302 mode = up->ier;1303 up->ier = 0;1304 serial_out(up, UART_IER, 0);1305 1306 /* enable / disable rts */1307 val = (rs485->flags & SER_RS485_ENABLED) ?1308 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;1309 val = (rs485->flags & val) ? 1 : 0;1310 gpiod_set_value(up->rts_gpiod, val);1311 1312 /* Enable interrupts */1313 up->ier = mode;1314 serial_out(up, UART_IER, up->ier);1315 1316 /* If RS-485 is disabled, make sure the THR interrupt is fired when1317 * TX FIFO is below the trigger level.1318 */1319 if (!(rs485->flags & SER_RS485_ENABLED) &&1320 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {1321 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;1322 serial_out(up, UART_OMAP_SCR, up->scr);1323 }1324 1325 return 0;1326}1327 1328static const struct uart_ops serial_omap_pops = {1329 .tx_empty = serial_omap_tx_empty,1330 .set_mctrl = serial_omap_set_mctrl,1331 .get_mctrl = serial_omap_get_mctrl,1332 .stop_tx = serial_omap_stop_tx,1333 .start_tx = serial_omap_start_tx,1334 .throttle = serial_omap_throttle,1335 .unthrottle = serial_omap_unthrottle,1336 .stop_rx = serial_omap_stop_rx,1337 .enable_ms = serial_omap_enable_ms,1338 .break_ctl = serial_omap_break_ctl,1339 .startup = serial_omap_startup,1340 .shutdown = serial_omap_shutdown,1341 .set_termios = serial_omap_set_termios,1342 .pm = serial_omap_pm,1343 .type = serial_omap_type,1344 .release_port = serial_omap_release_port,1345 .request_port = serial_omap_request_port,1346 .config_port = serial_omap_config_port,1347 .verify_port = serial_omap_verify_port,1348#ifdef CONFIG_CONSOLE_POLL1349 .poll_put_char = serial_omap_poll_put_char,1350 .poll_get_char = serial_omap_poll_get_char,1351#endif1352};1353 1354static struct uart_driver serial_omap_reg = {1355 .owner = THIS_MODULE,1356 .driver_name = "OMAP-SERIAL",1357 .dev_name = OMAP_SERIAL_NAME,1358 .nr = OMAP_MAX_HSUART_PORTS,1359 .cons = OMAP_CONSOLE,1360};1361 1362#ifdef CONFIG_PM_SLEEP1363static int serial_omap_prepare(struct device *dev)1364{1365 struct uart_omap_port *up = dev_get_drvdata(dev);1366 1367 up->is_suspending = true;1368 1369 return 0;1370}1371 1372static void serial_omap_complete(struct device *dev)1373{1374 struct uart_omap_port *up = dev_get_drvdata(dev);1375 1376 up->is_suspending = false;1377}1378 1379static int serial_omap_suspend(struct device *dev)1380{1381 struct uart_omap_port *up = dev_get_drvdata(dev);1382 1383 uart_suspend_port(&serial_omap_reg, &up->port);1384 flush_work(&up->qos_work);1385 1386 if (device_may_wakeup(dev))1387 serial_omap_enable_wakeup(up, true);1388 else1389 serial_omap_enable_wakeup(up, false);1390 1391 return 0;1392}1393 1394static int serial_omap_resume(struct device *dev)1395{1396 struct uart_omap_port *up = dev_get_drvdata(dev);1397 1398 if (device_may_wakeup(dev))1399 serial_omap_enable_wakeup(up, false);1400 1401 uart_resume_port(&serial_omap_reg, &up->port);1402 1403 return 0;1404}1405#else1406#define serial_omap_prepare NULL1407#define serial_omap_complete NULL1408#endif /* CONFIG_PM_SLEEP */1409 1410static void omap_serial_fill_features_erratas(struct uart_omap_port *up)1411{1412 u32 mvr, scheme;1413 u16 revision, major, minor;1414 1415 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));1416 1417 /* Check revision register scheme */1418 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;1419 1420 switch (scheme) {1421 case 0: /* Legacy Scheme: OMAP2/3 */1422 /* MINOR_REV[0:4], MAJOR_REV[4:7] */1423 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>1424 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;1425 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);1426 break;1427 case 1:1428 /* New Scheme: OMAP4+ */1429 /* MINOR_REV[0:5], MAJOR_REV[8:10] */1430 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>1431 OMAP_UART_MVR_MAJ_SHIFT;1432 minor = (mvr & OMAP_UART_MVR_MIN_MASK);1433 break;1434 default:1435 dev_warn(up->dev,1436 "Unknown %s revision, defaulting to highest\n",1437 up->name);1438 /* highest possible revision */1439 major = 0xff;1440 minor = 0xff;1441 }1442 1443 /* normalize revision for the driver */1444 revision = UART_BUILD_REVISION(major, minor);1445 1446 switch (revision) {1447 case OMAP_UART_REV_46:1448 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |1449 UART_ERRATA_i291_DMA_FORCEIDLE);1450 break;1451 case OMAP_UART_REV_52:1452 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |1453 UART_ERRATA_i291_DMA_FORCEIDLE);1454 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;1455 break;1456 case OMAP_UART_REV_63:1457 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;1458 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;1459 break;1460 default:1461 break;1462 }1463}1464 1465static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)1466{1467 struct omap_uart_port_info *omap_up_info;1468 1469 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);1470 if (!omap_up_info)1471 return NULL; /* out of memory */1472 1473 of_property_read_u32(dev->of_node, "clock-frequency",1474 &omap_up_info->uartclk);1475 1476 omap_up_info->flags = UPF_BOOT_AUTOCONF;1477 1478 return omap_up_info;1479}1480 1481static const struct serial_rs485 serial_omap_rs485_supported = {1482 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |1483 SER_RS485_RX_DURING_TX,1484 .delay_rts_before_send = 1,1485 .delay_rts_after_send = 1,1486};1487 1488static int serial_omap_probe_rs485(struct uart_omap_port *up,1489 struct device *dev)1490{1491 struct serial_rs485 *rs485conf = &up->port.rs485;1492 struct device_node *np = dev->of_node;1493 enum gpiod_flags gflags;1494 int ret;1495 1496 rs485conf->flags = 0;1497 up->rts_gpiod = NULL;1498 1499 if (!np)1500 return 0;1501 1502 up->port.rs485_config = serial_omap_config_rs485;1503 up->port.rs485_supported = serial_omap_rs485_supported;1504 1505 ret = uart_get_rs485_mode(&up->port);1506 if (ret)1507 return ret;1508 1509 if (of_property_read_bool(np, "rs485-rts-active-high")) {1510 rs485conf->flags |= SER_RS485_RTS_ON_SEND;1511 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;1512 } else {1513 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;1514 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;1515 }1516 1517 /* check for tx enable gpio */1518 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?1519 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;1520 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);1521 if (IS_ERR(up->rts_gpiod)) {1522 ret = PTR_ERR(up->rts_gpiod);1523 if (ret == -EPROBE_DEFER)1524 return ret;1525 1526 up->rts_gpiod = NULL;1527 up->port.rs485_supported = (const struct serial_rs485) { };1528 if (rs485conf->flags & SER_RS485_ENABLED) {1529 dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n");1530 memset(rs485conf, 0, sizeof(*rs485conf));1531 }1532 } else {1533 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");1534 }1535 1536 return 0;1537}1538 1539static int serial_omap_probe(struct platform_device *pdev)1540{1541 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);1542 struct uart_omap_port *up;1543 struct resource *mem;1544 void __iomem *base;1545 int uartirq = 0;1546 int wakeirq = 0;1547 int ret;1548 1549 /* The optional wakeirq may be specified in the board dts file */1550 if (pdev->dev.of_node) {1551 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);1552 if (!uartirq)1553 return -EPROBE_DEFER;1554 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);1555 omap_up_info = of_get_uart_port_info(&pdev->dev);1556 pdev->dev.platform_data = omap_up_info;1557 } else {1558 uartirq = platform_get_irq(pdev, 0);1559 if (uartirq < 0)1560 return -EPROBE_DEFER;1561 }1562 1563 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);1564 if (!up)1565 return -ENOMEM;1566 1567 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);1568 if (IS_ERR(base))1569 return PTR_ERR(base);1570 1571 up->dev = &pdev->dev;1572 up->port.dev = &pdev->dev;1573 up->port.type = PORT_OMAP;1574 up->port.iotype = UPIO_MEM;1575 up->port.irq = uartirq;1576 up->port.regshift = 2;1577 up->port.fifosize = 64;1578 up->port.ops = &serial_omap_pops;1579 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);1580 1581 if (pdev->dev.of_node)1582 ret = of_alias_get_id(pdev->dev.of_node, "serial");1583 else1584 ret = pdev->id;1585 1586 if (ret < 0) {1587 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",1588 ret);1589 goto err_port_line;1590 }1591 up->port.line = ret;1592 1593 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {1594 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,1595 OMAP_MAX_HSUART_PORTS);1596 ret = -ENXIO;1597 goto err_port_line;1598 }1599 1600 up->wakeirq = wakeirq;1601 if (!up->wakeirq)1602 dev_info(up->port.dev, "no wakeirq for uart%d\n",1603 up->port.line);1604 1605 sprintf(up->name, "OMAP UART%d", up->port.line);1606 up->port.mapbase = mem->start;1607 up->port.membase = base;1608 up->port.flags = omap_up_info->flags;1609 up->port.uartclk = omap_up_info->uartclk;1610 if (!up->port.uartclk) {1611 up->port.uartclk = DEFAULT_CLK_SPEED;1612 dev_warn(&pdev->dev,1613 "No clock speed specified: using default: %d\n",1614 DEFAULT_CLK_SPEED);1615 }1616 1617 ret = serial_omap_probe_rs485(up, &pdev->dev);1618 if (ret < 0)1619 goto err_rs485;1620 1621 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;1622 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;1623 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);1624 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);1625 1626 platform_set_drvdata(pdev, up);1627 if (omap_up_info->autosuspend_timeout == 0)1628 omap_up_info->autosuspend_timeout = -1;1629 1630 device_init_wakeup(up->dev, true);1631 1632 pm_runtime_enable(&pdev->dev);1633 1634 pm_runtime_get_sync(&pdev->dev);1635 1636 omap_serial_fill_features_erratas(up);1637 1638 ui[up->port.line] = up;1639 serial_omap_add_console_port(up);1640 1641 ret = uart_add_one_port(&serial_omap_reg, &up->port);1642 if (ret != 0)1643 goto err_add_port;1644 1645 return 0;1646 1647err_add_port:1648 pm_runtime_put_sync(&pdev->dev);1649 pm_runtime_disable(&pdev->dev);1650 cpu_latency_qos_remove_request(&up->pm_qos_request);1651 device_init_wakeup(up->dev, false);1652err_rs485:1653err_port_line:1654 return ret;1655}1656 1657static void serial_omap_remove(struct platform_device *dev)1658{1659 struct uart_omap_port *up = platform_get_drvdata(dev);1660 1661 pm_runtime_get_sync(up->dev);1662 1663 uart_remove_one_port(&serial_omap_reg, &up->port);1664 1665 pm_runtime_put_sync(up->dev);1666 pm_runtime_disable(up->dev);1667 cpu_latency_qos_remove_request(&up->pm_qos_request);1668 device_init_wakeup(&dev->dev, false);1669}1670 1671/*1672 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)1673 * The access to uart register after MDR1 Access1674 * causes UART to corrupt data.1675 *1676 * Need a delay =1677 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)1678 * give 10 times as much1679 */1680static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)1681{1682 u8 timeout = 255;1683 1684 serial_out(up, UART_OMAP_MDR1, mdr1);1685 udelay(2);1686 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |1687 UART_FCR_CLEAR_RCVR);1688 /*1689 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and1690 * TX_FIFO_E bit is 1.1691 */1692 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &1693 (UART_LSR_THRE | UART_LSR_DR))) {1694 timeout--;1695 if (!timeout) {1696 /* Should *never* happen. we warn and carry on */1697 dev_crit(up->dev, "Errata i202: timedout %x\n",1698 serial_in(up, UART_LSR));1699 break;1700 }1701 udelay(1);1702 }1703}1704 1705#ifdef CONFIG_PM1706static void serial_omap_restore_context(struct uart_omap_port *up)1707{1708 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)1709 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);1710 else1711 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);1712 1713 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */1714 serial_out(up, UART_EFR, UART_EFR_ECB);1715 serial_out(up, UART_LCR, 0x0); /* Operational mode */1716 serial_out(up, UART_IER, 0x0);1717 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */1718 serial_out(up, UART_DLL, up->dll);1719 serial_out(up, UART_DLM, up->dlh);1720 serial_out(up, UART_LCR, 0x0); /* Operational mode */1721 serial_out(up, UART_IER, up->ier);1722 serial_out(up, UART_FCR, up->fcr);1723 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);1724 serial_out(up, UART_MCR, up->mcr);1725 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */1726 serial_out(up, UART_OMAP_SCR, up->scr);1727 serial_out(up, UART_EFR, up->efr);1728 serial_out(up, UART_LCR, up->lcr);1729 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)1730 serial_omap_mdr1_errataset(up, up->mdr1);1731 else1732 serial_out(up, UART_OMAP_MDR1, up->mdr1);1733 serial_out(up, UART_OMAP_WER, up->wer);1734}1735 1736static int serial_omap_runtime_suspend(struct device *dev)1737{1738 struct uart_omap_port *up = dev_get_drvdata(dev);1739 1740 if (!up)1741 return -EINVAL;1742 1743 /*1744 * When using 'no_console_suspend', the console UART must not be1745 * suspended. Since driver suspend is managed by runtime suspend,1746 * preventing runtime suspend (by returning error) will keep device1747 * active during suspend.1748 */1749 if (up->is_suspending && !console_suspend_enabled &&1750 uart_console(&up->port))1751 return -EBUSY;1752 1753 up->context_loss_cnt = serial_omap_get_context_loss_count(up);1754 1755 serial_omap_enable_wakeup(up, true);1756 1757 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;1758 schedule_work(&up->qos_work);1759 1760 return 0;1761}1762 1763static int serial_omap_runtime_resume(struct device *dev)1764{1765 struct uart_omap_port *up = dev_get_drvdata(dev);1766 1767 int loss_cnt = serial_omap_get_context_loss_count(up);1768 1769 serial_omap_enable_wakeup(up, false);1770 1771 if (loss_cnt < 0) {1772 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",1773 loss_cnt);1774 serial_omap_restore_context(up);1775 } else if (up->context_loss_cnt != loss_cnt) {1776 serial_omap_restore_context(up);1777 }1778 up->latency = up->calc_latency;1779 schedule_work(&up->qos_work);1780 1781 return 0;1782}1783#endif1784 1785static const struct dev_pm_ops serial_omap_dev_pm_ops = {1786 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)1787 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,1788 serial_omap_runtime_resume, NULL)1789 .prepare = serial_omap_prepare,1790 .complete = serial_omap_complete,1791};1792 1793#if defined(CONFIG_OF)1794static const struct of_device_id omap_serial_of_match[] = {1795 { .compatible = "ti,omap2-uart" },1796 { .compatible = "ti,omap3-uart" },1797 { .compatible = "ti,omap4-uart" },1798 {},1799};1800MODULE_DEVICE_TABLE(of, omap_serial_of_match);1801#endif1802 1803static struct platform_driver serial_omap_driver = {1804 .probe = serial_omap_probe,1805 .remove_new = serial_omap_remove,1806 .driver = {1807 .name = OMAP_SERIAL_DRIVER_NAME,1808 .pm = &serial_omap_dev_pm_ops,1809 .of_match_table = of_match_ptr(omap_serial_of_match),1810 },1811};1812 1813static int __init serial_omap_init(void)1814{1815 int ret;1816 1817 ret = uart_register_driver(&serial_omap_reg);1818 if (ret != 0)1819 return ret;1820 ret = platform_driver_register(&serial_omap_driver);1821 if (ret != 0)1822 uart_unregister_driver(&serial_omap_reg);1823 return ret;1824}1825 1826static void __exit serial_omap_exit(void)1827{1828 platform_driver_unregister(&serial_omap_driver);1829 uart_unregister_driver(&serial_omap_reg);1830}1831 1832module_init(serial_omap_init);1833module_exit(serial_omap_exit);1834 1835MODULE_DESCRIPTION("OMAP High Speed UART driver");1836MODULE_LICENSE("GPL");1837MODULE_AUTHOR("Texas Instruments Inc");1838