1882 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.4 */5#include <linux/kernel.h>6#include <linux/serial.h>7#include <linux/serial_reg.h>8#include <linux/slab.h>9#include <linux/module.h>10#include <linux/pci.h>11#include <linux/console.h>12#include <linux/serial_core.h>13#include <linux/tty.h>14#include <linux/tty_flip.h>15#include <linux/interrupt.h>16#include <linux/io.h>17#include <linux/dmi.h>18#include <linux/nmi.h>19#include <linux/delay.h>20#include <linux/of.h>21 22#include <linux/debugfs.h>23#include <linux/dmaengine.h>24#include <linux/pch_dma.h>25 26enum {27 PCH_UART_HANDLED_RX_INT_SHIFT,28 PCH_UART_HANDLED_TX_INT_SHIFT,29 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,30 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,31 PCH_UART_HANDLED_MS_INT_SHIFT,32 PCH_UART_HANDLED_LS_INT_SHIFT,33};34 35#define PCH_UART_DRIVER_DEVICE "ttyPCH"36 37/* Set the max number of UART port38 * Intel EG20T PCH: 4 port39 * LAPIS Semiconductor ML7213 IOH: 3 port40 * LAPIS Semiconductor ML7223 IOH: 2 port41*/42#define PCH_UART_NR 443 44#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))45#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))46#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\47 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))48#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\49 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))50#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))51 52#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))53 54#define PCH_UART_RBR 0x0055#define PCH_UART_THR 0x0056 57#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\58 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)59#define PCH_UART_IER_ERBFI 0x0000000160#define PCH_UART_IER_ETBEI 0x0000000261#define PCH_UART_IER_ELSI 0x0000000462#define PCH_UART_IER_EDSSI 0x0000000863 64#define PCH_UART_IIR_IP 0x0000000165#define PCH_UART_IIR_IID 0x0000000666#define PCH_UART_IIR_MSI 0x0000000067#define PCH_UART_IIR_TRI 0x0000000268#define PCH_UART_IIR_RRI 0x0000000469#define PCH_UART_IIR_REI 0x0000000670#define PCH_UART_IIR_TOI 0x0000000871#define PCH_UART_IIR_FIFO256 0x0000002072#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO25673#define PCH_UART_IIR_FE 0x000000C074 75#define PCH_UART_FCR_FIFOE 0x0000000176#define PCH_UART_FCR_RFR 0x0000000277#define PCH_UART_FCR_TFR 0x0000000478#define PCH_UART_FCR_DMS 0x0000000879#define PCH_UART_FCR_FIFO256 0x0000002080#define PCH_UART_FCR_RFTL 0x000000C081 82#define PCH_UART_FCR_RFTL1 0x0000000083#define PCH_UART_FCR_RFTL64 0x0000004084#define PCH_UART_FCR_RFTL128 0x0000008085#define PCH_UART_FCR_RFTL224 0x000000C086#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL6487#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL12888#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL22489#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL6490#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL12891#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL22492#define PCH_UART_FCR_RFTL_SHIFT 693 94#define PCH_UART_LCR_WLS 0x0000000395#define PCH_UART_LCR_STB 0x0000000496#define PCH_UART_LCR_PEN 0x0000000897#define PCH_UART_LCR_EPS 0x0000001098#define PCH_UART_LCR_SP 0x0000002099#define PCH_UART_LCR_SB 0x00000040100#define PCH_UART_LCR_DLAB 0x00000080101#define PCH_UART_LCR_NP 0x00000000102#define PCH_UART_LCR_OP PCH_UART_LCR_PEN103#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)104#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)105#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\106 PCH_UART_LCR_SP)107 108#define PCH_UART_LCR_5BIT 0x00000000109#define PCH_UART_LCR_6BIT 0x00000001110#define PCH_UART_LCR_7BIT 0x00000002111#define PCH_UART_LCR_8BIT 0x00000003112 113#define PCH_UART_MCR_DTR 0x00000001114#define PCH_UART_MCR_RTS 0x00000002115#define PCH_UART_MCR_OUT 0x0000000C116#define PCH_UART_MCR_LOOP 0x00000010117#define PCH_UART_MCR_AFE 0x00000020118 119#define PCH_UART_LSR_DR 0x00000001120#define PCH_UART_LSR_ERR (1<<7)121 122#define PCH_UART_MSR_DCTS 0x00000001123#define PCH_UART_MSR_DDSR 0x00000002124#define PCH_UART_MSR_TERI 0x00000004125#define PCH_UART_MSR_DDCD 0x00000008126#define PCH_UART_MSR_CTS 0x00000010127#define PCH_UART_MSR_DSR 0x00000020128#define PCH_UART_MSR_RI 0x00000040129#define PCH_UART_MSR_DCD 0x00000080130#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\131 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)132 133#define PCH_UART_DLL 0x00134#define PCH_UART_DLM 0x01135 136#define PCH_UART_BRCSR 0x0E137 138#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)139#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)140#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)141#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)142#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)143 144#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)145#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)146#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)147#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)148#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)149#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)150#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)151#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)152#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)153#define PCH_UART_HAL_STB1 0154#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)155 156#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)157#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)158#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \159 PCH_UART_HAL_CLR_RX_FIFO)160 161#define PCH_UART_HAL_DMA_MODE0 0162#define PCH_UART_HAL_FIFO_DIS 0163#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)164#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \165 PCH_UART_FCR_FIFO256)166#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)167#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)168#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)169#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)170#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)171#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)172#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)173#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)174#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)175#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)176#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)177#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)178#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)179#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)180 181#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)182#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)183#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)184#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)185#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)186 187#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)188#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)189#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)190#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)191#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)192 193#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */194#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */195#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */196#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */197#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */198#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */199 200struct pch_uart_buffer {201 unsigned char *buf;202 int size;203};204 205struct eg20t_port {206 struct uart_port port;207 int port_type;208 void __iomem *membase;209 resource_size_t mapbase;210 unsigned int iobase;211 struct pci_dev *pdev;212 int fifo_size;213 unsigned int uartclk;214 int start_tx;215 int start_rx;216 int tx_empty;217 int trigger;218 int trigger_level;219 struct pch_uart_buffer rxbuf;220 unsigned int dmsr;221 unsigned int fcr;222 unsigned int mcr;223 unsigned int use_dma;224 struct dma_async_tx_descriptor *desc_tx;225 struct dma_async_tx_descriptor *desc_rx;226 struct pch_dma_slave param_tx;227 struct pch_dma_slave param_rx;228 struct dma_chan *chan_tx;229 struct dma_chan *chan_rx;230 struct scatterlist *sg_tx_p;231 int nent;232 int orig_nent;233 struct scatterlist sg_rx;234 int tx_dma_use;235 void *rx_buf_virt;236 dma_addr_t rx_buf_dma;237 238#define IRQ_NAME_SIZE 17239 char irq_name[IRQ_NAME_SIZE];240};241 242/**243 * struct pch_uart_driver_data - private data structure for UART-DMA244 * @port_type: The type of UART port245 * @line_no: UART port line number (0, 1, 2...)246 */247struct pch_uart_driver_data {248 int port_type;249 int line_no;250};251 252enum pch_uart_num_t {253 pch_et20t_uart0 = 0,254 pch_et20t_uart1,255 pch_et20t_uart2,256 pch_et20t_uart3,257 pch_ml7213_uart0,258 pch_ml7213_uart1,259 pch_ml7213_uart2,260 pch_ml7223_uart0,261 pch_ml7223_uart1,262 pch_ml7831_uart0,263 pch_ml7831_uart1,264};265 266static struct pch_uart_driver_data drv_dat[] = {267 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},268 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},269 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},270 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},271 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},272 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},273 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},274 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},275 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},276 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},277 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},278};279 280#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE281static struct eg20t_port *pch_uart_ports[PCH_UART_NR];282#endif283static unsigned int default_baud = 9600;284static unsigned int user_uartclk = 0;285static const int trigger_level_256[4] = { 1, 64, 128, 224 };286static const int trigger_level_64[4] = { 1, 16, 32, 56 };287static const int trigger_level_16[4] = { 1, 4, 8, 14 };288static const int trigger_level_1[4] = { 1, 1, 1, 1 };289 290#define PCH_REGS_BUFSIZE 1024291 292 293static ssize_t port_show_regs(struct file *file, char __user *user_buf,294 size_t count, loff_t *ppos)295{296 struct eg20t_port *priv = file->private_data;297 char *buf;298 u32 len = 0;299 ssize_t ret;300 unsigned char lcr;301 302 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);303 if (!buf)304 return 0;305 306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,307 "PCH EG20T port[%d] regs:\n", priv->port.line);308 309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,310 "=================================\n");311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,324 "BRCSR: \t0x%02x\n",325 ioread8(priv->membase + PCH_UART_BRCSR));326 327 lcr = ioread8(priv->membase + UART_LCR);328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,330 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));331 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,332 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));333 iowrite8(lcr, priv->membase + UART_LCR);334 335 if (len > PCH_REGS_BUFSIZE)336 len = PCH_REGS_BUFSIZE;337 338 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);339 kfree(buf);340 return ret;341}342 343static const struct file_operations port_regs_ops = {344 .owner = THIS_MODULE,345 .open = simple_open,346 .read = port_show_regs,347 .llseek = default_llseek,348};349 350static const struct dmi_system_id pch_uart_dmi_table[] = {351 {352 .ident = "CM-iTC",353 {354 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),355 },356 (void *)CMITC_UARTCLK,357 },358 {359 .ident = "FRI2",360 {361 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),362 },363 (void *)FRI2_64_UARTCLK,364 },365 {366 .ident = "Fish River Island II",367 {368 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),369 },370 (void *)FRI2_48_UARTCLK,371 },372 {373 .ident = "COMe-mTT",374 {375 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),376 },377 (void *)NTC1_UARTCLK,378 },379 {380 .ident = "nanoETXexpress-TT",381 {382 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),383 },384 (void *)NTC1_UARTCLK,385 },386 {387 .ident = "MinnowBoard",388 {389 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),390 },391 (void *)MINNOW_UARTCLK,392 },393 { }394};395 396/* Return UART clock, checking for board specific clocks. */397static unsigned int pch_uart_get_uartclk(void)398{399 const struct dmi_system_id *d;400 401 if (user_uartclk)402 return user_uartclk;403 404 d = dmi_first_match(pch_uart_dmi_table);405 if (d)406 return (unsigned long)d->driver_data;407 408 return DEFAULT_UARTCLK;409}410 411static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,412 unsigned int flag)413{414 u8 ier = ioread8(priv->membase + UART_IER);415 ier |= flag & PCH_UART_IER_MASK;416 iowrite8(ier, priv->membase + UART_IER);417}418 419static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,420 unsigned int flag)421{422 u8 ier = ioread8(priv->membase + UART_IER);423 ier &= ~(flag & PCH_UART_IER_MASK);424 iowrite8(ier, priv->membase + UART_IER);425}426 427static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,428 unsigned int parity, unsigned int bits,429 unsigned int stb)430{431 unsigned int dll, dlm, lcr;432 int div;433 434 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);435 if (div < 0 || USHRT_MAX <= div) {436 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);437 return -EINVAL;438 }439 440 dll = (unsigned int)div & 0x00FFU;441 dlm = ((unsigned int)div >> 8) & 0x00FFU;442 443 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {444 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);445 return -EINVAL;446 }447 448 if (bits & ~PCH_UART_LCR_WLS) {449 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);450 return -EINVAL;451 }452 453 if (stb & ~PCH_UART_LCR_STB) {454 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);455 return -EINVAL;456 }457 458 lcr = parity;459 lcr |= bits;460 lcr |= stb;461 462 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",463 __func__, baud, div, lcr, jiffies);464 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);465 iowrite8(dll, priv->membase + PCH_UART_DLL);466 iowrite8(dlm, priv->membase + PCH_UART_DLM);467 iowrite8(lcr, priv->membase + UART_LCR);468 469 return 0;470}471 472static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,473 unsigned int flag)474{475 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {476 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",477 __func__, flag);478 return -EINVAL;479 }480 481 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);482 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,483 priv->membase + UART_FCR);484 iowrite8(priv->fcr, priv->membase + UART_FCR);485 486 return 0;487}488 489static int pch_uart_hal_set_fifo(struct eg20t_port *priv,490 unsigned int dmamode,491 unsigned int fifo_size, unsigned int trigger)492{493 u8 fcr;494 495 if (dmamode & ~PCH_UART_FCR_DMS) {496 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",497 __func__, dmamode);498 return -EINVAL;499 }500 501 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {502 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",503 __func__, fifo_size);504 return -EINVAL;505 }506 507 if (trigger & ~PCH_UART_FCR_RFTL) {508 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",509 __func__, trigger);510 return -EINVAL;511 }512 513 switch (priv->fifo_size) {514 case 256:515 priv->trigger_level =516 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];517 break;518 case 64:519 priv->trigger_level =520 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];521 break;522 case 16:523 priv->trigger_level =524 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];525 break;526 default:527 priv->trigger_level =528 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];529 break;530 }531 fcr =532 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;533 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);534 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,535 priv->membase + UART_FCR);536 iowrite8(fcr, priv->membase + UART_FCR);537 priv->fcr = fcr;538 539 return 0;540}541 542static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)543{544 unsigned int msr = ioread8(priv->membase + UART_MSR);545 priv->dmsr = msr & PCH_UART_MSR_DELTA;546 return (u8)msr;547}548 549static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,550 int rx_size)551{552 int i;553 u8 rbr, lsr;554 struct uart_port *port = &priv->port;555 556 lsr = ioread8(priv->membase + UART_LSR);557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);558 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);559 lsr = ioread8(priv->membase + UART_LSR)) {560 rbr = ioread8(priv->membase + PCH_UART_RBR);561 562 if (lsr & UART_LSR_BI) {563 port->icount.brk++;564 if (uart_handle_break(port))565 continue;566 }567 if (uart_prepare_sysrq_char(port, rbr))568 continue;569 570 buf[i++] = rbr;571 }572 return i;573}574 575static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)576{577 return ioread8(priv->membase + UART_IIR) &\578 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);579}580 581static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)582{583 return ioread8(priv->membase + UART_LSR);584}585 586static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)587{588 unsigned int lcr;589 590 lcr = ioread8(priv->membase + UART_LCR);591 if (on)592 lcr |= PCH_UART_LCR_SB;593 else594 lcr &= ~PCH_UART_LCR_SB;595 596 iowrite8(lcr, priv->membase + UART_LCR);597}598 599static void push_rx(struct eg20t_port *priv, const unsigned char *buf,600 int size)601{602 struct uart_port *port = &priv->port;603 struct tty_port *tport = &port->state->port;604 605 tty_insert_flip_string(tport, buf, size);606 tty_flip_buffer_push(tport);607}608 609static int dma_push_rx(struct eg20t_port *priv, int size)610{611 int room;612 struct uart_port *port = &priv->port;613 struct tty_port *tport = &port->state->port;614 615 room = tty_buffer_request_room(tport, size);616 617 if (room < size)618 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",619 size - room);620 if (!room)621 return 0;622 623 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);624 625 port->icount.rx += room;626 627 return room;628}629 630static void pch_free_dma(struct uart_port *port)631{632 struct eg20t_port *priv;633 priv = container_of(port, struct eg20t_port, port);634 635 if (priv->chan_tx) {636 dma_release_channel(priv->chan_tx);637 priv->chan_tx = NULL;638 }639 if (priv->chan_rx) {640 dma_release_channel(priv->chan_rx);641 priv->chan_rx = NULL;642 }643 644 if (priv->rx_buf_dma) {645 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,646 priv->rx_buf_dma);647 priv->rx_buf_virt = NULL;648 priv->rx_buf_dma = 0;649 }650 651 return;652}653 654static bool filter(struct dma_chan *chan, void *slave)655{656 struct pch_dma_slave *param = slave;657 658 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==659 chan->device->dev)) {660 chan->private = param;661 return true;662 } else {663 return false;664 }665}666 667static void pch_request_dma(struct uart_port *port)668{669 dma_cap_mask_t mask;670 struct dma_chan *chan;671 struct pci_dev *dma_dev;672 struct pch_dma_slave *param;673 struct eg20t_port *priv =674 container_of(port, struct eg20t_port, port);675 dma_cap_zero(mask);676 dma_cap_set(DMA_SLAVE, mask);677 678 /* Get DMA's dev information */679 dma_dev = pci_get_slot(priv->pdev->bus,680 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));681 682 /* Set Tx DMA */683 param = &priv->param_tx;684 param->dma_dev = &dma_dev->dev;685 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */686 687 param->tx_reg = port->mapbase + UART_TX;688 chan = dma_request_channel(mask, filter, param);689 if (!chan) {690 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",691 __func__);692 pci_dev_put(dma_dev);693 return;694 }695 priv->chan_tx = chan;696 697 /* Set Rx DMA */698 param = &priv->param_rx;699 param->dma_dev = &dma_dev->dev;700 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */701 702 param->rx_reg = port->mapbase + UART_RX;703 chan = dma_request_channel(mask, filter, param);704 if (!chan) {705 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",706 __func__);707 dma_release_channel(priv->chan_tx);708 priv->chan_tx = NULL;709 pci_dev_put(dma_dev);710 return;711 }712 713 /* Get Consistent memory for DMA */714 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,715 &priv->rx_buf_dma, GFP_KERNEL);716 priv->chan_rx = chan;717 718 pci_dev_put(dma_dev);719}720 721static void pch_dma_rx_complete(void *arg)722{723 struct eg20t_port *priv = arg;724 struct uart_port *port = &priv->port;725 int count;726 727 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);728 count = dma_push_rx(priv, priv->trigger_level);729 if (count)730 tty_flip_buffer_push(&port->state->port);731 async_tx_ack(priv->desc_rx);732 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |733 PCH_UART_HAL_RX_ERR_INT);734}735 736static void pch_dma_tx_complete(void *arg)737{738 struct eg20t_port *priv = arg;739 struct uart_port *port = &priv->port;740 struct scatterlist *sg = priv->sg_tx_p;741 int i;742 743 for (i = 0; i < priv->nent; i++, sg++)744 uart_xmit_advance(port, sg_dma_len(sg));745 746 async_tx_ack(priv->desc_tx);747 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);748 priv->tx_dma_use = 0;749 priv->nent = 0;750 priv->orig_nent = 0;751 kfree(priv->sg_tx_p);752 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);753}754 755static int handle_rx_to(struct eg20t_port *priv)756{757 struct pch_uart_buffer *buf;758 int rx_size;759 760 if (!priv->start_rx) {761 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |762 PCH_UART_HAL_RX_ERR_INT);763 return 0;764 }765 buf = &priv->rxbuf;766 do {767 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);768 push_rx(priv, buf->buf, rx_size);769 } while (rx_size == buf->size);770 771 return PCH_UART_HANDLED_RX_INT;772}773 774static int dma_handle_rx(struct eg20t_port *priv)775{776 struct uart_port *port = &priv->port;777 struct dma_async_tx_descriptor *desc;778 struct scatterlist *sg;779 780 priv = container_of(port, struct eg20t_port, port);781 sg = &priv->sg_rx;782 783 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */784 785 sg_dma_len(sg) = priv->trigger_level;786 787 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),788 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));789 790 sg_dma_address(sg) = priv->rx_buf_dma;791 792 desc = dmaengine_prep_slave_sg(priv->chan_rx,793 sg, 1, DMA_DEV_TO_MEM,794 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);795 796 if (!desc)797 return 0;798 799 priv->desc_rx = desc;800 desc->callback = pch_dma_rx_complete;801 desc->callback_param = priv;802 desc->tx_submit(desc);803 dma_async_issue_pending(priv->chan_rx);804 805 return PCH_UART_HANDLED_RX_INT;806}807 808static unsigned int handle_tx(struct eg20t_port *priv)809{810 struct uart_port *port = &priv->port;811 unsigned char ch;812 int fifo_size;813 int tx_empty;814 815 if (!priv->start_tx) {816 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",817 __func__, jiffies);818 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);819 priv->tx_empty = 1;820 return 0;821 }822 823 fifo_size = max(priv->fifo_size, 1);824 tx_empty = 1;825 if (port->x_char) {826 iowrite8(port->x_char, priv->membase + PCH_UART_THR);827 port->icount.tx++;828 port->x_char = 0;829 tx_empty = 0;830 fifo_size--;831 }832 833 while (!uart_tx_stopped(port) && fifo_size &&834 uart_fifo_get(port, &ch)) {835 iowrite8(ch, priv->membase + PCH_UART_THR);836 fifo_size--;837 tx_empty = 0;838 }839 840 priv->tx_empty = tx_empty;841 842 if (tx_empty) {843 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);844 uart_write_wakeup(port);845 }846 847 return PCH_UART_HANDLED_TX_INT;848}849 850static unsigned int dma_handle_tx(struct eg20t_port *priv)851{852 struct uart_port *port = &priv->port;853 struct tty_port *tport = &port->state->port;854 struct scatterlist *sg;855 int nent;856 int fifo_size;857 struct dma_async_tx_descriptor *desc;858 unsigned int bytes, tail;859 int num;860 int i;861 int size;862 int rem;863 864 if (!priv->start_tx) {865 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",866 __func__, jiffies);867 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);868 priv->tx_empty = 1;869 return 0;870 }871 872 if (priv->tx_dma_use) {873 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",874 __func__, jiffies);875 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);876 priv->tx_empty = 1;877 return 0;878 }879 880 fifo_size = max(priv->fifo_size, 1);881 882 if (port->x_char) {883 iowrite8(port->x_char, priv->membase + PCH_UART_THR);884 port->icount.tx++;885 port->x_char = 0;886 fifo_size--;887 }888 889 bytes = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE);890 if (!bytes) {891 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);892 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);893 uart_write_wakeup(port);894 return 0;895 }896 897 if (bytes > fifo_size) {898 num = bytes / fifo_size + 1;899 size = fifo_size;900 rem = bytes % fifo_size;901 } else {902 num = 1;903 size = bytes;904 rem = bytes;905 }906 907 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",908 __func__, num, size, rem);909 910 priv->tx_dma_use = 1;911 912 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);913 if (!priv->sg_tx_p) {914 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);915 return 0;916 }917 918 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */919 sg = priv->sg_tx_p;920 921 for (i = 0; i < num; i++, sg++) {922 if (i == (num - 1))923 sg_set_page(sg, virt_to_page(tport->xmit_buf),924 rem, fifo_size * i);925 else926 sg_set_page(sg, virt_to_page(tport->xmit_buf),927 size, fifo_size * i);928 }929 930 sg = priv->sg_tx_p;931 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);932 if (!nent) {933 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);934 return 0;935 }936 priv->orig_nent = num;937 priv->nent = nent;938 939 for (i = 0; i < nent; i++, sg++) {940 sg->offset = tail + fifo_size * i;941 sg_dma_address(sg) = (sg_dma_address(sg) &942 ~(UART_XMIT_SIZE - 1)) + sg->offset;943 if (i == (nent - 1))944 sg_dma_len(sg) = rem;945 else946 sg_dma_len(sg) = size;947 }948 949 desc = dmaengine_prep_slave_sg(priv->chan_tx,950 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,951 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);952 if (!desc) {953 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",954 __func__);955 return 0;956 }957 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);958 priv->desc_tx = desc;959 desc->callback = pch_dma_tx_complete;960 desc->callback_param = priv;961 962 desc->tx_submit(desc);963 964 dma_async_issue_pending(priv->chan_tx);965 966 return PCH_UART_HANDLED_TX_INT;967}968 969static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)970{971 struct uart_port *port = &priv->port;972 struct tty_struct *tty = tty_port_tty_get(&port->state->port);973 char *error_msg[5] = {};974 int i = 0;975 976 if (lsr & PCH_UART_LSR_ERR)977 error_msg[i++] = "Error data in FIFO\n";978 979 if (lsr & UART_LSR_FE) {980 port->icount.frame++;981 error_msg[i++] = " Framing Error\n";982 }983 984 if (lsr & UART_LSR_PE) {985 port->icount.parity++;986 error_msg[i++] = " Parity Error\n";987 }988 989 if (lsr & UART_LSR_OE) {990 port->icount.overrun++;991 error_msg[i++] = " Overrun Error\n";992 }993 994 if (tty == NULL) {995 for (i = 0; error_msg[i] != NULL; i++)996 dev_err(&priv->pdev->dev, error_msg[i]);997 } else {998 tty_kref_put(tty);999 }1000}1001 1002static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)1003{1004 struct eg20t_port *priv = dev_id;1005 unsigned int handled;1006 u8 lsr;1007 int ret = 0;1008 unsigned char iid;1009 int next = 1;1010 u8 msr;1011 1012 uart_port_lock(&priv->port);1013 handled = 0;1014 while (next) {1015 iid = pch_uart_hal_get_iid(priv);1016 if (iid & PCH_UART_IIR_IP) /* No Interrupt */1017 break;1018 switch (iid) {1019 case PCH_UART_IID_RLS: /* Receiver Line Status */1020 lsr = pch_uart_hal_get_line_status(priv);1021 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |1022 UART_LSR_PE | UART_LSR_OE)) {1023 pch_uart_err_ir(priv, lsr);1024 ret = PCH_UART_HANDLED_RX_ERR_INT;1025 } else {1026 ret = PCH_UART_HANDLED_LS_INT;1027 }1028 break;1029 case PCH_UART_IID_RDR: /* Received Data Ready */1030 if (priv->use_dma) {1031 pch_uart_hal_disable_interrupt(priv,1032 PCH_UART_HAL_RX_INT |1033 PCH_UART_HAL_RX_ERR_INT);1034 ret = dma_handle_rx(priv);1035 if (!ret)1036 pch_uart_hal_enable_interrupt(priv,1037 PCH_UART_HAL_RX_INT |1038 PCH_UART_HAL_RX_ERR_INT);1039 } else {1040 ret = handle_rx_to(priv);1041 }1042 break;1043 case PCH_UART_IID_RDR_TO: /* Received Data Ready1044 (FIFO Timeout) */1045 ret = handle_rx_to(priv);1046 break;1047 case PCH_UART_IID_THRE: /* Transmitter Holding Register1048 Empty */1049 if (priv->use_dma)1050 ret = dma_handle_tx(priv);1051 else1052 ret = handle_tx(priv);1053 break;1054 case PCH_UART_IID_MS: /* Modem Status */1055 msr = pch_uart_hal_get_modem(priv);1056 next = 0; /* MS ir prioirty is the lowest. So, MS ir1057 means final interrupt */1058 if ((msr & UART_MSR_ANY_DELTA) == 0)1059 break;1060 ret |= PCH_UART_HANDLED_MS_INT;1061 break;1062 default: /* Never junp to this label */1063 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,1064 iid, jiffies);1065 ret = -1;1066 next = 0;1067 break;1068 }1069 handled |= (unsigned int)ret;1070 }1071 1072 uart_unlock_and_check_sysrq(&priv->port);1073 return IRQ_RETVAL(handled);1074}1075 1076/* This function tests whether the transmitter fifo and shifter for the port1077 described by 'port' is empty. */1078static unsigned int pch_uart_tx_empty(struct uart_port *port)1079{1080 struct eg20t_port *priv;1081 1082 priv = container_of(port, struct eg20t_port, port);1083 if (priv->tx_empty)1084 return TIOCSER_TEMT;1085 else1086 return 0;1087}1088 1089/* Returns the current state of modem control inputs. */1090static unsigned int pch_uart_get_mctrl(struct uart_port *port)1091{1092 struct eg20t_port *priv;1093 u8 modem;1094 unsigned int ret = 0;1095 1096 priv = container_of(port, struct eg20t_port, port);1097 modem = pch_uart_hal_get_modem(priv);1098 1099 if (modem & UART_MSR_DCD)1100 ret |= TIOCM_CAR;1101 1102 if (modem & UART_MSR_RI)1103 ret |= TIOCM_RNG;1104 1105 if (modem & UART_MSR_DSR)1106 ret |= TIOCM_DSR;1107 1108 if (modem & UART_MSR_CTS)1109 ret |= TIOCM_CTS;1110 1111 return ret;1112}1113 1114static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)1115{1116 u32 mcr = 0;1117 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);1118 1119 if (mctrl & TIOCM_DTR)1120 mcr |= UART_MCR_DTR;1121 if (mctrl & TIOCM_RTS)1122 mcr |= UART_MCR_RTS;1123 if (mctrl & TIOCM_LOOP)1124 mcr |= UART_MCR_LOOP;1125 1126 if (priv->mcr & UART_MCR_AFE)1127 mcr |= UART_MCR_AFE;1128 1129 if (mctrl)1130 iowrite8(mcr, priv->membase + UART_MCR);1131}1132 1133static void pch_uart_stop_tx(struct uart_port *port)1134{1135 struct eg20t_port *priv;1136 priv = container_of(port, struct eg20t_port, port);1137 priv->start_tx = 0;1138 priv->tx_dma_use = 0;1139}1140 1141static void pch_uart_start_tx(struct uart_port *port)1142{1143 struct eg20t_port *priv;1144 1145 priv = container_of(port, struct eg20t_port, port);1146 1147 if (priv->use_dma) {1148 if (priv->tx_dma_use) {1149 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",1150 __func__);1151 return;1152 }1153 }1154 1155 priv->start_tx = 1;1156 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);1157}1158 1159static void pch_uart_stop_rx(struct uart_port *port)1160{1161 struct eg20t_port *priv;1162 priv = container_of(port, struct eg20t_port, port);1163 priv->start_rx = 0;1164 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |1165 PCH_UART_HAL_RX_ERR_INT);1166}1167 1168/* Enable the modem status interrupts. */1169static void pch_uart_enable_ms(struct uart_port *port)1170{1171 struct eg20t_port *priv;1172 priv = container_of(port, struct eg20t_port, port);1173 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);1174}1175 1176/* Control the transmission of a break signal. */1177static void pch_uart_break_ctl(struct uart_port *port, int ctl)1178{1179 struct eg20t_port *priv;1180 unsigned long flags;1181 1182 priv = container_of(port, struct eg20t_port, port);1183 uart_port_lock_irqsave(&priv->port, &flags);1184 pch_uart_hal_set_break(priv, ctl);1185 uart_port_unlock_irqrestore(&priv->port, flags);1186}1187 1188/* Grab any interrupt resources and initialise any low level driver state. */1189static int pch_uart_startup(struct uart_port *port)1190{1191 struct eg20t_port *priv;1192 int ret;1193 int fifo_size;1194 int trigger_level;1195 1196 priv = container_of(port, struct eg20t_port, port);1197 priv->tx_empty = 1;1198 1199 if (port->uartclk)1200 priv->uartclk = port->uartclk;1201 else1202 port->uartclk = priv->uartclk;1203 1204 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);1205 ret = pch_uart_hal_set_line(priv, default_baud,1206 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,1207 PCH_UART_HAL_STB1);1208 if (ret)1209 return ret;1210 1211 switch (priv->fifo_size) {1212 case 256:1213 fifo_size = PCH_UART_HAL_FIFO256;1214 break;1215 case 64:1216 fifo_size = PCH_UART_HAL_FIFO64;1217 break;1218 case 16:1219 fifo_size = PCH_UART_HAL_FIFO16;1220 break;1221 case 1:1222 default:1223 fifo_size = PCH_UART_HAL_FIFO_DIS;1224 break;1225 }1226 1227 switch (priv->trigger) {1228 case PCH_UART_HAL_TRIGGER1:1229 trigger_level = 1;1230 break;1231 case PCH_UART_HAL_TRIGGER_L:1232 trigger_level = priv->fifo_size / 4;1233 break;1234 case PCH_UART_HAL_TRIGGER_M:1235 trigger_level = priv->fifo_size / 2;1236 break;1237 case PCH_UART_HAL_TRIGGER_H:1238 default:1239 trigger_level = priv->fifo_size - (priv->fifo_size / 8);1240 break;1241 }1242 1243 priv->trigger_level = trigger_level;1244 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,1245 fifo_size, priv->trigger);1246 if (ret < 0)1247 return ret;1248 1249 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,1250 priv->irq_name, priv);1251 if (ret < 0)1252 return ret;1253 1254 if (priv->use_dma)1255 pch_request_dma(port);1256 1257 priv->start_rx = 1;1258 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |1259 PCH_UART_HAL_RX_ERR_INT);1260 uart_update_timeout(port, CS8, default_baud);1261 1262 return 0;1263}1264 1265static void pch_uart_shutdown(struct uart_port *port)1266{1267 struct eg20t_port *priv;1268 int ret;1269 1270 priv = container_of(port, struct eg20t_port, port);1271 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);1272 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);1273 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,1274 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);1275 if (ret)1276 dev_err(priv->port.dev,1277 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);1278 1279 pch_free_dma(port);1280 1281 free_irq(priv->port.irq, priv);1282}1283 1284/* Change the port parameters, including word length, parity, stop1285 *bits. Update read_status_mask and ignore_status_mask to indicate1286 *the types of events we are interested in receiving. */1287static void pch_uart_set_termios(struct uart_port *port,1288 struct ktermios *termios,1289 const struct ktermios *old)1290{1291 int rtn;1292 unsigned int baud, parity, bits, stb;1293 struct eg20t_port *priv;1294 unsigned long flags;1295 1296 priv = container_of(port, struct eg20t_port, port);1297 switch (termios->c_cflag & CSIZE) {1298 case CS5:1299 bits = PCH_UART_HAL_5BIT;1300 break;1301 case CS6:1302 bits = PCH_UART_HAL_6BIT;1303 break;1304 case CS7:1305 bits = PCH_UART_HAL_7BIT;1306 break;1307 default: /* CS8 */1308 bits = PCH_UART_HAL_8BIT;1309 break;1310 }1311 if (termios->c_cflag & CSTOPB)1312 stb = PCH_UART_HAL_STB2;1313 else1314 stb = PCH_UART_HAL_STB1;1315 1316 if (termios->c_cflag & PARENB) {1317 if (termios->c_cflag & PARODD)1318 parity = PCH_UART_HAL_PARITY_ODD;1319 else1320 parity = PCH_UART_HAL_PARITY_EVEN;1321 1322 } else1323 parity = PCH_UART_HAL_PARITY_NONE;1324 1325 /* Only UART0 has auto hardware flow function */1326 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))1327 priv->mcr |= UART_MCR_AFE;1328 else1329 priv->mcr &= ~UART_MCR_AFE;1330 1331 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */1332 1333 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);1334 1335 uart_port_lock_irqsave(port, &flags);1336 1337 uart_update_timeout(port, termios->c_cflag, baud);1338 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);1339 if (rtn)1340 goto out;1341 1342 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);1343 /* Don't rewrite B0 */1344 if (tty_termios_baud_rate(termios))1345 tty_termios_encode_baud_rate(termios, baud, baud);1346 1347out:1348 uart_port_unlock_irqrestore(port, flags);1349}1350 1351static const char *pch_uart_type(struct uart_port *port)1352{1353 return KBUILD_MODNAME;1354}1355 1356static void pch_uart_release_port(struct uart_port *port)1357{1358 struct eg20t_port *priv;1359 1360 priv = container_of(port, struct eg20t_port, port);1361 pci_iounmap(priv->pdev, priv->membase);1362 pci_release_regions(priv->pdev);1363}1364 1365static int pch_uart_request_port(struct uart_port *port)1366{1367 struct eg20t_port *priv;1368 int ret;1369 void __iomem *membase;1370 1371 priv = container_of(port, struct eg20t_port, port);1372 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);1373 if (ret < 0)1374 return -EBUSY;1375 1376 membase = pci_iomap(priv->pdev, 1, 0);1377 if (!membase) {1378 pci_release_regions(priv->pdev);1379 return -EBUSY;1380 }1381 priv->membase = port->membase = membase;1382 1383 return 0;1384}1385 1386static void pch_uart_config_port(struct uart_port *port, int type)1387{1388 struct eg20t_port *priv;1389 1390 priv = container_of(port, struct eg20t_port, port);1391 if (type & UART_CONFIG_TYPE) {1392 port->type = priv->port_type;1393 pch_uart_request_port(port);1394 }1395}1396 1397static int pch_uart_verify_port(struct uart_port *port,1398 struct serial_struct *serinfo)1399{1400 struct eg20t_port *priv;1401 1402 priv = container_of(port, struct eg20t_port, port);1403 if (serinfo->flags & UPF_LOW_LATENCY) {1404 dev_info(priv->port.dev,1405 "PCH UART : Use PIO Mode (without DMA)\n");1406 priv->use_dma = 0;1407 serinfo->flags &= ~UPF_LOW_LATENCY;1408 } else {1409#ifndef CONFIG_PCH_DMA1410 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",1411 __func__);1412 return -EOPNOTSUPP;1413#endif1414 if (!priv->use_dma) {1415 pch_request_dma(port);1416 if (priv->chan_rx)1417 priv->use_dma = 1;1418 }1419 dev_info(priv->port.dev, "PCH UART: %s\n",1420 priv->use_dma ?1421 "Use DMA Mode" : "No DMA");1422 }1423 1424 return 0;1425}1426 1427#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)1428/*1429 * Wait for transmitter & holding register to empty1430 */1431static void wait_for_xmitr(struct eg20t_port *up, int bits)1432{1433 unsigned int status, tmout = 10000;1434 1435 /* Wait up to 10ms for the character(s) to be sent. */1436 for (;;) {1437 status = ioread8(up->membase + UART_LSR);1438 1439 if ((status & bits) == bits)1440 break;1441 if (--tmout == 0)1442 break;1443 udelay(1);1444 }1445 1446 /* Wait up to 1s for flow control if necessary */1447 if (up->port.flags & UPF_CONS_FLOW) {1448 unsigned int tmout;1449 for (tmout = 1000000; tmout; tmout--) {1450 unsigned int msr = ioread8(up->membase + UART_MSR);1451 if (msr & UART_MSR_CTS)1452 break;1453 udelay(1);1454 touch_nmi_watchdog();1455 }1456 }1457}1458#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */1459 1460#ifdef CONFIG_CONSOLE_POLL1461/*1462 * Console polling routines for communicate via uart while1463 * in an interrupt or debug context.1464 */1465static int pch_uart_get_poll_char(struct uart_port *port)1466{1467 struct eg20t_port *priv =1468 container_of(port, struct eg20t_port, port);1469 u8 lsr = ioread8(priv->membase + UART_LSR);1470 1471 if (!(lsr & UART_LSR_DR))1472 return NO_POLL_CHAR;1473 1474 return ioread8(priv->membase + PCH_UART_RBR);1475}1476 1477 1478static void pch_uart_put_poll_char(struct uart_port *port,1479 unsigned char c)1480{1481 unsigned int ier;1482 struct eg20t_port *priv =1483 container_of(port, struct eg20t_port, port);1484 1485 /*1486 * First save the IER then disable the interrupts1487 */1488 ier = ioread8(priv->membase + UART_IER);1489 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);1490 1491 wait_for_xmitr(priv, UART_LSR_THRE);1492 /*1493 * Send the character out.1494 */1495 iowrite8(c, priv->membase + PCH_UART_THR);1496 1497 /*1498 * Finally, wait for transmitter to become empty1499 * and restore the IER1500 */1501 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);1502 iowrite8(ier, priv->membase + UART_IER);1503}1504#endif /* CONFIG_CONSOLE_POLL */1505 1506static const struct uart_ops pch_uart_ops = {1507 .tx_empty = pch_uart_tx_empty,1508 .set_mctrl = pch_uart_set_mctrl,1509 .get_mctrl = pch_uart_get_mctrl,1510 .stop_tx = pch_uart_stop_tx,1511 .start_tx = pch_uart_start_tx,1512 .stop_rx = pch_uart_stop_rx,1513 .enable_ms = pch_uart_enable_ms,1514 .break_ctl = pch_uart_break_ctl,1515 .startup = pch_uart_startup,1516 .shutdown = pch_uart_shutdown,1517 .set_termios = pch_uart_set_termios,1518/* .pm = pch_uart_pm, Not supported yet */1519 .type = pch_uart_type,1520 .release_port = pch_uart_release_port,1521 .request_port = pch_uart_request_port,1522 .config_port = pch_uart_config_port,1523 .verify_port = pch_uart_verify_port,1524#ifdef CONFIG_CONSOLE_POLL1525 .poll_get_char = pch_uart_get_poll_char,1526 .poll_put_char = pch_uart_put_poll_char,1527#endif1528};1529 1530#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE1531 1532static void pch_console_putchar(struct uart_port *port, unsigned char ch)1533{1534 struct eg20t_port *priv =1535 container_of(port, struct eg20t_port, port);1536 1537 wait_for_xmitr(priv, UART_LSR_THRE);1538 iowrite8(ch, priv->membase + PCH_UART_THR);1539}1540 1541/*1542 * Print a string to the serial port trying not to disturb1543 * any possible real use of the port...1544 *1545 * The console_lock must be held when we get here.1546 */1547static void1548pch_console_write(struct console *co, const char *s, unsigned int count)1549{1550 struct eg20t_port *priv;1551 unsigned long flags;1552 int locked = 1;1553 u8 ier;1554 1555 priv = pch_uart_ports[co->index];1556 1557 touch_nmi_watchdog();1558 1559 if (oops_in_progress)1560 locked = uart_port_trylock_irqsave(&priv->port, &flags);1561 else1562 uart_port_lock_irqsave(&priv->port, &flags);1563 1564 /*1565 * First save the IER then disable the interrupts1566 */1567 ier = ioread8(priv->membase + UART_IER);1568 1569 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);1570 1571 uart_console_write(&priv->port, s, count, pch_console_putchar);1572 1573 /*1574 * Finally, wait for transmitter to become empty1575 * and restore the IER1576 */1577 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);1578 iowrite8(ier, priv->membase + UART_IER);1579 1580 if (locked)1581 uart_port_unlock_irqrestore(&priv->port, flags);1582}1583 1584static int __init pch_console_setup(struct console *co, char *options)1585{1586 struct uart_port *port;1587 int baud = default_baud;1588 int bits = 8;1589 int parity = 'n';1590 int flow = 'n';1591 1592 /*1593 * Check whether an invalid uart number has been specified, and1594 * if so, search for the first available port that does have1595 * console support.1596 */1597 if (co->index >= PCH_UART_NR)1598 co->index = 0;1599 port = &pch_uart_ports[co->index]->port;1600 1601 if (!port || (!port->iobase && !port->membase))1602 return -ENODEV;1603 1604 port->uartclk = pch_uart_get_uartclk();1605 1606 if (options)1607 uart_parse_options(options, &baud, &parity, &bits, &flow);1608 1609 return uart_set_options(port, co, baud, parity, bits, flow);1610}1611 1612static struct uart_driver pch_uart_driver;1613 1614static struct console pch_console = {1615 .name = PCH_UART_DRIVER_DEVICE,1616 .write = pch_console_write,1617 .device = uart_console_device,1618 .setup = pch_console_setup,1619 .flags = CON_PRINTBUFFER | CON_ANYTIME,1620 .index = -1,1621 .data = &pch_uart_driver,1622};1623 1624#define PCH_CONSOLE (&pch_console)1625#else1626#define PCH_CONSOLE NULL1627#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */1628 1629static struct uart_driver pch_uart_driver = {1630 .owner = THIS_MODULE,1631 .driver_name = KBUILD_MODNAME,1632 .dev_name = PCH_UART_DRIVER_DEVICE,1633 .major = 0,1634 .minor = 0,1635 .nr = PCH_UART_NR,1636 .cons = PCH_CONSOLE,1637};1638 1639static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,1640 const struct pci_device_id *id)1641{1642 struct eg20t_port *priv;1643 int ret;1644 unsigned int iobase;1645 unsigned int mapbase;1646 unsigned char *rxbuf;1647 int fifosize;1648 int port_type;1649 struct pch_uart_driver_data *board;1650 char name[32];1651 1652 board = &drv_dat[id->driver_data];1653 port_type = board->port_type;1654 1655 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);1656 if (priv == NULL)1657 goto init_port_alloc_err;1658 1659 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);1660 if (!rxbuf)1661 goto init_port_free_txbuf;1662 1663 switch (port_type) {1664 case PORT_PCH_8LINE:1665 fifosize = 256; /* EG20T/ML7213: UART0 */1666 break;1667 case PORT_PCH_2LINE:1668 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/1669 break;1670 default:1671 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);1672 goto init_port_hal_free;1673 }1674 1675 pci_enable_msi(pdev);1676 pci_set_master(pdev);1677 1678 iobase = pci_resource_start(pdev, 0);1679 mapbase = pci_resource_start(pdev, 1);1680 priv->mapbase = mapbase;1681 priv->iobase = iobase;1682 priv->pdev = pdev;1683 priv->tx_empty = 1;1684 priv->rxbuf.buf = rxbuf;1685 priv->rxbuf.size = PAGE_SIZE;1686 1687 priv->fifo_size = fifosize;1688 priv->uartclk = pch_uart_get_uartclk();1689 priv->port_type = port_type;1690 priv->port.dev = &pdev->dev;1691 priv->port.iobase = iobase;1692 priv->port.membase = NULL;1693 priv->port.mapbase = mapbase;1694 priv->port.irq = pdev->irq;1695 priv->port.iotype = UPIO_PORT;1696 priv->port.ops = &pch_uart_ops;1697 priv->port.flags = UPF_BOOT_AUTOCONF;1698 priv->port.fifosize = fifosize;1699 priv->port.line = board->line_no;1700 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);1701 priv->trigger = PCH_UART_HAL_TRIGGER_M;1702 1703 snprintf(priv->irq_name, IRQ_NAME_SIZE,1704 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",1705 priv->port.line);1706 1707 pci_set_drvdata(pdev, priv);1708 priv->trigger_level = 1;1709 priv->fcr = 0;1710 1711 if (pdev->dev.of_node)1712 of_property_read_u32(pdev->dev.of_node, "clock-frequency"1713 , &user_uartclk);1714 1715#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE1716 pch_uart_ports[board->line_no] = priv;1717#endif1718 ret = uart_add_one_port(&pch_uart_driver, &priv->port);1719 if (ret < 0)1720 goto init_port_hal_free;1721 1722 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);1723 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,1724 &port_regs_ops);1725 1726 return priv;1727 1728init_port_hal_free:1729#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE1730 pch_uart_ports[board->line_no] = NULL;1731#endif1732 free_page((unsigned long)rxbuf);1733init_port_free_txbuf:1734 kfree(priv);1735init_port_alloc_err:1736 1737 return NULL;1738}1739 1740static void pch_uart_exit_port(struct eg20t_port *priv)1741{1742 char name[32];1743 1744 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);1745 debugfs_lookup_and_remove(name, NULL);1746 uart_remove_one_port(&pch_uart_driver, &priv->port);1747 free_page((unsigned long)priv->rxbuf.buf);1748}1749 1750static void pch_uart_pci_remove(struct pci_dev *pdev)1751{1752 struct eg20t_port *priv = pci_get_drvdata(pdev);1753 1754 pci_disable_msi(pdev);1755 1756#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE1757 pch_uart_ports[priv->port.line] = NULL;1758#endif1759 pch_uart_exit_port(priv);1760 pci_disable_device(pdev);1761 kfree(priv);1762 return;1763}1764 1765static int __maybe_unused pch_uart_pci_suspend(struct device *dev)1766{1767 struct eg20t_port *priv = dev_get_drvdata(dev);1768 1769 uart_suspend_port(&pch_uart_driver, &priv->port);1770 1771 return 0;1772}1773 1774static int __maybe_unused pch_uart_pci_resume(struct device *dev)1775{1776 struct eg20t_port *priv = dev_get_drvdata(dev);1777 1778 uart_resume_port(&pch_uart_driver, &priv->port);1779 1780 return 0;1781}1782 1783static const struct pci_device_id pch_uart_pci_id[] = {1784 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),1785 .driver_data = pch_et20t_uart0},1786 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),1787 .driver_data = pch_et20t_uart1},1788 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),1789 .driver_data = pch_et20t_uart2},1790 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),1791 .driver_data = pch_et20t_uart3},1792 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),1793 .driver_data = pch_ml7213_uart0},1794 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),1795 .driver_data = pch_ml7213_uart1},1796 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),1797 .driver_data = pch_ml7213_uart2},1798 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),1799 .driver_data = pch_ml7223_uart0},1800 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),1801 .driver_data = pch_ml7223_uart1},1802 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),1803 .driver_data = pch_ml7831_uart0},1804 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),1805 .driver_data = pch_ml7831_uart1},1806 {0,},1807};1808 1809static int pch_uart_pci_probe(struct pci_dev *pdev,1810 const struct pci_device_id *id)1811{1812 int ret;1813 struct eg20t_port *priv;1814 1815 ret = pci_enable_device(pdev);1816 if (ret < 0)1817 goto probe_error;1818 1819 priv = pch_uart_init_port(pdev, id);1820 if (!priv) {1821 ret = -EBUSY;1822 goto probe_disable_device;1823 }1824 pci_set_drvdata(pdev, priv);1825 1826 return ret;1827 1828probe_disable_device:1829 pci_disable_msi(pdev);1830 pci_disable_device(pdev);1831probe_error:1832 return ret;1833}1834 1835static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,1836 pch_uart_pci_suspend,1837 pch_uart_pci_resume);1838 1839static struct pci_driver pch_uart_pci_driver = {1840 .name = "pch_uart",1841 .id_table = pch_uart_pci_id,1842 .probe = pch_uart_pci_probe,1843 .remove = pch_uart_pci_remove,1844 .driver.pm = &pch_uart_pci_pm_ops,1845};1846 1847static int __init pch_uart_module_init(void)1848{1849 int ret;1850 1851 /* register as UART driver */1852 ret = uart_register_driver(&pch_uart_driver);1853 if (ret < 0)1854 return ret;1855 1856 /* register as PCI driver */1857 ret = pci_register_driver(&pch_uart_pci_driver);1858 if (ret < 0)1859 uart_unregister_driver(&pch_uart_driver);1860 1861 return ret;1862}1863module_init(pch_uart_module_init);1864 1865static void __exit pch_uart_module_exit(void)1866{1867 pci_unregister_driver(&pch_uart_pci_driver);1868 uart_unregister_driver(&pch_uart_driver);1869}1870module_exit(pch_uart_module_exit);1871 1872MODULE_LICENSE("GPL v2");1873MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");1874MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);1875 1876module_param(default_baud, uint, S_IRUGO);1877MODULE_PARM_DESC(default_baud,1878 "Default BAUD for initial driver state and console (default 9600)");1879module_param(user_uartclk, uint, S_IRUGO);1880MODULE_PARM_DESC(user_uartclk,1881 "Override UART default or board specific UART clock");1882