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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Driver for PowerMac Z85c30 based ESCC cell found in the4 * "macio" ASICs of various PowerMac models5 * 6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)7 *8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras9 * and drivers/serial/sunzilog.c by David S. Miller10 *11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and12 * adapted special tweaks needed for us. I don't think it's worth13 * merging back those though. The DMA code still has to get in14 * and once done, I expect that driver to remain fairly stable in15 * the long term, unless we change the driver model again...16 *17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>18 * - Enable BREAK interrupt19 * - Add support for sysreq20 *21 * TODO: - Add DMA support22 * - Defer port shutdown to a few seconds after close23 * - maybe put something right into uap->clk_divisor24 */25 26#undef DEBUG27#undef USE_CTRL_O_SYSRQ28 29#include <linux/module.h>30#include <linux/tty.h>31 32#include <linux/tty_flip.h>33#include <linux/major.h>34#include <linux/string.h>35#include <linux/fcntl.h>36#include <linux/mm.h>37#include <linux/kernel.h>38#include <linux/delay.h>39#include <linux/init.h>40#include <linux/console.h>41#include <linux/adb.h>42#include <linux/pmu.h>43#include <linux/bitops.h>44#include <linux/sysrq.h>45#include <linux/mutex.h>46#include <linux/of_address.h>47#include <linux/of_irq.h>48#include <asm/sections.h>49#include <linux/io.h>50#include <asm/irq.h>51 52#ifdef CONFIG_PPC_PMAC53#include <asm/machdep.h>54#include <asm/pmac_feature.h>55#include <asm/macio.h>56#else57#include <linux/platform_device.h>58#define of_machine_is_compatible(x) (0)59#endif60 61#include <linux/serial.h>62#include <linux/serial_core.h>63 64#include "pmac_zilog.h"65 66MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");67MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");68MODULE_LICENSE("GPL");69 70#ifdef CONFIG_SERIAL_PMACZILOG_TTYS71#define PMACZILOG_MAJOR TTY_MAJOR72#define PMACZILOG_MINOR 6473#define PMACZILOG_NAME "ttyS"74#else75#define PMACZILOG_MAJOR 20476#define PMACZILOG_MINOR 19277#define PMACZILOG_NAME "ttyPZ"78#endif79 80#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)81#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)82#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)83 84/*85 * For the sake of early serial console, we can do a pre-probe86 * (optional) of the ports at rather early boot time.87 */88static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];89static int pmz_ports_count;90 91static struct uart_driver pmz_uart_reg = {92 .owner = THIS_MODULE,93 .driver_name = PMACZILOG_NAME,94 .dev_name = PMACZILOG_NAME,95 .major = PMACZILOG_MAJOR,96 .minor = PMACZILOG_MINOR,97};98 99 100/* 101 * Load all registers to reprogram the port102 * This function must only be called when the TX is not busy. The UART103 * port lock must be held and local interrupts disabled.104 */105static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)106{107 int i;108 109 /* Let pending transmits finish. */110 for (i = 0; i < 1000; i++) {111 unsigned char stat = read_zsreg(uap, R1);112 if (stat & ALL_SNT)113 break;114 udelay(100);115 }116 117 ZS_CLEARERR(uap);118 zssync(uap);119 ZS_CLEARFIFO(uap);120 zssync(uap);121 ZS_CLEARERR(uap);122 123 /* Disable all interrupts. */124 write_zsreg(uap, R1,125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));126 127 /* Set parity, sync config, stop bits, and clock divisor. */128 write_zsreg(uap, R4, regs[R4]);129 130 /* Set misc. TX/RX control bits. */131 write_zsreg(uap, R10, regs[R10]);132 133 /* Set TX/RX controls sans the enable bits. */134 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);136 137 /* now set R7 "prime" on ESCC */138 write_zsreg(uap, R15, regs[R15] | EN85C30);139 write_zsreg(uap, R7, regs[R7P]);140 141 /* make sure we use R7 "non-prime" on ESCC */142 write_zsreg(uap, R15, regs[R15] & ~EN85C30);143 144 /* Synchronous mode config. */145 write_zsreg(uap, R6, regs[R6]);146 write_zsreg(uap, R7, regs[R7]);147 148 /* Disable baud generator. */149 write_zsreg(uap, R14, regs[R14] & ~BRENAB);150 151 /* Clock mode control. */152 write_zsreg(uap, R11, regs[R11]);153 154 /* Lower and upper byte of baud rate generator divisor. */155 write_zsreg(uap, R12, regs[R12]);156 write_zsreg(uap, R13, regs[R13]);157 158 /* Now rewrite R14, with BRENAB (if set). */159 write_zsreg(uap, R14, regs[R14]);160 161 /* Reset external status interrupts. */162 write_zsreg(uap, R0, RES_EXT_INT);163 write_zsreg(uap, R0, RES_EXT_INT);164 165 /* Rewrite R3/R5, this time without enables masked. */166 write_zsreg(uap, R3, regs[R3]);167 write_zsreg(uap, R5, regs[R5]);168 169 /* Rewrite R1, this time without IRQ enabled masked. */170 write_zsreg(uap, R1, regs[R1]);171 172 /* Enable interrupts */173 write_zsreg(uap, R9, regs[R9]);174}175 176/* 177 * We do like sunzilog to avoid disrupting pending Tx178 * Reprogram the Zilog channel HW registers with the copies found in the179 * software state struct. If the transmitter is busy, we defer this update180 * until the next TX complete interrupt. Else, we do it right now.181 *182 * The UART port lock must be held and local interrupts disabled.183 */184static void pmz_maybe_update_regs(struct uart_pmac_port *uap)185{186 if (!ZS_REGS_HELD(uap)) {187 if (ZS_TX_ACTIVE(uap)) {188 uap->flags |= PMACZILOG_FLAG_REGS_HELD;189 } else {190 pmz_debug("pmz: maybe_update_regs: updating\n");191 pmz_load_zsregs(uap, uap->curregs);192 }193 }194}195 196static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)197{198 if (enable) {199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;200 if (!ZS_IS_EXTCLK(uap))201 uap->curregs[1] |= EXT_INT_ENAB;202 } else {203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);204 }205 write_zsreg(uap, R1, uap->curregs[1]);206}207 208static bool pmz_receive_chars(struct uart_pmac_port *uap)209 __must_hold(&uap->port.lock)210{211 struct tty_port *port;212 unsigned char ch, r1, drop, flag;213 214 /* Sanity check, make sure the old bug is no longer happening */215 if (uap->port.state == NULL) {216 WARN_ON(1);217 (void)read_zsdata(uap);218 return false;219 }220 port = &uap->port.state->port;221 222 while (1) {223 drop = 0;224 225 r1 = read_zsreg(uap, R1);226 ch = read_zsdata(uap);227 228 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {229 write_zsreg(uap, R0, ERR_RES);230 zssync(uap);231 }232 233 ch &= uap->parity_mask;234 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {235 uap->flags &= ~PMACZILOG_FLAG_BREAK;236 }237 238#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)239#ifdef USE_CTRL_O_SYSRQ240 /* Handle the SysRq ^O Hack */241 if (ch == '\x0f') {242 uap->port.sysrq = jiffies + HZ*5;243 goto next_char;244 }245#endif /* USE_CTRL_O_SYSRQ */246 if (uap->port.sysrq) {247 int swallow;248 uart_port_unlock(&uap->port);249 swallow = uart_handle_sysrq_char(&uap->port, ch);250 uart_port_lock(&uap->port);251 if (swallow)252 goto next_char;253 }254#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */255 256 /* A real serial line, record the character and status. */257 if (drop)258 goto next_char;259 260 flag = TTY_NORMAL;261 uap->port.icount.rx++;262 263 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {264 if (r1 & BRK_ABRT) {265 pmz_debug("pmz: got break !\n");266 r1 &= ~(PAR_ERR | CRC_ERR);267 uap->port.icount.brk++;268 if (uart_handle_break(&uap->port))269 goto next_char;270 }271 else if (r1 & PAR_ERR)272 uap->port.icount.parity++;273 else if (r1 & CRC_ERR)274 uap->port.icount.frame++;275 if (r1 & Rx_OVR)276 uap->port.icount.overrun++;277 r1 &= uap->port.read_status_mask;278 if (r1 & BRK_ABRT)279 flag = TTY_BREAK;280 else if (r1 & PAR_ERR)281 flag = TTY_PARITY;282 else if (r1 & CRC_ERR)283 flag = TTY_FRAME;284 }285 286 if (uap->port.ignore_status_mask == 0xff ||287 (r1 & uap->port.ignore_status_mask) == 0) {288 tty_insert_flip_char(port, ch, flag);289 }290 if (r1 & Rx_OVR)291 tty_insert_flip_char(port, 0, TTY_OVERRUN);292 next_char:293 ch = read_zsreg(uap, R0);294 if (!(ch & Rx_CH_AV))295 break;296 }297 298 return true;299}300 301static void pmz_status_handle(struct uart_pmac_port *uap)302{303 unsigned char status;304 305 status = read_zsreg(uap, R0);306 write_zsreg(uap, R0, RES_EXT_INT);307 zssync(uap);308 309 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {310 if (status & SYNC_HUNT)311 uap->port.icount.dsr++;312 313 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.314 * But it does not tell us which bit has changed, we have to keep315 * track of this ourselves.316 * The CTS input is inverted for some reason. -- paulus317 */318 if ((status ^ uap->prev_status) & DCD)319 uart_handle_dcd_change(&uap->port,320 (status & DCD));321 if ((status ^ uap->prev_status) & CTS)322 uart_handle_cts_change(&uap->port,323 !(status & CTS));324 325 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);326 }327 328 if (status & BRK_ABRT)329 uap->flags |= PMACZILOG_FLAG_BREAK;330 331 uap->prev_status = status;332}333 334static void pmz_transmit_chars(struct uart_pmac_port *uap)335{336 struct tty_port *tport;337 unsigned char ch;338 339 if (ZS_IS_CONS(uap)) {340 unsigned char status = read_zsreg(uap, R0);341 342 /* TX still busy? Just wait for the next TX done interrupt.343 *344 * It can occur because of how we do serial console writes. It would345 * be nice to transmit console writes just like we normally would for346 * a TTY line. (ie. buffered and TX interrupt driven). That is not347 * easy because console writes cannot sleep. One solution might be348 * to poll on enough port->xmit space becoming free. -DaveM349 */350 if (!(status & Tx_BUF_EMP))351 return;352 }353 354 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;355 356 if (ZS_REGS_HELD(uap)) {357 pmz_load_zsregs(uap, uap->curregs);358 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;359 }360 361 if (ZS_TX_STOPPED(uap)) {362 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;363 goto ack_tx_int;364 }365 366 /* Under some circumstances, we see interrupts reported for367 * a closed channel. The interrupt mask in R1 is clear, but368 * R3 still signals the interrupts and we see them when taking369 * an interrupt for the other channel (this could be a qemu370 * bug but since the ESCC doc doesn't specify precsiely whether371 * R3 interrup status bits are masked by R1 interrupt enable372 * bits, better safe than sorry). --BenH.373 */374 if (!ZS_IS_OPEN(uap))375 goto ack_tx_int;376 377 if (uap->port.x_char) {378 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;379 write_zsdata(uap, uap->port.x_char);380 zssync(uap);381 uap->port.icount.tx++;382 uap->port.x_char = 0;383 return;384 }385 386 if (uap->port.state == NULL)387 goto ack_tx_int;388 tport = &uap->port.state->port;389 if (kfifo_is_empty(&tport->xmit_fifo)) {390 uart_write_wakeup(&uap->port);391 goto ack_tx_int;392 }393 if (uart_tx_stopped(&uap->port))394 goto ack_tx_int;395 396 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;397 WARN_ON(!uart_fifo_get(&uap->port, &ch));398 write_zsdata(uap, ch);399 zssync(uap);400 401 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)402 uart_write_wakeup(&uap->port);403 404 return;405 406ack_tx_int:407 write_zsreg(uap, R0, RES_Tx_P);408 zssync(uap);409}410 411/* Hrm... we register that twice, fixme later.... */412static irqreturn_t pmz_interrupt(int irq, void *dev_id)413{414 struct uart_pmac_port *uap = dev_id;415 struct uart_pmac_port *uap_a;416 struct uart_pmac_port *uap_b;417 int rc = IRQ_NONE;418 bool push;419 u8 r3;420 421 uap_a = pmz_get_port_A(uap);422 uap_b = uap_a->mate;423 424 uart_port_lock(&uap_a->port);425 r3 = read_zsreg(uap_a, R3);426 427 /* Channel A */428 push = false;429 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {430 if (!ZS_IS_OPEN(uap_a)) {431 pmz_debug("ChanA interrupt while not open !\n");432 goto skip_a;433 }434 write_zsreg(uap_a, R0, RES_H_IUS);435 zssync(uap_a); 436 if (r3 & CHAEXT)437 pmz_status_handle(uap_a);438 if (r3 & CHARxIP)439 push = pmz_receive_chars(uap_a);440 if (r3 & CHATxIP)441 pmz_transmit_chars(uap_a);442 rc = IRQ_HANDLED;443 }444 skip_a:445 uart_port_unlock(&uap_a->port);446 if (push)447 tty_flip_buffer_push(&uap->port.state->port);448 449 if (!uap_b)450 goto out;451 452 uart_port_lock(&uap_b->port);453 push = false;454 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {455 if (!ZS_IS_OPEN(uap_b)) {456 pmz_debug("ChanB interrupt while not open !\n");457 goto skip_b;458 }459 write_zsreg(uap_b, R0, RES_H_IUS);460 zssync(uap_b);461 if (r3 & CHBEXT)462 pmz_status_handle(uap_b);463 if (r3 & CHBRxIP)464 push = pmz_receive_chars(uap_b);465 if (r3 & CHBTxIP)466 pmz_transmit_chars(uap_b);467 rc = IRQ_HANDLED;468 }469 skip_b:470 uart_port_unlock(&uap_b->port);471 if (push)472 tty_flip_buffer_push(&uap->port.state->port);473 474 out:475 return rc;476}477 478/*479 * Peek the status register, lock not held by caller480 */481static inline u8 pmz_peek_status(struct uart_pmac_port *uap)482{483 unsigned long flags;484 u8 status;485 486 uart_port_lock_irqsave(&uap->port, &flags);487 status = read_zsreg(uap, R0);488 uart_port_unlock_irqrestore(&uap->port, flags);489 490 return status;491}492 493/* 494 * Check if transmitter is empty495 * The port lock is not held.496 */497static unsigned int pmz_tx_empty(struct uart_port *port)498{499 unsigned char status;500 501 status = pmz_peek_status(to_pmz(port));502 if (status & Tx_BUF_EMP)503 return TIOCSER_TEMT;504 return 0;505}506 507/* 508 * Set Modem Control (RTS & DTR) bits509 * The port lock is held and interrupts are disabled.510 * Note: Shall we really filter out RTS on external ports or511 * should that be dealt at higher level only ?512 */513static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)514{515 struct uart_pmac_port *uap = to_pmz(port);516 unsigned char set_bits, clear_bits;517 518 /* Do nothing for irda for now... */519 if (ZS_IS_IRDA(uap))520 return;521 /* We get called during boot with a port not up yet */522 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))523 return;524 525 set_bits = clear_bits = 0;526 527 if (ZS_IS_INTMODEM(uap)) {528 if (mctrl & TIOCM_RTS)529 set_bits |= RTS;530 else531 clear_bits |= RTS;532 }533 if (mctrl & TIOCM_DTR)534 set_bits |= DTR;535 else536 clear_bits |= DTR;537 538 /* NOTE: Not subject to 'transmitter active' rule. */ 539 uap->curregs[R5] |= set_bits;540 uap->curregs[R5] &= ~clear_bits;541 542 write_zsreg(uap, R5, uap->curregs[R5]);543 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",544 set_bits, clear_bits, uap->curregs[R5]);545 zssync(uap);546}547 548/* 549 * Get Modem Control bits (only the input ones, the core will550 * or that with a cached value of the control ones)551 * The port lock is held and interrupts are disabled.552 */553static unsigned int pmz_get_mctrl(struct uart_port *port)554{555 struct uart_pmac_port *uap = to_pmz(port);556 unsigned char status;557 unsigned int ret;558 559 status = read_zsreg(uap, R0);560 561 ret = 0;562 if (status & DCD)563 ret |= TIOCM_CAR;564 if (status & SYNC_HUNT)565 ret |= TIOCM_DSR;566 if (!(status & CTS))567 ret |= TIOCM_CTS;568 569 return ret;570}571 572/* 573 * Stop TX side. Dealt like sunzilog at next Tx interrupt,574 * though for DMA, we will have to do a bit more.575 * The port lock is held and interrupts are disabled.576 */577static void pmz_stop_tx(struct uart_port *port)578{579 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;580}581 582/* 583 * Kick the Tx side.584 * The port lock is held and interrupts are disabled.585 */586static void pmz_start_tx(struct uart_port *port)587{588 struct uart_pmac_port *uap = to_pmz(port);589 unsigned char status;590 591 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;592 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;593 594 status = read_zsreg(uap, R0);595 596 /* TX busy? Just wait for the TX done interrupt. */597 if (!(status & Tx_BUF_EMP))598 return;599 600 /* Send the first character to jump-start the TX done601 * IRQ sending engine.602 */603 if (port->x_char) {604 write_zsdata(uap, port->x_char);605 zssync(uap);606 port->icount.tx++;607 port->x_char = 0;608 } else {609 struct tty_port *tport = &port->state->port;610 unsigned char ch;611 612 if (!uart_fifo_get(&uap->port, &ch))613 return;614 write_zsdata(uap, ch);615 zssync(uap);616 617 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)618 uart_write_wakeup(&uap->port);619 }620}621 622/* 623 * Stop Rx side, basically disable emitting of624 * Rx interrupts on the port. We don't disable the rx625 * side of the chip proper though626 * The port lock is held.627 */628static void pmz_stop_rx(struct uart_port *port)629{630 struct uart_pmac_port *uap = to_pmz(port);631 632 /* Disable all RX interrupts. */633 uap->curregs[R1] &= ~RxINT_MASK;634 pmz_maybe_update_regs(uap);635}636 637/* 638 * Enable modem status change interrupts639 * The port lock is held.640 */641static void pmz_enable_ms(struct uart_port *port)642{643 struct uart_pmac_port *uap = to_pmz(port);644 unsigned char new_reg;645 646 if (ZS_IS_IRDA(uap))647 return;648 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);649 if (new_reg != uap->curregs[R15]) {650 uap->curregs[R15] = new_reg;651 652 /* NOTE: Not subject to 'transmitter active' rule. */653 write_zsreg(uap, R15, uap->curregs[R15]);654 }655}656 657/* 658 * Control break state emission659 * The port lock is not held.660 */661static void pmz_break_ctl(struct uart_port *port, int break_state)662{663 struct uart_pmac_port *uap = to_pmz(port);664 unsigned char set_bits, clear_bits, new_reg;665 unsigned long flags;666 667 set_bits = clear_bits = 0;668 669 if (break_state)670 set_bits |= SND_BRK;671 else672 clear_bits |= SND_BRK;673 674 uart_port_lock_irqsave(port, &flags);675 676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;677 if (new_reg != uap->curregs[R5]) {678 uap->curregs[R5] = new_reg;679 write_zsreg(uap, R5, uap->curregs[R5]);680 }681 682 uart_port_unlock_irqrestore(port, flags);683}684 685#ifdef CONFIG_PPC_PMAC686 687/*688 * Turn power on or off to the SCC and associated stuff689 * (port drivers, modem, IR port, etc.)690 * Returns the number of milliseconds we should wait before691 * trying to use the port.692 */693static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)694{695 int delay = 0;696 int rc;697 698 if (state) {699 rc = pmac_call_feature(700 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);701 pmz_debug("port power on result: %d\n", rc);702 if (ZS_IS_INTMODEM(uap)) {703 rc = pmac_call_feature(704 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);705 delay = 2500; /* wait for 2.5s before using */706 pmz_debug("modem power result: %d\n", rc);707 }708 } else {709 /* TODO: Make that depend on a timer, don't power down710 * immediately711 */712 if (ZS_IS_INTMODEM(uap)) {713 rc = pmac_call_feature(714 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);715 pmz_debug("port power off result: %d\n", rc);716 }717 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);718 }719 return delay;720}721 722#else723 724static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)725{726 return 0;727}728 729#endif /* !CONFIG_PPC_PMAC */730 731/*732 * FixZeroBug....Works around a bug in the SCC receiving channel.733 * Inspired from Darwin code, 15 Sept. 2000 -DanM734 *735 * The following sequence prevents a problem that is seen with O'Hare ASICs736 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero737 * at the input to the receiver becomes 'stuck' and locks up the receiver.738 * This problem can occur as a result of a zero bit at the receiver input739 * coincident with any of the following events:740 *741 * The SCC is initialized (hardware or software).742 * A framing error is detected.743 * The clocking option changes from synchronous or X1 asynchronous744 * clocking to X16, X32, or X64 asynchronous clocking.745 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.746 *747 * This workaround attempts to recover from the lockup condition by placing748 * the SCC in synchronous loopback mode with a fast clock before programming749 * any of the asynchronous modes.750 */751static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)752{753 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);754 zssync(uap);755 udelay(10);756 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);757 zssync(uap);758 759 write_zsreg(uap, 4, X1CLK | MONSYNC);760 write_zsreg(uap, 3, Rx8);761 write_zsreg(uap, 5, Tx8 | RTS);762 write_zsreg(uap, 9, NV); /* Didn't we already do this? */763 write_zsreg(uap, 11, RCBR | TCBR);764 write_zsreg(uap, 12, 0);765 write_zsreg(uap, 13, 0);766 write_zsreg(uap, 14, (LOOPBAK | BRSRC));767 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));768 write_zsreg(uap, 3, Rx8 | RxENABLE);769 write_zsreg(uap, 0, RES_EXT_INT);770 write_zsreg(uap, 0, RES_EXT_INT);771 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */772 773 /* The channel should be OK now, but it is probably receiving774 * loopback garbage.775 * Switch to asynchronous mode, disable the receiver,776 * and discard everything in the receive buffer.777 */778 write_zsreg(uap, 9, NV);779 write_zsreg(uap, 4, X16CLK | SB_MASK);780 write_zsreg(uap, 3, Rx8);781 782 while (read_zsreg(uap, 0) & Rx_CH_AV) {783 (void)read_zsreg(uap, 8);784 write_zsreg(uap, 0, RES_EXT_INT);785 write_zsreg(uap, 0, ERR_RES);786 }787}788 789/*790 * Real startup routine, powers up the hardware and sets up791 * the SCC. Returns a delay in ms where you need to wait before792 * actually using the port, this is typically the internal modem793 * powerup delay. This routine expect the lock to be taken.794 */795static int __pmz_startup(struct uart_pmac_port *uap)796{797 int pwr_delay = 0;798 799 memset(&uap->curregs, 0, sizeof(uap->curregs));800 801 /* Power up the SCC & underlying hardware (modem/irda) */802 pwr_delay = pmz_set_scc_power(uap, 1);803 804 /* Nice buggy HW ... */805 pmz_fix_zero_bug_scc(uap);806 807 /* Reset the channel */808 uap->curregs[R9] = 0;809 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);810 zssync(uap);811 udelay(10);812 write_zsreg(uap, 9, 0);813 zssync(uap);814 815 /* Clear the interrupt registers */816 write_zsreg(uap, R1, 0);817 write_zsreg(uap, R0, ERR_RES);818 write_zsreg(uap, R0, ERR_RES);819 write_zsreg(uap, R0, RES_H_IUS);820 write_zsreg(uap, R0, RES_H_IUS);821 822 /* Setup some valid baud rate */823 uap->curregs[R4] = X16CLK | SB1;824 uap->curregs[R3] = Rx8;825 uap->curregs[R5] = Tx8 | RTS;826 if (!ZS_IS_IRDA(uap))827 uap->curregs[R5] |= DTR;828 uap->curregs[R12] = 0;829 uap->curregs[R13] = 0;830 uap->curregs[R14] = BRENAB;831 832 /* Clear handshaking, enable BREAK interrupts */833 uap->curregs[R15] = BRKIE;834 835 /* Master interrupt enable */836 uap->curregs[R9] |= NV | MIE;837 838 pmz_load_zsregs(uap, uap->curregs);839 840 /* Enable receiver and transmitter. */841 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);842 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);843 844 /* Remember status for DCD/CTS changes */845 uap->prev_status = read_zsreg(uap, R0);846 847 return pwr_delay;848}849 850static void pmz_irda_reset(struct uart_pmac_port *uap)851{852 unsigned long flags;853 854 uart_port_lock_irqsave(&uap->port, &flags);855 uap->curregs[R5] |= DTR;856 write_zsreg(uap, R5, uap->curregs[R5]);857 zssync(uap);858 uart_port_unlock_irqrestore(&uap->port, flags);859 msleep(110);860 861 uart_port_lock_irqsave(&uap->port, &flags);862 uap->curregs[R5] &= ~DTR;863 write_zsreg(uap, R5, uap->curregs[R5]);864 zssync(uap);865 uart_port_unlock_irqrestore(&uap->port, flags);866 msleep(10);867}868 869/*870 * This is the "normal" startup routine, using the above one871 * wrapped with the lock and doing a schedule delay872 */873static int pmz_startup(struct uart_port *port)874{875 struct uart_pmac_port *uap = to_pmz(port);876 unsigned long flags;877 int pwr_delay = 0;878 879 uap->flags |= PMACZILOG_FLAG_IS_OPEN;880 881 /* A console is never powered down. Else, power up and882 * initialize the chip883 */884 if (!ZS_IS_CONS(uap)) {885 uart_port_lock_irqsave(port, &flags);886 pwr_delay = __pmz_startup(uap);887 uart_port_unlock_irqrestore(port, flags);888 } 889 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);890 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,891 uap->irq_name, uap)) {892 pmz_error("Unable to register zs interrupt handler.\n");893 pmz_set_scc_power(uap, 0);894 return -ENXIO;895 }896 897 /* Right now, we deal with delay by blocking here, I'll be898 * smarter later on899 */900 if (pwr_delay != 0) {901 pmz_debug("pmz: delaying %d ms\n", pwr_delay);902 msleep(pwr_delay);903 }904 905 /* IrDA reset is done now */906 if (ZS_IS_IRDA(uap))907 pmz_irda_reset(uap);908 909 /* Enable interrupt requests for the channel */910 uart_port_lock_irqsave(port, &flags);911 pmz_interrupt_control(uap, 1);912 uart_port_unlock_irqrestore(port, flags);913 914 return 0;915}916 917static void pmz_shutdown(struct uart_port *port)918{919 struct uart_pmac_port *uap = to_pmz(port);920 unsigned long flags;921 922 uart_port_lock_irqsave(port, &flags);923 924 /* Disable interrupt requests for the channel */925 pmz_interrupt_control(uap, 0);926 927 if (!ZS_IS_CONS(uap)) {928 /* Disable receiver and transmitter */929 uap->curregs[R3] &= ~RxENABLE;930 uap->curregs[R5] &= ~TxENABLE;931 932 /* Disable break assertion */933 uap->curregs[R5] &= ~SND_BRK;934 pmz_maybe_update_regs(uap);935 }936 937 uart_port_unlock_irqrestore(port, flags);938 939 /* Release interrupt handler */940 free_irq(uap->port.irq, uap);941 942 uart_port_lock_irqsave(port, &flags);943 944 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;945 946 if (!ZS_IS_CONS(uap))947 pmz_set_scc_power(uap, 0); /* Shut the chip down */948 949 uart_port_unlock_irqrestore(port, flags);950}951 952/* Shared by TTY driver and serial console setup. The port lock is held953 * and local interrupts are disabled.954 */955static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,956 unsigned int iflag, unsigned long baud)957{958 int brg;959 960 /* Switch to external clocking for IrDA high clock rates. That961 * code could be re-used for Midi interfaces with different962 * multipliers963 */964 if (baud >= 115200 && ZS_IS_IRDA(uap)) {965 uap->curregs[R4] = X1CLK;966 uap->curregs[R11] = RCTRxCP | TCTRxCP;967 uap->curregs[R14] = 0; /* BRG off */968 uap->curregs[R12] = 0;969 uap->curregs[R13] = 0;970 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;971 } else {972 switch (baud) {973 case ZS_CLOCK/16: /* 230400 */974 uap->curregs[R4] = X16CLK;975 uap->curregs[R11] = 0;976 uap->curregs[R14] = 0;977 break;978 case ZS_CLOCK/32: /* 115200 */979 uap->curregs[R4] = X32CLK;980 uap->curregs[R11] = 0;981 uap->curregs[R14] = 0;982 break;983 default:984 uap->curregs[R4] = X16CLK;985 uap->curregs[R11] = TCBR | RCBR;986 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);987 uap->curregs[R12] = (brg & 255);988 uap->curregs[R13] = ((brg >> 8) & 255);989 uap->curregs[R14] = BRENAB;990 }991 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;992 }993 994 /* Character size, stop bits, and parity. */995 uap->curregs[3] &= ~RxN_MASK;996 uap->curregs[5] &= ~TxN_MASK;997 998 switch (cflag & CSIZE) {999 case CS5:1000 uap->curregs[3] |= Rx5;1001 uap->curregs[5] |= Tx5;1002 uap->parity_mask = 0x1f;1003 break;1004 case CS6:1005 uap->curregs[3] |= Rx6;1006 uap->curregs[5] |= Tx6;1007 uap->parity_mask = 0x3f;1008 break;1009 case CS7:1010 uap->curregs[3] |= Rx7;1011 uap->curregs[5] |= Tx7;1012 uap->parity_mask = 0x7f;1013 break;1014 case CS8:1015 default:1016 uap->curregs[3] |= Rx8;1017 uap->curregs[5] |= Tx8;1018 uap->parity_mask = 0xff;1019 break;1020 }1021 uap->curregs[4] &= ~(SB_MASK);1022 if (cflag & CSTOPB)1023 uap->curregs[4] |= SB2;1024 else1025 uap->curregs[4] |= SB1;1026 if (cflag & PARENB)1027 uap->curregs[4] |= PAR_ENAB;1028 else1029 uap->curregs[4] &= ~PAR_ENAB;1030 if (!(cflag & PARODD))1031 uap->curregs[4] |= PAR_EVEN;1032 else1033 uap->curregs[4] &= ~PAR_EVEN;1034 1035 uap->port.read_status_mask = Rx_OVR;1036 if (iflag & INPCK)1037 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;1038 if (iflag & (IGNBRK | BRKINT | PARMRK))1039 uap->port.read_status_mask |= BRK_ABRT;1040 1041 uap->port.ignore_status_mask = 0;1042 if (iflag & IGNPAR)1043 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;1044 if (iflag & IGNBRK) {1045 uap->port.ignore_status_mask |= BRK_ABRT;1046 if (iflag & IGNPAR)1047 uap->port.ignore_status_mask |= Rx_OVR;1048 }1049 1050 if ((cflag & CREAD) == 0)1051 uap->port.ignore_status_mask = 0xff;1052}1053 1054 1055/*1056 * Set the irda codec on the imac to the specified baud rate.1057 */1058static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)1059{1060 u8 cmdbyte;1061 int t, version;1062 1063 switch (*baud) {1064 /* SIR modes */1065 case 2400:1066 cmdbyte = 0x53;1067 break;1068 case 4800:1069 cmdbyte = 0x52;1070 break;1071 case 9600:1072 cmdbyte = 0x51;1073 break;1074 case 19200:1075 cmdbyte = 0x50;1076 break;1077 case 38400:1078 cmdbyte = 0x4f;1079 break;1080 case 57600:1081 cmdbyte = 0x4e;1082 break;1083 case 115200:1084 cmdbyte = 0x4d;1085 break;1086 /* The FIR modes aren't really supported at this point, how1087 * do we select the speed ? via the FCR on KeyLargo ?1088 */1089 case 1152000:1090 cmdbyte = 0;1091 break;1092 case 4000000:1093 cmdbyte = 0;1094 break;1095 default: /* 9600 */1096 cmdbyte = 0x51;1097 *baud = 9600;1098 break;1099 }1100 1101 /* Wait for transmitter to drain */1102 t = 10000;1103 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 01104 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {1105 if (--t <= 0) {1106 pmz_error("transmitter didn't drain\n");1107 return;1108 }1109 udelay(10);1110 }1111 1112 /* Drain the receiver too */1113 t = 100;1114 (void)read_zsdata(uap);1115 (void)read_zsdata(uap);1116 (void)read_zsdata(uap);1117 mdelay(10);1118 while (read_zsreg(uap, R0) & Rx_CH_AV) {1119 read_zsdata(uap);1120 mdelay(10);1121 if (--t <= 0) {1122 pmz_error("receiver didn't drain\n");1123 return;1124 }1125 }1126 1127 /* Switch to command mode */1128 uap->curregs[R5] |= DTR;1129 write_zsreg(uap, R5, uap->curregs[R5]);1130 zssync(uap);1131 mdelay(1);1132 1133 /* Switch SCC to 19200 */1134 pmz_convert_to_zs(uap, CS8, 0, 19200); 1135 pmz_load_zsregs(uap, uap->curregs);1136 mdelay(1);1137 1138 /* Write get_version command byte */1139 write_zsdata(uap, 1);1140 t = 5000;1141 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {1142 if (--t <= 0) {1143 pmz_error("irda_setup timed out on get_version byte\n");1144 goto out;1145 }1146 udelay(10);1147 }1148 version = read_zsdata(uap);1149 1150 if (version < 4) {1151 pmz_info("IrDA: dongle version %d not supported\n", version);1152 goto out;1153 }1154 1155 /* Send speed mode */1156 write_zsdata(uap, cmdbyte);1157 t = 5000;1158 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {1159 if (--t <= 0) {1160 pmz_error("irda_setup timed out on speed mode byte\n");1161 goto out;1162 }1163 udelay(10);1164 }1165 t = read_zsdata(uap);1166 if (t != cmdbyte)1167 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);1168 1169 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",1170 *baud, version);1171 1172 (void)read_zsdata(uap);1173 (void)read_zsdata(uap);1174 (void)read_zsdata(uap);1175 1176 out:1177 /* Switch back to data mode */1178 uap->curregs[R5] &= ~DTR;1179 write_zsreg(uap, R5, uap->curregs[R5]);1180 zssync(uap);1181 1182 (void)read_zsdata(uap);1183 (void)read_zsdata(uap);1184 (void)read_zsdata(uap);1185}1186 1187 1188static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,1189 const struct ktermios *old)1190{1191 struct uart_pmac_port *uap = to_pmz(port);1192 unsigned long baud;1193 1194 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds1195 * on the IR dongle. Note that the IRTTY driver currently doesn't know1196 * about the FIR mode and high speed modes. So these are unused. For1197 * implementing proper support for these, we should probably add some1198 * DMA as well, at least on the Rx side, which isn't a simple thing1199 * at this point.1200 */1201 if (ZS_IS_IRDA(uap)) {1202 /* Calc baud rate */1203 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);1204 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);1205 /* Cet the irda codec to the right rate */1206 pmz_irda_setup(uap, &baud);1207 /* Set final baud rate */1208 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);1209 pmz_load_zsregs(uap, uap->curregs);1210 zssync(uap);1211 } else {1212 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);1213 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);1214 /* Make sure modem status interrupts are correctly configured */1215 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {1216 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;1217 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;1218 } else {1219 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);1220 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;1221 }1222 1223 /* Load registers to the chip */1224 pmz_maybe_update_regs(uap);1225 }1226 uart_update_timeout(port, termios->c_cflag, baud);1227}1228 1229/* The port lock is not held. */1230static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,1231 const struct ktermios *old)1232{1233 struct uart_pmac_port *uap = to_pmz(port);1234 unsigned long flags;1235 1236 uart_port_lock_irqsave(port, &flags); 1237 1238 /* Disable IRQs on the port */1239 pmz_interrupt_control(uap, 0);1240 1241 /* Setup new port configuration */1242 __pmz_set_termios(port, termios, old);1243 1244 /* Re-enable IRQs on the port */1245 if (ZS_IS_OPEN(uap))1246 pmz_interrupt_control(uap, 1);1247 1248 uart_port_unlock_irqrestore(port, flags);1249}1250 1251static const char *pmz_type(struct uart_port *port)1252{1253 struct uart_pmac_port *uap = to_pmz(port);1254 1255 if (ZS_IS_IRDA(uap))1256 return "Z85c30 ESCC - Infrared port";1257 else if (ZS_IS_INTMODEM(uap))1258 return "Z85c30 ESCC - Internal modem";1259 return "Z85c30 ESCC - Serial port";1260}1261 1262/* We do not request/release mappings of the registers here, this1263 * happens at early serial probe time.1264 */1265static void pmz_release_port(struct uart_port *port)1266{1267}1268 1269static int pmz_request_port(struct uart_port *port)1270{1271 return 0;1272}1273 1274/* These do not need to do anything interesting either. */1275static void pmz_config_port(struct uart_port *port, int flags)1276{1277}1278 1279/* We do not support letting the user mess with the divisor, IRQ, etc. */1280static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)1281{1282 return -EINVAL;1283}1284 1285#ifdef CONFIG_CONSOLE_POLL1286 1287static int pmz_poll_get_char(struct uart_port *port)1288{1289 struct uart_pmac_port *uap =1290 container_of(port, struct uart_pmac_port, port);1291 int tries = 2;1292 1293 while (tries) {1294 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)1295 return read_zsdata(uap);1296 if (tries--)1297 udelay(5);1298 }1299 1300 return NO_POLL_CHAR;1301}1302 1303static void pmz_poll_put_char(struct uart_port *port, unsigned char c)1304{1305 struct uart_pmac_port *uap =1306 container_of(port, struct uart_pmac_port, port);1307 1308 /* Wait for the transmit buffer to empty. */1309 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)1310 udelay(5);1311 write_zsdata(uap, c);1312}1313 1314#endif /* CONFIG_CONSOLE_POLL */1315 1316static const struct uart_ops pmz_pops = {1317 .tx_empty = pmz_tx_empty,1318 .set_mctrl = pmz_set_mctrl,1319 .get_mctrl = pmz_get_mctrl,1320 .stop_tx = pmz_stop_tx,1321 .start_tx = pmz_start_tx,1322 .stop_rx = pmz_stop_rx,1323 .enable_ms = pmz_enable_ms,1324 .break_ctl = pmz_break_ctl,1325 .startup = pmz_startup,1326 .shutdown = pmz_shutdown,1327 .set_termios = pmz_set_termios,1328 .type = pmz_type,1329 .release_port = pmz_release_port,1330 .request_port = pmz_request_port,1331 .config_port = pmz_config_port,1332 .verify_port = pmz_verify_port,1333#ifdef CONFIG_CONSOLE_POLL1334 .poll_get_char = pmz_poll_get_char,1335 .poll_put_char = pmz_poll_put_char,1336#endif1337};1338 1339#ifdef CONFIG_PPC_PMAC1340 1341/*1342 * Setup one port structure after probing, HW is down at this point,1343 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't1344 * register our console before uart_add_one_port() is called1345 */1346static int __init pmz_init_port(struct uart_pmac_port *uap)1347{1348 struct device_node *np = uap->node;1349 const char *conn;1350 const struct slot_names_prop {1351 int count;1352 char name[1];1353 } *slots;1354 int len;1355 struct resource r_ports;1356 1357 /*1358 * Request & map chip registers1359 */1360 if (of_address_to_resource(np, 0, &r_ports))1361 return -ENODEV;1362 uap->port.mapbase = r_ports.start;1363 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);1364 1365 uap->control_reg = uap->port.membase;1366 uap->data_reg = uap->control_reg + 0x10;1367 1368 /*1369 * Detect port type1370 */1371 if (of_device_is_compatible(np, "cobalt"))1372 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;1373 conn = of_get_property(np, "AAPL,connector", &len);1374 if (conn && (strcmp(conn, "infrared") == 0))1375 uap->flags |= PMACZILOG_FLAG_IS_IRDA;1376 uap->port_type = PMAC_SCC_ASYNC;1377 /* 1999 Powerbook G3 has slot-names property instead */1378 slots = of_get_property(np, "slot-names", &len);1379 if (slots && slots->count > 0) {1380 if (strcmp(slots->name, "IrDA") == 0)1381 uap->flags |= PMACZILOG_FLAG_IS_IRDA;1382 else if (strcmp(slots->name, "Modem") == 0)1383 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;1384 }1385 if (ZS_IS_IRDA(uap))1386 uap->port_type = PMAC_SCC_IRDA;1387 if (ZS_IS_INTMODEM(uap)) {1388 struct device_node* i2c_modem =1389 of_find_node_by_name(NULL, "i2c-modem");1390 if (i2c_modem) {1391 const char* mid =1392 of_get_property(i2c_modem, "modem-id", NULL);1393 if (mid) switch(*mid) {1394 case 0x04 :1395 case 0x05 :1396 case 0x07 :1397 case 0x08 :1398 case 0x0b :1399 case 0x0c :1400 uap->port_type = PMAC_SCC_I2S1;1401 }1402 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",1403 mid ? (*mid) : 0);1404 of_node_put(i2c_modem);1405 } else {1406 printk(KERN_INFO "pmac_zilog: serial modem detected\n");1407 }1408 }1409 1410 /*1411 * Init remaining bits of "port" structure1412 */1413 uap->port.iotype = UPIO_MEM;1414 uap->port.irq = irq_of_parse_and_map(np, 0);1415 uap->port.uartclk = ZS_CLOCK;1416 uap->port.fifosize = 1;1417 uap->port.ops = &pmz_pops;1418 uap->port.type = PORT_PMAC_ZILOG;1419 uap->port.flags = 0;1420 1421 /*1422 * Fixup for the port on Gatwick for which the device-tree has1423 * missing interrupts. Normally, the macio_dev would contain1424 * fixed up interrupt info, but we use the device-tree directly1425 * here due to early probing so we need the fixup too.1426 */1427 if (uap->port.irq == 0 &&1428 np->parent && np->parent->parent &&1429 of_device_is_compatible(np->parent->parent, "gatwick")) {1430 /* IRQs on gatwick are offset by 64 */1431 uap->port.irq = irq_create_mapping(NULL, 64 + 15);1432 }1433 1434 /* Setup some valid baud rate information in the register1435 * shadows so we don't write crap there before baud rate is1436 * first initialized.1437 */1438 pmz_convert_to_zs(uap, CS8, 0, 9600);1439 1440 return 0;1441}1442 1443/*1444 * Get rid of a port on module removal1445 */1446static void pmz_dispose_port(struct uart_pmac_port *uap)1447{1448 struct device_node *np;1449 1450 np = uap->node;1451 iounmap(uap->control_reg);1452 uap->node = NULL;1453 of_node_put(np);1454 memset(uap, 0, sizeof(struct uart_pmac_port));1455}1456 1457/*1458 * Called upon match with an escc node in the device-tree.1459 */1460static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)1461{1462 struct uart_pmac_port *uap;1463 int i;1464 1465 /* Iterate the pmz_ports array to find a matching entry1466 */1467 for (i = 0; i < MAX_ZS_PORTS; i++)1468 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)1469 break;1470 if (i >= MAX_ZS_PORTS)1471 return -ENODEV;1472 1473 1474 uap = &pmz_ports[i];1475 uap->dev = mdev;1476 uap->port.dev = &mdev->ofdev.dev;1477 dev_set_drvdata(&mdev->ofdev.dev, uap);1478 1479 /* We still activate the port even when failing to request resources1480 * to work around bugs in ancient Apple device-trees1481 */1482 if (macio_request_resources(uap->dev, "pmac_zilog"))1483 printk(KERN_WARNING "%pOFn: Failed to request resource"1484 ", port still active\n",1485 uap->node);1486 else1487 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;1488 1489 return uart_add_one_port(&pmz_uart_reg, &uap->port);1490}1491 1492/*1493 * That one should not be called, macio isn't really a hotswap device,1494 * we don't expect one of those serial ports to go away...1495 */1496static void pmz_detach(struct macio_dev *mdev)1497{1498 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);1499 1500 if (!uap)1501 return;1502 1503 uart_remove_one_port(&pmz_uart_reg, &uap->port);1504 1505 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {1506 macio_release_resources(uap->dev);1507 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;1508 }1509 dev_set_drvdata(&mdev->ofdev.dev, NULL);1510 uap->dev = NULL;1511 uap->port.dev = NULL;1512}1513 1514static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)1515{1516 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);1517 1518 if (uap == NULL) {1519 printk("HRM... pmz_suspend with NULL uap\n");1520 return 0;1521 }1522 1523 uart_suspend_port(&pmz_uart_reg, &uap->port);1524 1525 return 0;1526}1527 1528 1529static int pmz_resume(struct macio_dev *mdev)1530{1531 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);1532 1533 if (uap == NULL)1534 return 0;1535 1536 uart_resume_port(&pmz_uart_reg, &uap->port);1537 1538 return 0;1539}1540 1541/*1542 * Probe all ports in the system and build the ports array, we register1543 * with the serial layer later, so we get a proper struct device which1544 * allows the tty to attach properly. This is later than it used to be1545 * but the tty layer really wants it that way.1546 */1547static int __init pmz_probe(void)1548{1549 struct device_node *node_p, *node_a, *node_b, *np;1550 int count = 0;1551 int rc;1552 1553 /*1554 * Find all escc chips in the system1555 */1556 for_each_node_by_name(node_p, "escc") {1557 /*1558 * First get channel A/B node pointers1559 * 1560 * TODO: Add routines with proper locking to do that...1561 */1562 node_a = node_b = NULL;1563 for_each_child_of_node(node_p, np) {1564 if (of_node_name_prefix(np, "ch-a"))1565 node_a = of_node_get(np);1566 else if (of_node_name_prefix(np, "ch-b"))1567 node_b = of_node_get(np);1568 }1569 if (!node_a && !node_b) {1570 of_node_put(node_a);1571 of_node_put(node_b);1572 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",1573 (!node_a) ? 'a' : 'b', node_p);1574 continue;1575 }1576 1577 /*1578 * Fill basic fields in the port structures1579 */1580 if (node_b != NULL) {1581 pmz_ports[count].mate = &pmz_ports[count+1];1582 pmz_ports[count+1].mate = &pmz_ports[count];1583 }1584 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;1585 pmz_ports[count].node = node_a;1586 pmz_ports[count+1].node = node_b;1587 pmz_ports[count].port.line = count;1588 pmz_ports[count+1].port.line = count+1;1589 1590 /*1591 * Setup the ports for real1592 */1593 rc = pmz_init_port(&pmz_ports[count]);1594 if (rc == 0 && node_b != NULL)1595 rc = pmz_init_port(&pmz_ports[count+1]);1596 if (rc != 0) {1597 of_node_put(node_a);1598 of_node_put(node_b);1599 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));1600 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));1601 continue;1602 }1603 count += 2;1604 }1605 pmz_ports_count = count;1606 1607 return 0;1608}1609 1610#else1611 1612/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware1613 * tree to obtain the device_nodes needed to start the console before the1614 * macio driver. On Macs without OpenFirmware, global platform_devices take1615 * the place of those device_nodes.1616 */1617extern struct platform_device scc_a_pdev, scc_b_pdev;1618 1619static int __init pmz_init_port(struct uart_pmac_port *uap)1620{1621 struct resource *r_ports;1622 int irq;1623 1624 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);1625 if (!r_ports)1626 return -ENODEV;1627 1628 irq = platform_get_irq(uap->pdev, 0);1629 if (irq < 0)1630 return irq;1631 1632 uap->port.mapbase = r_ports->start;1633 uap->port.membase = (unsigned char __iomem *) r_ports->start;1634 uap->port.iotype = UPIO_MEM;1635 uap->port.irq = irq;1636 uap->port.uartclk = ZS_CLOCK;1637 uap->port.fifosize = 1;1638 uap->port.ops = &pmz_pops;1639 uap->port.type = PORT_PMAC_ZILOG;1640 uap->port.flags = 0;1641 1642 uap->control_reg = uap->port.membase;1643 uap->data_reg = uap->control_reg + 4;1644 uap->port_type = 0;1645 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);1646 1647 pmz_convert_to_zs(uap, CS8, 0, 9600);1648 1649 return 0;1650}1651 1652static int __init pmz_probe(void)1653{1654 int err;1655 1656 pmz_ports_count = 0;1657 1658 pmz_ports[0].port.line = 0;1659 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;1660 pmz_ports[0].pdev = &scc_a_pdev;1661 err = pmz_init_port(&pmz_ports[0]);1662 if (err)1663 return err;1664 pmz_ports_count++;1665 1666 pmz_ports[0].mate = &pmz_ports[1];1667 pmz_ports[1].mate = &pmz_ports[0];1668 pmz_ports[1].port.line = 1;1669 pmz_ports[1].flags = 0;1670 pmz_ports[1].pdev = &scc_b_pdev;1671 err = pmz_init_port(&pmz_ports[1]);1672 if (err)1673 return err;1674 pmz_ports_count++;1675 1676 return 0;1677}1678 1679static void pmz_dispose_port(struct uart_pmac_port *uap)1680{1681 memset(uap, 0, sizeof(struct uart_pmac_port));1682}1683 1684static int pmz_attach(struct platform_device *pdev)1685{1686 struct uart_pmac_port *uap;1687 int i;1688 1689 /* Iterate the pmz_ports array to find a matching entry */1690 for (i = 0; i < pmz_ports_count; i++)1691 if (pmz_ports[i].pdev == pdev)1692 break;1693 if (i >= pmz_ports_count)1694 return -ENODEV;1695 1696 uap = &pmz_ports[i];1697 uap->port.dev = &pdev->dev;1698 platform_set_drvdata(pdev, uap);1699 1700 return uart_add_one_port(&pmz_uart_reg, &uap->port);1701}1702 1703static void pmz_detach(struct platform_device *pdev)1704{1705 struct uart_pmac_port *uap = platform_get_drvdata(pdev);1706 1707 uart_remove_one_port(&pmz_uart_reg, &uap->port);1708 1709 uap->port.dev = NULL;1710}1711 1712#endif /* !CONFIG_PPC_PMAC */1713 1714#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE1715 1716static void pmz_console_write(struct console *con, const char *s, unsigned int count);1717static int __init pmz_console_setup(struct console *co, char *options);1718 1719static struct console pmz_console = {1720 .name = PMACZILOG_NAME,1721 .write = pmz_console_write,1722 .device = uart_console_device,1723 .setup = pmz_console_setup,1724 .flags = CON_PRINTBUFFER,1725 .index = -1,1726 .data = &pmz_uart_reg,1727};1728 1729#define PMACZILOG_CONSOLE &pmz_console1730#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */1731#define PMACZILOG_CONSOLE (NULL)1732#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */1733 1734/*1735 * Register the driver, console driver and ports with the serial1736 * core1737 */1738static int __init pmz_register(void)1739{1740 pmz_uart_reg.nr = pmz_ports_count;1741 pmz_uart_reg.cons = PMACZILOG_CONSOLE;1742 1743 /*1744 * Register this driver with the serial core1745 */1746 return uart_register_driver(&pmz_uart_reg);1747}1748 1749#ifdef CONFIG_PPC_PMAC1750 1751static const struct of_device_id pmz_match[] =1752{1753 {1754 .name = "ch-a",1755 },1756 {1757 .name = "ch-b",1758 },1759 {},1760};1761MODULE_DEVICE_TABLE (of, pmz_match);1762 1763static struct macio_driver pmz_driver = {1764 .driver = {1765 .name = "pmac_zilog",1766 .owner = THIS_MODULE,1767 .of_match_table = pmz_match,1768 },1769 .probe = pmz_attach,1770 .remove = pmz_detach,1771 .suspend = pmz_suspend,1772 .resume = pmz_resume,1773};1774 1775#else1776 1777static struct platform_driver pmz_driver = {1778 .probe = pmz_attach,1779 .remove_new = pmz_detach,1780 .driver = {1781 .name = "scc",1782 },1783};1784 1785#endif /* !CONFIG_PPC_PMAC */1786 1787static int __init init_pmz(void)1788{1789 int rc, i;1790 1791 /* 1792 * First, we need to do a direct OF-based probe pass. We1793 * do that because we want serial console up before the1794 * macio stuffs calls us back, and since that makes it1795 * easier to pass the proper number of channels to1796 * uart_register_driver()1797 */1798 if (pmz_ports_count == 0)1799 pmz_probe();1800 1801 /*1802 * Bail early if no port found1803 */1804 if (pmz_ports_count == 0)1805 return -ENODEV;1806 1807 /*1808 * Now we register with the serial layer1809 */1810 rc = pmz_register();1811 if (rc) {1812 printk(KERN_ERR 1813 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"1814 "pmac_zilog: Did another serial driver already claim the minors?\n"); 1815 /* effectively "pmz_unprobe()" */1816 for (i=0; i < pmz_ports_count; i++)1817 pmz_dispose_port(&pmz_ports[i]);1818 return rc;1819 }1820 1821 /*1822 * Then we register the macio driver itself1823 */1824#ifdef CONFIG_PPC_PMAC1825 return macio_register_driver(&pmz_driver);1826#else1827 return platform_driver_register(&pmz_driver);1828#endif1829}1830 1831static void __exit exit_pmz(void)1832{1833 int i;1834 1835#ifdef CONFIG_PPC_PMAC1836 /* Get rid of macio-driver (detach from macio) */1837 macio_unregister_driver(&pmz_driver);1838#else1839 platform_driver_unregister(&pmz_driver);1840#endif1841 1842 for (i = 0; i < pmz_ports_count; i++) {1843 struct uart_pmac_port *uport = &pmz_ports[i];1844#ifdef CONFIG_PPC_PMAC1845 if (uport->node != NULL)1846 pmz_dispose_port(uport);1847#else1848 if (uport->pdev != NULL)1849 pmz_dispose_port(uport);1850#endif1851 }1852 /* Unregister UART driver */1853 uart_unregister_driver(&pmz_uart_reg);1854}1855 1856#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE1857 1858static void pmz_console_putchar(struct uart_port *port, unsigned char ch)1859{1860 struct uart_pmac_port *uap =1861 container_of(port, struct uart_pmac_port, port);1862 1863 /* Wait for the transmit buffer to empty. */1864 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)1865 udelay(5);1866 write_zsdata(uap, ch);1867}1868 1869/*1870 * Print a string to the serial port trying not to disturb1871 * any possible real use of the port...1872 */1873static void pmz_console_write(struct console *con, const char *s, unsigned int count)1874{1875 struct uart_pmac_port *uap = &pmz_ports[con->index];1876 unsigned long flags;1877 1878 uart_port_lock_irqsave(&uap->port, &flags);1879 1880 /* Turn of interrupts and enable the transmitter. */1881 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);1882 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);1883 1884 uart_console_write(&uap->port, s, count, pmz_console_putchar);1885 1886 /* Restore the values in the registers. */1887 write_zsreg(uap, R1, uap->curregs[1]);1888 /* Don't disable the transmitter. */1889 1890 uart_port_unlock_irqrestore(&uap->port, flags);1891}1892 1893/*1894 * Setup the serial console1895 */1896static int __init pmz_console_setup(struct console *co, char *options)1897{1898 struct uart_pmac_port *uap;1899 struct uart_port *port;1900 int baud = 38400;1901 int bits = 8;1902 int parity = 'n';1903 int flow = 'n';1904 unsigned long pwr_delay;1905 1906 /*1907 * XServe's default to 57600 bps1908 */1909 if (of_machine_is_compatible("RackMac1,1")1910 || of_machine_is_compatible("RackMac1,2")1911 || of_machine_is_compatible("MacRISC4"))1912 baud = 57600;1913 1914 /*1915 * Check whether an invalid uart number has been specified, and1916 * if so, search for the first available port that does have1917 * console support.1918 */1919 if (co->index >= pmz_ports_count)1920 co->index = 0;1921 uap = &pmz_ports[co->index];1922#ifdef CONFIG_PPC_PMAC1923 if (uap->node == NULL)1924 return -ENODEV;1925#else1926 if (uap->pdev == NULL)1927 return -ENODEV;1928#endif1929 port = &uap->port;1930 1931 /*1932 * Mark port as beeing a console1933 */1934 uap->flags |= PMACZILOG_FLAG_IS_CONS;1935 1936 /*1937 * Temporary fix for uart layer who didn't setup the spinlock yet1938 */1939 spin_lock_init(&port->lock);1940 1941 /*1942 * Enable the hardware1943 */1944 pwr_delay = __pmz_startup(uap);1945 if (pwr_delay)1946 mdelay(pwr_delay);1947 1948 if (options)1949 uart_parse_options(options, &baud, &parity, &bits, &flow);1950 1951 return uart_set_options(port, co, baud, parity, bits, flow);1952}1953 1954static int __init pmz_console_init(void)1955{1956 /* Probe ports */1957 pmz_probe();1958 1959 if (pmz_ports_count == 0)1960 return -ENODEV;1961 1962 /* TODO: Autoprobe console based on OF */1963 /* pmz_console.index = i; */1964 register_console(&pmz_console);1965 1966 return 0;1967 1968}1969console_initcall(pmz_console_init);1970#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */1971 1972module_init(init_pmz);1973module_exit(exit_pmz);1974