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1// SPDX-License-Identifier: GPL-2.0+2/*3 * SC16IS7xx tty serial driver - common code4 *5 * Copyright (C) 2014 GridPoint6 * Author: Jon Ringle <jringle@gridpoint.com>7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>8 */9 10#undef DEFAULT_SYMBOL_NAMESPACE11#define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX12 13#include <linux/bits.h>14#include <linux/clk.h>15#include <linux/delay.h>16#include <linux/device.h>17#include <linux/export.h>18#include <linux/gpio/consumer.h>19#include <linux/gpio/driver.h>20#include <linux/idr.h>21#include <linux/kthread.h>22#include <linux/mod_devicetable.h>23#include <linux/module.h>24#include <linux/property.h>25#include <linux/regmap.h>26#include <linux/sched.h>27#include <linux/serial_core.h>28#include <linux/serial.h>29#include <linux/string.h>30#include <linux/tty.h>31#include <linux/tty_flip.h>32#include <linux/uaccess.h>33#include <linux/units.h>34 35#include "sc16is7xx.h"36 37#define SC16IS7XX_MAX_DEVS 838 39/* SC16IS7XX register definitions */40#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */41#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */42#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */43#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */44#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */45#define SC16IS7XX_LCR_REG (0x03) /* Line Control */46#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */47#define SC16IS7XX_LSR_REG (0x05) /* Line Status */48#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */49#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */50#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */51#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */52#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction53 * - only on 75x/76x54 */55#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State56 * - only on 75x/76x57 */58#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable59 * - only on 75x/76x60 */61#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control62 * - only on 75x/76x63 */64#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */65 66/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */67#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */68#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */69 70/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */71#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */72#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */73 74/* Enhanced Register set: Only if (LCR == 0xBF) */75#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */76#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */77#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */78#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */79#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */80 81/* IER register bits */82#define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */83#define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register84 * interrupt */85#define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status86 * interrupt */87#define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status88 * interrupt */89 90/* IER register bits - write only if (EFR[4] == 1) */91#define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */92#define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */93#define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */94#define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */95 96/* FCR register bits */97#define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */98#define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */99#define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */100#define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */101#define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */102 103/* FCR register bits - write only if (EFR[4] == 1) */104#define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */105#define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */106 107/* IIR register bits */108#define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */109#define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */110#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */111#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */112#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */113#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */114#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt115 * - only on 75x/76x116 */117#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state118 * - only on 75x/76x119 */120#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */121#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state122 * from active (LOW)123 * to inactive (HIGH)124 */125/* LCR register bits */126#define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */127#define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1128 *129 * Word length bits table:130 * 00 -> 5 bit words131 * 01 -> 6 bit words132 * 10 -> 7 bit words133 * 11 -> 8 bit words134 */135#define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit136 *137 * STOP length bit table:138 * 0 -> 1 stop bit139 * 1 -> 1-1.5 stop bits if140 * word length is 5,141 * 2 stop bits otherwise142 */143#define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */144#define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */145#define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */146#define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */147#define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */148#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)149#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)150#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)151#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)152#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special153 * reg set */154#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced155 * reg set */156 157/* MCR register bits */158#define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement159 * - only on 75x/76x160 */161#define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */162#define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */163#define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */164#define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any165 * - write enabled166 * if (EFR[4] == 1)167 */168#define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode169 * - write enabled170 * if (EFR[4] == 1)171 */172#define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4173 * - write enabled174 * if (EFR[4] == 1)175 */176 177/* LSR register bits */178#define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */179#define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */180#define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */181#define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */182#define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */183#define SC16IS7XX_LSR_BRK_ERROR_MASK \184 (SC16IS7XX_LSR_OE_BIT | \185 SC16IS7XX_LSR_PE_BIT | \186 SC16IS7XX_LSR_FE_BIT | \187 SC16IS7XX_LSR_BI_BIT)188 189#define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */190#define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */191#define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */192 193/* MSR register bits */194#define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */195#define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready196 * or (IO4)197 * - only on 75x/76x198 */199#define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator200 * or (IO7)201 * - only on 75x/76x202 */203#define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect204 * or (IO6)205 * - only on 75x/76x206 */207#define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */208#define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4)209 * - only on 75x/76x210 */211#define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7)212 * - only on 75x/76x213 */214#define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6)215 * - only on 75x/76x216 */217 218/*219 * TCR register bits220 * TCR trigger levels are available from 0 to 60 characters with a granularity221 * of four.222 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is223 * no built-in hardware check to make sure this condition is met. Also, the TCR224 * must be programmed with this condition before auto RTS or software flow225 * control is enabled to avoid spurious operation of the device.226 */227#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)228#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)229 230/*231 * TLR register bits232 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the233 * FIFO Control Register (FCR) are used for the transmit and receive FIFO234 * trigger levels. Trigger levels from 4 characters to 60 characters are235 * available with a granularity of four.236 *237 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the238 * trigger level setting defined in FCR. If TLR has non-zero trigger level value239 * the trigger level defined in FCR is discarded. This applies to both transmit240 * FIFO and receive FIFO trigger level setting.241 *242 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the243 * default state, that is, '00'.244 */245#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)246#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)247 248/* IOControl register bits (Only 75x/76x) */249#define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */250#define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */251#define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */252#define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */253 254/* EFCR register bits */255#define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop256 * mode (RS485) */257#define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */258#define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */259#define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */260#define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */261#define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode262 * 0 = rate upto 115.2 kbit/s263 * - Only 75x/76x264 * 1 = rate upto 1.152 Mbit/s265 * - Only 76x266 */267 268/* EFR register bits */269#define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */270#define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */271#define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */272#define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions273 * and writing to IER[7:4],274 * FCR[5:4], MCR[7:5]275 */276#define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)277#define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)278 /*279 * SWFLOW bits 3 & 2 table:280 * 00 -> no transmitter flow281 * control282 * 01 -> transmitter generates283 * XON2 and XOFF2284 * 10 -> transmitter generates285 * XON1 and XOFF1286 * 11 -> transmitter generates287 * XON1, XON2, XOFF1 and288 * XOFF2289 */290#define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)291#define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)292 /*293 * SWFLOW bits 1 & 0 table:294 * 00 -> no received flow295 * control296 * 01 -> receiver compares297 * XON2 and XOFF2298 * 10 -> receiver compares299 * XON1 and XOFF1300 * 11 -> receiver compares301 * XON1, XON2, XOFF1 and302 * XOFF2303 */304#define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \305 SC16IS7XX_EFR_AUTOCTS_BIT | \306 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \307 SC16IS7XX_EFR_SWFLOW3_BIT | \308 SC16IS7XX_EFR_SWFLOW2_BIT | \309 SC16IS7XX_EFR_SWFLOW1_BIT | \310 SC16IS7XX_EFR_SWFLOW0_BIT)311 312 313/* Misc definitions */314#define SC16IS7XX_FIFO_SIZE (64)315#define SC16IS7XX_GPIOS_PER_BANK 4316 317#define SC16IS7XX_RECONF_MD BIT(0)318#define SC16IS7XX_RECONF_IER BIT(1)319#define SC16IS7XX_RECONF_RS485 BIT(2)320 321struct sc16is7xx_one_config {322 unsigned int flags;323 u8 ier_mask;324 u8 ier_val;325};326 327struct sc16is7xx_one {328 struct uart_port port;329 struct regmap *regmap;330 struct mutex efr_lock; /* EFR registers access */331 struct kthread_work tx_work;332 struct kthread_work reg_work;333 struct kthread_delayed_work ms_work;334 struct sc16is7xx_one_config config;335 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */336 unsigned int old_mctrl;337 u8 old_lcr; /* Value before EFR access. */338 bool irda_mode;339};340 341struct sc16is7xx_port {342 const struct sc16is7xx_devtype *devtype;343 struct clk *clk;344#ifdef CONFIG_GPIOLIB345 struct gpio_chip gpio;346 unsigned long gpio_valid_mask;347#endif348 u8 mctrl_mask;349 struct kthread_worker kworker;350 struct task_struct *kworker_task;351 struct sc16is7xx_one p[];352};353 354static DEFINE_IDA(sc16is7xx_lines);355 356static struct uart_driver sc16is7xx_uart = {357 .owner = THIS_MODULE,358 .driver_name = SC16IS7XX_NAME,359 .dev_name = "ttySC",360 .nr = SC16IS7XX_MAX_DEVS,361};362 363#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))364 365static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)366{367 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);368 unsigned int val = 0;369 370 regmap_read(one->regmap, reg, &val);371 372 return val;373}374 375static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)376{377 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);378 379 regmap_write(one->regmap, reg, val);380}381 382static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)383{384 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);385 386 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);387}388 389static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)390{391 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);392 393 /*394 * Don't send zero-length data, at least on SPI it confuses the chip395 * delivering wrong TXLVL data.396 */397 if (unlikely(!to_send))398 return;399 400 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);401}402 403static void sc16is7xx_port_update(struct uart_port *port, u8 reg,404 u8 mask, u8 val)405{406 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);407 408 regmap_update_bits(one->regmap, reg, mask, val);409}410 411static void sc16is7xx_power(struct uart_port *port, int on)412{413 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,414 SC16IS7XX_IER_SLEEP_BIT,415 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);416}417 418/*419 * In an amazing feat of design, the Enhanced Features Register (EFR)420 * shares the address of the Interrupt Identification Register (IIR).421 * Access to EFR is switched on by writing a magic value (0xbf) to the422 * Line Control Register (LCR). Any interrupt firing during this time will423 * see the EFR where it expects the IIR to be, leading to424 * "Unexpected interrupt" messages.425 *426 * Prevent this possibility by claiming a mutex while accessing the EFR,427 * and claiming the same mutex from within the interrupt handler. This is428 * similar to disabling the interrupt, but that doesn't work because the429 * bulk of the interrupt processing is run as a workqueue job in thread430 * context.431 */432static void sc16is7xx_efr_lock(struct uart_port *port)433{434 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);435 436 mutex_lock(&one->efr_lock);437 438 /* Backup content of LCR. */439 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);440 441 /* Enable access to Enhanced register set */442 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B);443 444 /* Disable cache updates when writing to EFR registers */445 regcache_cache_bypass(one->regmap, true);446}447 448static void sc16is7xx_efr_unlock(struct uart_port *port)449{450 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);451 452 /* Re-enable cache updates when writing to normal registers */453 regcache_cache_bypass(one->regmap, false);454 455 /* Restore original content of LCR */456 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);457 458 mutex_unlock(&one->efr_lock);459}460 461static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)462{463 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);464 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);465 466 lockdep_assert_held_once(&port->lock);467 468 one->config.flags |= SC16IS7XX_RECONF_IER;469 one->config.ier_mask |= bit;470 one->config.ier_val &= ~bit;471 kthread_queue_work(&s->kworker, &one->reg_work);472}473 474static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)475{476 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);477 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);478 479 lockdep_assert_held_once(&port->lock);480 481 one->config.flags |= SC16IS7XX_RECONF_IER;482 one->config.ier_mask |= bit;483 one->config.ier_val |= bit;484 kthread_queue_work(&s->kworker, &one->reg_work);485}486 487static void sc16is7xx_stop_tx(struct uart_port *port)488{489 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);490}491 492static void sc16is7xx_stop_rx(struct uart_port *port)493{494 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);495}496 497const struct sc16is7xx_devtype sc16is74x_devtype = {498 .name = "SC16IS74X",499 .nr_gpio = 0,500 .nr_uart = 1,501};502EXPORT_SYMBOL_GPL(sc16is74x_devtype);503 504const struct sc16is7xx_devtype sc16is750_devtype = {505 .name = "SC16IS750",506 .nr_gpio = 8,507 .nr_uart = 1,508};509EXPORT_SYMBOL_GPL(sc16is750_devtype);510 511const struct sc16is7xx_devtype sc16is752_devtype = {512 .name = "SC16IS752",513 .nr_gpio = 8,514 .nr_uart = 2,515};516EXPORT_SYMBOL_GPL(sc16is752_devtype);517 518const struct sc16is7xx_devtype sc16is760_devtype = {519 .name = "SC16IS760",520 .nr_gpio = 8,521 .nr_uart = 1,522};523EXPORT_SYMBOL_GPL(sc16is760_devtype);524 525const struct sc16is7xx_devtype sc16is762_devtype = {526 .name = "SC16IS762",527 .nr_gpio = 8,528 .nr_uart = 2,529};530EXPORT_SYMBOL_GPL(sc16is762_devtype);531 532static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)533{534 switch (reg) {535 case SC16IS7XX_RHR_REG:536 case SC16IS7XX_IIR_REG:537 case SC16IS7XX_LSR_REG:538 case SC16IS7XX_MSR_REG:539 case SC16IS7XX_TXLVL_REG:540 case SC16IS7XX_RXLVL_REG:541 case SC16IS7XX_IOSTATE_REG:542 case SC16IS7XX_IOCONTROL_REG:543 return true;544 default:545 return false;546 }547}548 549static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)550{551 switch (reg) {552 case SC16IS7XX_RHR_REG:553 return true;554 default:555 return false;556 }557}558 559static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)560{561 return reg == SC16IS7XX_RHR_REG;562}563 564/*565 * Configure programmable baud rate generator (divisor) according to the566 * desired baud rate.567 *568 * From the datasheet, the divisor is computed according to:569 *570 * XTAL1 input frequency571 * -----------------------572 * prescaler573 * divisor = ---------------------------574 * baud-rate x sampling-rate575 */576static int sc16is7xx_set_baud(struct uart_port *port, int baud)577{578 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);579 u8 lcr;580 unsigned int prescaler = 1;581 unsigned long clk = port->uartclk, div = clk / 16 / baud;582 583 if (div >= BIT(16)) {584 prescaler = 4;585 div /= prescaler;586 }587 588 /* Enable enhanced features */589 sc16is7xx_efr_lock(port);590 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,591 SC16IS7XX_EFR_ENABLE_BIT,592 SC16IS7XX_EFR_ENABLE_BIT);593 sc16is7xx_efr_unlock(port);594 595 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */596 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,597 SC16IS7XX_MCR_CLKSEL_BIT,598 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);599 600 mutex_lock(&one->efr_lock);601 602 /* Backup LCR and access special register set (DLL/DLH) */603 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);604 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,605 SC16IS7XX_LCR_CONF_MODE_A);606 607 /* Write the new divisor */608 regcache_cache_bypass(one->regmap, true);609 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);610 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);611 regcache_cache_bypass(one->regmap, false);612 613 /* Restore LCR and access to general register set */614 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);615 616 mutex_unlock(&one->efr_lock);617 618 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);619}620 621static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,622 unsigned int iir)623{624 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);625 unsigned int lsr = 0, bytes_read, i;626 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;627 u8 ch, flag;628 629 if (unlikely(rxlen >= sizeof(one->buf))) {630 dev_warn_ratelimited(port->dev,631 "ttySC%i: Possible RX FIFO overrun: %d\n",632 port->line, rxlen);633 port->icount.buf_overrun++;634 /* Ensure sanity of RX level */635 rxlen = sizeof(one->buf);636 }637 638 while (rxlen) {639 /* Only read lsr if there are possible errors in FIFO */640 if (read_lsr) {641 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);642 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))643 read_lsr = false; /* No errors left in FIFO */644 } else645 lsr = 0;646 647 if (read_lsr) {648 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);649 bytes_read = 1;650 } else {651 sc16is7xx_fifo_read(port, one->buf, rxlen);652 bytes_read = rxlen;653 }654 655 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;656 657 port->icount.rx++;658 flag = TTY_NORMAL;659 660 if (unlikely(lsr)) {661 if (lsr & SC16IS7XX_LSR_BI_BIT) {662 port->icount.brk++;663 if (uart_handle_break(port))664 continue;665 } else if (lsr & SC16IS7XX_LSR_PE_BIT)666 port->icount.parity++;667 else if (lsr & SC16IS7XX_LSR_FE_BIT)668 port->icount.frame++;669 else if (lsr & SC16IS7XX_LSR_OE_BIT)670 port->icount.overrun++;671 672 lsr &= port->read_status_mask;673 if (lsr & SC16IS7XX_LSR_BI_BIT)674 flag = TTY_BREAK;675 else if (lsr & SC16IS7XX_LSR_PE_BIT)676 flag = TTY_PARITY;677 else if (lsr & SC16IS7XX_LSR_FE_BIT)678 flag = TTY_FRAME;679 else if (lsr & SC16IS7XX_LSR_OE_BIT)680 flag = TTY_OVERRUN;681 }682 683 for (i = 0; i < bytes_read; ++i) {684 ch = one->buf[i];685 if (uart_handle_sysrq_char(port, ch))686 continue;687 688 if (lsr & port->ignore_status_mask)689 continue;690 691 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,692 flag);693 }694 rxlen -= bytes_read;695 }696 697 tty_flip_buffer_push(&port->state->port);698}699 700static void sc16is7xx_handle_tx(struct uart_port *port)701{702 struct tty_port *tport = &port->state->port;703 unsigned long flags;704 unsigned int txlen;705 unsigned char *tail;706 707 if (unlikely(port->x_char)) {708 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);709 port->icount.tx++;710 port->x_char = 0;711 return;712 }713 714 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {715 uart_port_lock_irqsave(port, &flags);716 sc16is7xx_stop_tx(port);717 uart_port_unlock_irqrestore(port, flags);718 return;719 }720 721 /* Limit to space available in TX FIFO */722 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);723 if (txlen > SC16IS7XX_FIFO_SIZE) {724 dev_err_ratelimited(port->dev,725 "chip reports %d free bytes in TX fifo, but it only has %d",726 txlen, SC16IS7XX_FIFO_SIZE);727 txlen = 0;728 }729 730 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);731 sc16is7xx_fifo_write(port, tail, txlen);732 uart_xmit_advance(port, txlen);733 734 uart_port_lock_irqsave(port, &flags);735 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)736 uart_write_wakeup(port);737 738 if (kfifo_is_empty(&tport->xmit_fifo))739 sc16is7xx_stop_tx(port);740 else741 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);742 uart_port_unlock_irqrestore(port, flags);743}744 745static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)746{747 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);748 unsigned int mctrl = 0;749 750 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;751 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;752 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;753 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;754 return mctrl;755}756 757static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)758{759 struct uart_port *port = &one->port;760 unsigned long flags;761 unsigned int status, changed;762 763 lockdep_assert_held_once(&one->efr_lock);764 765 status = sc16is7xx_get_hwmctrl(port);766 changed = status ^ one->old_mctrl;767 768 if (changed == 0)769 return;770 771 one->old_mctrl = status;772 773 uart_port_lock_irqsave(port, &flags);774 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))775 port->icount.rng++;776 if (changed & TIOCM_DSR)777 port->icount.dsr++;778 if (changed & TIOCM_CAR)779 uart_handle_dcd_change(port, status & TIOCM_CAR);780 if (changed & TIOCM_CTS)781 uart_handle_cts_change(port, status & TIOCM_CTS);782 783 wake_up_interruptible(&port->state->port.delta_msr_wait);784 uart_port_unlock_irqrestore(port, flags);785}786 787static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)788{789 bool rc = true;790 unsigned int iir, rxlen;791 struct uart_port *port = &s->p[portno].port;792 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);793 794 mutex_lock(&one->efr_lock);795 796 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);797 if (iir & SC16IS7XX_IIR_NO_INT_BIT) {798 rc = false;799 goto out_port_irq;800 }801 802 iir &= SC16IS7XX_IIR_ID_MASK;803 804 switch (iir) {805 case SC16IS7XX_IIR_RDI_SRC:806 case SC16IS7XX_IIR_RLSE_SRC:807 case SC16IS7XX_IIR_RTOI_SRC:808 case SC16IS7XX_IIR_XOFFI_SRC:809 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);810 811 /*812 * There is a silicon bug that makes the chip report a813 * time-out interrupt but no data in the FIFO. This is814 * described in errata section 18.1.4.815 *816 * When this happens, read one byte from the FIFO to817 * clear the interrupt.818 */819 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)820 rxlen = 1;821 822 if (rxlen)823 sc16is7xx_handle_rx(port, rxlen, iir);824 break;825 /* CTSRTS interrupt comes only when CTS goes inactive */826 case SC16IS7XX_IIR_CTSRTS_SRC:827 case SC16IS7XX_IIR_MSI_SRC:828 sc16is7xx_update_mlines(one);829 break;830 case SC16IS7XX_IIR_THRI_SRC:831 sc16is7xx_handle_tx(port);832 break;833 default:834 dev_err_ratelimited(port->dev,835 "ttySC%i: Unexpected interrupt: %x",836 port->line, iir);837 break;838 }839 840out_port_irq:841 mutex_unlock(&one->efr_lock);842 843 return rc;844}845 846static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)847{848 bool keep_polling;849 850 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;851 852 do {853 int i;854 855 keep_polling = false;856 857 for (i = 0; i < s->devtype->nr_uart; ++i)858 keep_polling |= sc16is7xx_port_irq(s, i);859 } while (keep_polling);860 861 return IRQ_HANDLED;862}863 864static void sc16is7xx_tx_proc(struct kthread_work *ws)865{866 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);867 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);868 869 if ((port->rs485.flags & SER_RS485_ENABLED) &&870 (port->rs485.delay_rts_before_send > 0))871 msleep(port->rs485.delay_rts_before_send);872 873 mutex_lock(&one->efr_lock);874 sc16is7xx_handle_tx(port);875 mutex_unlock(&one->efr_lock);876}877 878static void sc16is7xx_reconf_rs485(struct uart_port *port)879{880 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |881 SC16IS7XX_EFCR_RTS_INVERT_BIT;882 u32 efcr = 0;883 struct serial_rs485 *rs485 = &port->rs485;884 unsigned long irqflags;885 886 uart_port_lock_irqsave(port, &irqflags);887 if (rs485->flags & SER_RS485_ENABLED) {888 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;889 890 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)891 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;892 }893 uart_port_unlock_irqrestore(port, irqflags);894 895 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);896}897 898static void sc16is7xx_reg_proc(struct kthread_work *ws)899{900 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);901 struct sc16is7xx_one_config config;902 unsigned long irqflags;903 904 uart_port_lock_irqsave(&one->port, &irqflags);905 config = one->config;906 memset(&one->config, 0, sizeof(one->config));907 uart_port_unlock_irqrestore(&one->port, irqflags);908 909 if (config.flags & SC16IS7XX_RECONF_MD) {910 u8 mcr = 0;911 912 /* Device ignores RTS setting when hardware flow is enabled */913 if (one->port.mctrl & TIOCM_RTS)914 mcr |= SC16IS7XX_MCR_RTS_BIT;915 916 if (one->port.mctrl & TIOCM_DTR)917 mcr |= SC16IS7XX_MCR_DTR_BIT;918 919 if (one->port.mctrl & TIOCM_LOOP)920 mcr |= SC16IS7XX_MCR_LOOP_BIT;921 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,922 SC16IS7XX_MCR_RTS_BIT |923 SC16IS7XX_MCR_DTR_BIT |924 SC16IS7XX_MCR_LOOP_BIT,925 mcr);926 }927 928 if (config.flags & SC16IS7XX_RECONF_IER)929 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,930 config.ier_mask, config.ier_val);931 932 if (config.flags & SC16IS7XX_RECONF_RS485)933 sc16is7xx_reconf_rs485(&one->port);934}935 936static void sc16is7xx_ms_proc(struct kthread_work *ws)937{938 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);939 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);940 941 if (one->port.state) {942 mutex_lock(&one->efr_lock);943 sc16is7xx_update_mlines(one);944 mutex_unlock(&one->efr_lock);945 946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);947 }948}949 950static void sc16is7xx_enable_ms(struct uart_port *port)951{952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);953 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);954 955 lockdep_assert_held_once(&port->lock);956 957 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);958}959 960static void sc16is7xx_start_tx(struct uart_port *port)961{962 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);963 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);964 965 kthread_queue_work(&s->kworker, &one->tx_work);966}967 968static void sc16is7xx_throttle(struct uart_port *port)969{970 unsigned long flags;971 972 /*973 * Hardware flow control is enabled and thus the device ignores RTS974 * value set in MCR register. Stop reading data from RX FIFO so the975 * AutoRTS feature will de-activate RTS output.976 */977 uart_port_lock_irqsave(port, &flags);978 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);979 uart_port_unlock_irqrestore(port, flags);980}981 982static void sc16is7xx_unthrottle(struct uart_port *port)983{984 unsigned long flags;985 986 uart_port_lock_irqsave(port, &flags);987 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);988 uart_port_unlock_irqrestore(port, flags);989}990 991static unsigned int sc16is7xx_tx_empty(struct uart_port *port)992{993 unsigned int lsr;994 995 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);996 997 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;998}999 1000static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)1001{1002 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1003 1004 /* Called with port lock taken so we can only return cached value */1005 return one->old_mctrl;1006}1007 1008static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)1009{1010 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);1011 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1012 1013 one->config.flags |= SC16IS7XX_RECONF_MD;1014 kthread_queue_work(&s->kworker, &one->reg_work);1015}1016 1017static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)1018{1019 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,1020 SC16IS7XX_LCR_TXBREAK_BIT,1021 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);1022}1023 1024static void sc16is7xx_set_termios(struct uart_port *port,1025 struct ktermios *termios,1026 const struct ktermios *old)1027{1028 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1029 unsigned int lcr, flow = 0;1030 int baud;1031 unsigned long flags;1032 1033 kthread_cancel_delayed_work_sync(&one->ms_work);1034 1035 /* Mask termios capabilities we don't support */1036 termios->c_cflag &= ~CMSPAR;1037 1038 /* Word size */1039 switch (termios->c_cflag & CSIZE) {1040 case CS5:1041 lcr = SC16IS7XX_LCR_WORD_LEN_5;1042 break;1043 case CS6:1044 lcr = SC16IS7XX_LCR_WORD_LEN_6;1045 break;1046 case CS7:1047 lcr = SC16IS7XX_LCR_WORD_LEN_7;1048 break;1049 case CS8:1050 lcr = SC16IS7XX_LCR_WORD_LEN_8;1051 break;1052 default:1053 lcr = SC16IS7XX_LCR_WORD_LEN_8;1054 termios->c_cflag &= ~CSIZE;1055 termios->c_cflag |= CS8;1056 break;1057 }1058 1059 /* Parity */1060 if (termios->c_cflag & PARENB) {1061 lcr |= SC16IS7XX_LCR_PARITY_BIT;1062 if (!(termios->c_cflag & PARODD))1063 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;1064 }1065 1066 /* Stop bits */1067 if (termios->c_cflag & CSTOPB)1068 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */1069 1070 /* Set read status mask */1071 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;1072 if (termios->c_iflag & INPCK)1073 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |1074 SC16IS7XX_LSR_FE_BIT;1075 if (termios->c_iflag & (BRKINT | PARMRK))1076 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;1077 1078 /* Set status ignore mask */1079 port->ignore_status_mask = 0;1080 if (termios->c_iflag & IGNBRK)1081 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;1082 if (!(termios->c_cflag & CREAD))1083 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;1084 1085 /* Configure flow control */1086 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);1087 if (termios->c_cflag & CRTSCTS) {1088 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |1089 SC16IS7XX_EFR_AUTORTS_BIT;1090 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;1091 }1092 if (termios->c_iflag & IXON)1093 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;1094 if (termios->c_iflag & IXOFF)1095 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;1096 1097 /* Update LCR register */1098 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);1099 1100 /* Update EFR registers */1101 sc16is7xx_efr_lock(port);1102 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);1103 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);1104 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,1105 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);1106 sc16is7xx_efr_unlock(port);1107 1108 /* Get baud rate generator configuration */1109 baud = uart_get_baud_rate(port, termios, old,1110 port->uartclk / 16 / 4 / 0xffff,1111 port->uartclk / 16);1112 1113 /* Setup baudrate generator */1114 baud = sc16is7xx_set_baud(port, baud);1115 1116 uart_port_lock_irqsave(port, &flags);1117 1118 /* Update timeout according to new baud rate */1119 uart_update_timeout(port, termios->c_cflag, baud);1120 1121 if (UART_ENABLE_MS(port, termios->c_cflag))1122 sc16is7xx_enable_ms(port);1123 1124 uart_port_unlock_irqrestore(port, flags);1125}1126 1127static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,1128 struct serial_rs485 *rs485)1129{1130 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);1131 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1132 1133 if (rs485->flags & SER_RS485_ENABLED) {1134 /*1135 * RTS signal is handled by HW, it's timing can't be influenced.1136 * However, it's sometimes useful to delay TX even without RTS1137 * control therefore we try to handle .delay_rts_before_send.1138 */1139 if (rs485->delay_rts_after_send)1140 return -EINVAL;1141 }1142 1143 one->config.flags |= SC16IS7XX_RECONF_RS485;1144 kthread_queue_work(&s->kworker, &one->reg_work);1145 1146 return 0;1147}1148 1149static int sc16is7xx_startup(struct uart_port *port)1150{1151 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1152 unsigned int val;1153 unsigned long flags;1154 1155 sc16is7xx_power(port, 1);1156 1157 /* Reset FIFOs*/1158 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;1159 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);1160 udelay(5);1161 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,1162 SC16IS7XX_FCR_FIFO_BIT);1163 1164 /* Enable EFR */1165 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,1166 SC16IS7XX_LCR_CONF_MODE_B);1167 1168 regcache_cache_bypass(one->regmap, true);1169 1170 /* Enable write access to enhanced features and internal clock div */1171 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,1172 SC16IS7XX_EFR_ENABLE_BIT,1173 SC16IS7XX_EFR_ENABLE_BIT);1174 1175 /* Enable TCR/TLR */1176 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,1177 SC16IS7XX_MCR_TCRTLR_BIT,1178 SC16IS7XX_MCR_TCRTLR_BIT);1179 1180 /* Configure flow control levels */1181 /* Flow control halt level 48, resume level 24 */1182 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,1183 SC16IS7XX_TCR_RX_RESUME(24) |1184 SC16IS7XX_TCR_RX_HALT(48));1185 1186 regcache_cache_bypass(one->regmap, false);1187 1188 /* Now, initialize the UART */1189 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);1190 1191 /* Enable IrDA mode if requested in DT */1192 /* This bit must be written with LCR[7] = 0 */1193 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,1194 SC16IS7XX_MCR_IRDA_BIT,1195 one->irda_mode ?1196 SC16IS7XX_MCR_IRDA_BIT : 0);1197 1198 /* Enable the Rx and Tx FIFO */1199 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,1200 SC16IS7XX_EFCR_RXDISABLE_BIT |1201 SC16IS7XX_EFCR_TXDISABLE_BIT,1202 0);1203 1204 /* Enable RX, CTS change and modem lines interrupts */1205 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |1206 SC16IS7XX_IER_MSI_BIT;1207 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);1208 1209 /* Enable modem status polling */1210 uart_port_lock_irqsave(port, &flags);1211 sc16is7xx_enable_ms(port);1212 uart_port_unlock_irqrestore(port, flags);1213 1214 return 0;1215}1216 1217static void sc16is7xx_shutdown(struct uart_port *port)1218{1219 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);1220 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);1221 1222 kthread_cancel_delayed_work_sync(&one->ms_work);1223 1224 /* Disable all interrupts */1225 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);1226 /* Disable TX/RX */1227 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,1228 SC16IS7XX_EFCR_RXDISABLE_BIT |1229 SC16IS7XX_EFCR_TXDISABLE_BIT,1230 SC16IS7XX_EFCR_RXDISABLE_BIT |1231 SC16IS7XX_EFCR_TXDISABLE_BIT);1232 1233 sc16is7xx_power(port, 0);1234 1235 kthread_flush_worker(&s->kworker);1236}1237 1238static const char *sc16is7xx_type(struct uart_port *port)1239{1240 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);1241 1242 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;1243}1244 1245static int sc16is7xx_request_port(struct uart_port *port)1246{1247 /* Do nothing */1248 return 0;1249}1250 1251static void sc16is7xx_config_port(struct uart_port *port, int flags)1252{1253 if (flags & UART_CONFIG_TYPE)1254 port->type = PORT_SC16IS7XX;1255}1256 1257static int sc16is7xx_verify_port(struct uart_port *port,1258 struct serial_struct *s)1259{1260 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))1261 return -EINVAL;1262 if (s->irq != port->irq)1263 return -EINVAL;1264 1265 return 0;1266}1267 1268static void sc16is7xx_pm(struct uart_port *port, unsigned int state,1269 unsigned int oldstate)1270{1271 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);1272}1273 1274static void sc16is7xx_null_void(struct uart_port *port)1275{1276 /* Do nothing */1277}1278 1279static const struct uart_ops sc16is7xx_ops = {1280 .tx_empty = sc16is7xx_tx_empty,1281 .set_mctrl = sc16is7xx_set_mctrl,1282 .get_mctrl = sc16is7xx_get_mctrl,1283 .stop_tx = sc16is7xx_stop_tx,1284 .start_tx = sc16is7xx_start_tx,1285 .throttle = sc16is7xx_throttle,1286 .unthrottle = sc16is7xx_unthrottle,1287 .stop_rx = sc16is7xx_stop_rx,1288 .enable_ms = sc16is7xx_enable_ms,1289 .break_ctl = sc16is7xx_break_ctl,1290 .startup = sc16is7xx_startup,1291 .shutdown = sc16is7xx_shutdown,1292 .set_termios = sc16is7xx_set_termios,1293 .type = sc16is7xx_type,1294 .request_port = sc16is7xx_request_port,1295 .release_port = sc16is7xx_null_void,1296 .config_port = sc16is7xx_config_port,1297 .verify_port = sc16is7xx_verify_port,1298 .pm = sc16is7xx_pm,1299};1300 1301#ifdef CONFIG_GPIOLIB1302static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)1303{1304 unsigned int val;1305 struct sc16is7xx_port *s = gpiochip_get_data(chip);1306 struct uart_port *port = &s->p[0].port;1307 1308 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);1309 1310 return !!(val & BIT(offset));1311}1312 1313static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)1314{1315 struct sc16is7xx_port *s = gpiochip_get_data(chip);1316 struct uart_port *port = &s->p[0].port;1317 1318 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),1319 val ? BIT(offset) : 0);1320}1321 1322static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,1323 unsigned offset)1324{1325 struct sc16is7xx_port *s = gpiochip_get_data(chip);1326 struct uart_port *port = &s->p[0].port;1327 1328 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);1329 1330 return 0;1331}1332 1333static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,1334 unsigned offset, int val)1335{1336 struct sc16is7xx_port *s = gpiochip_get_data(chip);1337 struct uart_port *port = &s->p[0].port;1338 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);1339 1340 if (val)1341 state |= BIT(offset);1342 else1343 state &= ~BIT(offset);1344 1345 /*1346 * If we write IOSTATE first, and then IODIR, the output value is not1347 * transferred to the corresponding I/O pin.1348 * The datasheet states that each register bit will be transferred to1349 * the corresponding I/O pin programmed as output when writing to1350 * IOSTATE. Therefore, configure direction first with IODIR, and then1351 * set value after with IOSTATE.1352 */1353 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),1354 BIT(offset));1355 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);1356 1357 return 0;1358}1359 1360static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,1361 unsigned long *valid_mask,1362 unsigned int ngpios)1363{1364 struct sc16is7xx_port *s = gpiochip_get_data(chip);1365 1366 *valid_mask = s->gpio_valid_mask;1367 1368 return 0;1369}1370 1371static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)1372{1373 struct device *dev = s->p[0].port.dev;1374 1375 if (!s->devtype->nr_gpio)1376 return 0;1377 1378 switch (s->mctrl_mask) {1379 case 0:1380 s->gpio_valid_mask = GENMASK(7, 0);1381 break;1382 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:1383 s->gpio_valid_mask = GENMASK(3, 0);1384 break;1385 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:1386 s->gpio_valid_mask = GENMASK(7, 4);1387 break;1388 default:1389 break;1390 }1391 1392 if (s->gpio_valid_mask == 0)1393 return 0;1394 1395 s->gpio.owner = THIS_MODULE;1396 s->gpio.parent = dev;1397 s->gpio.label = dev_name(dev);1398 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;1399 s->gpio.direction_input = sc16is7xx_gpio_direction_input;1400 s->gpio.get = sc16is7xx_gpio_get;1401 s->gpio.direction_output = sc16is7xx_gpio_direction_output;1402 s->gpio.set = sc16is7xx_gpio_set;1403 s->gpio.base = -1;1404 s->gpio.ngpio = s->devtype->nr_gpio;1405 s->gpio.can_sleep = 1;1406 1407 return gpiochip_add_data(&s->gpio, s);1408}1409#endif1410 1411static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)1412{1413 int i;1414 int ret;1415 int count;1416 u32 irda_port[SC16IS7XX_MAX_PORTS];1417 struct device *dev = s->p[0].port.dev;1418 1419 count = device_property_count_u32(dev, "irda-mode-ports");1420 if (count < 0 || count > ARRAY_SIZE(irda_port))1421 return;1422 1423 ret = device_property_read_u32_array(dev, "irda-mode-ports",1424 irda_port, count);1425 if (ret)1426 return;1427 1428 for (i = 0; i < count; i++) {1429 if (irda_port[i] < s->devtype->nr_uart)1430 s->p[irda_port[i]].irda_mode = true;1431 }1432}1433 1434/*1435 * Configure ports designated to operate as modem control lines.1436 */1437static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,1438 struct regmap *regmap)1439{1440 int i;1441 int ret;1442 int count;1443 u32 mctrl_port[SC16IS7XX_MAX_PORTS];1444 struct device *dev = s->p[0].port.dev;1445 1446 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");1447 if (count < 0 || count > ARRAY_SIZE(mctrl_port))1448 return 0;1449 1450 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",1451 mctrl_port, count);1452 if (ret)1453 return ret;1454 1455 s->mctrl_mask = 0;1456 1457 for (i = 0; i < count; i++) {1458 /* Use GPIO lines as modem control lines */1459 if (mctrl_port[i] == 0)1460 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;1461 else if (mctrl_port[i] == 1)1462 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;1463 }1464 1465 if (s->mctrl_mask)1466 regmap_update_bits(1467 regmap,1468 SC16IS7XX_IOCONTROL_REG,1469 SC16IS7XX_IOCONTROL_MODEM_A_BIT |1470 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);1471 1472 return 0;1473}1474 1475static const struct serial_rs485 sc16is7xx_rs485_supported = {1476 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,1477 .delay_rts_before_send = 1,1478 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */1479};1480 1481/* Reset device, purging any pending irq / data */1482static int sc16is7xx_reset(struct device *dev, struct regmap *regmap)1483{1484 struct gpio_desc *reset_gpio;1485 1486 /* Assert reset GPIO if defined and valid. */1487 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);1488 if (IS_ERR(reset_gpio))1489 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n");1490 1491 if (reset_gpio) {1492 /* The minimum reset pulse width is 3 us. */1493 fsleep(5);1494 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */1495 } else {1496 /* Software reset */1497 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG,1498 SC16IS7XX_IOCONTROL_SRESET_BIT);1499 }1500 1501 return 0;1502}1503 1504int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,1505 struct regmap *regmaps[], int irq)1506{1507 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);1508 unsigned int val;1509 u32 uartclk = 0;1510 int i, ret;1511 struct sc16is7xx_port *s;1512 bool port_registered[SC16IS7XX_MAX_PORTS];1513 1514 for (i = 0; i < devtype->nr_uart; i++)1515 if (IS_ERR(regmaps[i]))1516 return PTR_ERR(regmaps[i]);1517 1518 /*1519 * This device does not have an identification register that would1520 * tell us if we are really connected to the correct device.1521 * The best we can do is to check if communication is at all possible.1522 *1523 * Note: regmap[0] is used in the probe function to access registers1524 * common to all channels/ports, as it is guaranteed to be present on1525 * all variants.1526 */1527 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);1528 if (ret < 0)1529 return -EPROBE_DEFER;1530 1531 /* Alloc port structure */1532 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);1533 if (!s) {1534 dev_err(dev, "Error allocating port structure\n");1535 return -ENOMEM;1536 }1537 1538 /* Always ask for fixed clock rate from a property. */1539 device_property_read_u32(dev, "clock-frequency", &uartclk);1540 1541 s->clk = devm_clk_get_optional(dev, NULL);1542 if (IS_ERR(s->clk))1543 return PTR_ERR(s->clk);1544 1545 ret = clk_prepare_enable(s->clk);1546 if (ret)1547 return ret;1548 1549 freq = clk_get_rate(s->clk);1550 if (freq == 0) {1551 if (uartclk)1552 freq = uartclk;1553 if (pfreq)1554 freq = *pfreq;1555 if (freq)1556 dev_dbg(dev, "Clock frequency: %luHz\n", freq);1557 else1558 return -EINVAL;1559 }1560 1561 s->devtype = devtype;1562 dev_set_drvdata(dev, s);1563 1564 kthread_init_worker(&s->kworker);1565 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,1566 "sc16is7xx");1567 if (IS_ERR(s->kworker_task)) {1568 ret = PTR_ERR(s->kworker_task);1569 goto out_clk;1570 }1571 sched_set_fifo(s->kworker_task);1572 1573 ret = sc16is7xx_reset(dev, regmaps[0]);1574 if (ret)1575 goto out_kthread;1576 1577 /* Mark each port line and status as uninitialised. */1578 for (i = 0; i < devtype->nr_uart; ++i) {1579 s->p[i].port.line = SC16IS7XX_MAX_DEVS;1580 port_registered[i] = false;1581 }1582 1583 for (i = 0; i < devtype->nr_uart; ++i) {1584 ret = ida_alloc_max(&sc16is7xx_lines,1585 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);1586 if (ret < 0)1587 goto out_ports;1588 1589 s->p[i].port.line = ret;1590 1591 /* Initialize port data */1592 s->p[i].port.dev = dev;1593 s->p[i].port.irq = irq;1594 s->p[i].port.type = PORT_SC16IS7XX;1595 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;1596 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;1597 s->p[i].port.iobase = i;1598 /*1599 * Use all ones as membase to make sure uart_configure_port() in1600 * serial_core.c does not abort for SPI/I2C devices where the1601 * membase address is not applicable.1602 */1603 s->p[i].port.membase = (void __iomem *)~0;1604 s->p[i].port.iotype = UPIO_PORT;1605 s->p[i].port.uartclk = freq;1606 s->p[i].port.rs485_config = sc16is7xx_config_rs485;1607 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;1608 s->p[i].port.ops = &sc16is7xx_ops;1609 s->p[i].old_mctrl = 0;1610 s->p[i].regmap = regmaps[i];1611 1612 mutex_init(&s->p[i].efr_lock);1613 1614 ret = uart_get_rs485_mode(&s->p[i].port);1615 if (ret)1616 goto out_ports;1617 1618 /* Disable all interrupts */1619 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);1620 /* Disable TX/RX */1621 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,1622 SC16IS7XX_EFCR_RXDISABLE_BIT |1623 SC16IS7XX_EFCR_TXDISABLE_BIT);1624 1625 /* Initialize kthread work structs */1626 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);1627 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);1628 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);1629 1630 /* Register port */1631 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);1632 if (ret)1633 goto out_ports;1634 1635 port_registered[i] = true;1636 1637 /* Enable EFR */1638 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,1639 SC16IS7XX_LCR_CONF_MODE_B);1640 1641 regcache_cache_bypass(regmaps[i], true);1642 1643 /* Enable write access to enhanced features */1644 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,1645 SC16IS7XX_EFR_ENABLE_BIT);1646 1647 regcache_cache_bypass(regmaps[i], false);1648 1649 /* Restore access to general registers */1650 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);1651 1652 /* Go to suspend mode */1653 sc16is7xx_power(&s->p[i].port, 0);1654 }1655 1656 sc16is7xx_setup_irda_ports(s);1657 1658 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);1659 if (ret)1660 goto out_ports;1661 1662#ifdef CONFIG_GPIOLIB1663 ret = sc16is7xx_setup_gpio_chip(s);1664 if (ret)1665 goto out_ports;1666#endif1667 1668 /*1669 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.1670 * If that succeeds, we can allow sharing the interrupt as well.1671 * In case the interrupt controller doesn't support that, we fall1672 * back to a non-shared falling-edge trigger.1673 */1674 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,1675 IRQF_TRIGGER_LOW | IRQF_SHARED |1676 IRQF_ONESHOT,1677 dev_name(dev), s);1678 if (!ret)1679 return 0;1680 1681 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,1682 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,1683 dev_name(dev), s);1684 if (!ret)1685 return 0;1686 1687#ifdef CONFIG_GPIOLIB1688 if (s->gpio_valid_mask)1689 gpiochip_remove(&s->gpio);1690#endif1691 1692out_ports:1693 for (i = 0; i < devtype->nr_uart; i++) {1694 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)1695 ida_free(&sc16is7xx_lines, s->p[i].port.line);1696 if (port_registered[i])1697 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);1698 }1699 1700out_kthread:1701 kthread_stop(s->kworker_task);1702 1703out_clk:1704 clk_disable_unprepare(s->clk);1705 1706 return ret;1707}1708EXPORT_SYMBOL_GPL(sc16is7xx_probe);1709 1710void sc16is7xx_remove(struct device *dev)1711{1712 struct sc16is7xx_port *s = dev_get_drvdata(dev);1713 int i;1714 1715#ifdef CONFIG_GPIOLIB1716 if (s->gpio_valid_mask)1717 gpiochip_remove(&s->gpio);1718#endif1719 1720 for (i = 0; i < s->devtype->nr_uart; i++) {1721 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);1722 ida_free(&sc16is7xx_lines, s->p[i].port.line);1723 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);1724 sc16is7xx_power(&s->p[i].port, 0);1725 }1726 1727 kthread_flush_worker(&s->kworker);1728 kthread_stop(s->kworker_task);1729 1730 clk_disable_unprepare(s->clk);1731}1732EXPORT_SYMBOL_GPL(sc16is7xx_remove);1733 1734const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {1735 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },1736 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },1737 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },1738 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },1739 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },1740 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },1741 { }1742};1743EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);1744MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);1745 1746const struct regmap_config sc16is7xx_regcfg = {1747 .reg_bits = 5,1748 .pad_bits = 3,1749 .val_bits = 8,1750 .cache_type = REGCACHE_MAPLE,1751 .volatile_reg = sc16is7xx_regmap_volatile,1752 .precious_reg = sc16is7xx_regmap_precious,1753 .writeable_noinc_reg = sc16is7xx_regmap_noinc,1754 .readable_noinc_reg = sc16is7xx_regmap_noinc,1755 .max_raw_read = SC16IS7XX_FIFO_SIZE,1756 .max_raw_write = SC16IS7XX_FIFO_SIZE,1757 .max_register = SC16IS7XX_EFCR_REG,1758};1759EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);1760 1761const char *sc16is7xx_regmap_name(u8 port_id)1762{1763 switch (port_id) {1764 case 0: return "port0";1765 case 1: return "port1";1766 default:1767 WARN_ON(true);1768 return NULL;1769 }1770}1771EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);1772 1773unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)1774{1775 /* CH1,CH0 are at bits 2:1. */1776 return port_id << 1;1777}1778EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);1779 1780static int __init sc16is7xx_init(void)1781{1782 return uart_register_driver(&sc16is7xx_uart);1783}1784module_init(sc16is7xx_init);1785 1786static void __exit sc16is7xx_exit(void)1787{1788 uart_unregister_driver(&sc16is7xx_uart);1789}1790module_exit(sc16is7xx_exit);1791 1792MODULE_LICENSE("GPL");1793MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");1794MODULE_DESCRIPTION("SC16IS7xx tty serial core driver");1795