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1// SPDX-License-Identifier: GPL-2.0+2/*3 * NXP (Philips) SCC+++(SCN+++) serial driver4 *5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>6 *7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)8 */9 10#include <linux/clk.h>11#include <linux/delay.h>12#include <linux/err.h>13#include <linux/module.h>14#include <linux/mod_devicetable.h>15#include <linux/device.h>16#include <linux/console.h>17#include <linux/serial_core.h>18#include <linux/serial.h>19#include <linux/io.h>20#include <linux/tty.h>21#include <linux/tty_flip.h>22#include <linux/spinlock.h>23#include <linux/platform_device.h>24#include <linux/platform_data/serial-sccnxp.h>25#include <linux/regulator/consumer.h>26 27#define SCCNXP_NAME "uart-sccnxp"28#define SCCNXP_MAJOR 20429#define SCCNXP_MINOR 20530 31#define SCCNXP_MR_REG (0x00)32# define MR0_BAUD_NORMAL (0 << 0)33# define MR0_BAUD_EXT1 (1 << 0)34# define MR0_BAUD_EXT2 (5 << 0)35# define MR0_FIFO (1 << 3)36# define MR0_TXLVL (1 << 4)37# define MR1_BITS_5 (0 << 0)38# define MR1_BITS_6 (1 << 0)39# define MR1_BITS_7 (2 << 0)40# define MR1_BITS_8 (3 << 0)41# define MR1_PAR_EVN (0 << 2)42# define MR1_PAR_ODD (1 << 2)43# define MR1_PAR_NO (4 << 2)44# define MR2_STOP1 (7 << 0)45# define MR2_STOP2 (0xf << 0)46#define SCCNXP_SR_REG (0x01)47# define SR_RXRDY (1 << 0)48# define SR_FULL (1 << 1)49# define SR_TXRDY (1 << 2)50# define SR_TXEMT (1 << 3)51# define SR_OVR (1 << 4)52# define SR_PE (1 << 5)53# define SR_FE (1 << 6)54# define SR_BRK (1 << 7)55#define SCCNXP_CSR_REG (SCCNXP_SR_REG)56# define CSR_TIMER_MODE (0x0d)57#define SCCNXP_CR_REG (0x02)58# define CR_RX_ENABLE (1 << 0)59# define CR_RX_DISABLE (1 << 1)60# define CR_TX_ENABLE (1 << 2)61# define CR_TX_DISABLE (1 << 3)62# define CR_CMD_MRPTR1 (0x01 << 4)63# define CR_CMD_RX_RESET (0x02 << 4)64# define CR_CMD_TX_RESET (0x03 << 4)65# define CR_CMD_STATUS_RESET (0x04 << 4)66# define CR_CMD_BREAK_RESET (0x05 << 4)67# define CR_CMD_START_BREAK (0x06 << 4)68# define CR_CMD_STOP_BREAK (0x07 << 4)69# define CR_CMD_MRPTR0 (0x0b << 4)70#define SCCNXP_RHR_REG (0x03)71#define SCCNXP_THR_REG SCCNXP_RHR_REG72#define SCCNXP_IPCR_REG (0x04)73#define SCCNXP_ACR_REG SCCNXP_IPCR_REG74# define ACR_BAUD0 (0 << 7)75# define ACR_BAUD1 (1 << 7)76# define ACR_TIMER_MODE (6 << 4)77#define SCCNXP_ISR_REG (0x05)78#define SCCNXP_IMR_REG SCCNXP_ISR_REG79# define IMR_TXRDY (1 << 0)80# define IMR_RXRDY (1 << 1)81# define ISR_TXRDY(x) (1 << ((x * 4) + 0))82# define ISR_RXRDY(x) (1 << ((x * 4) + 1))83#define SCCNXP_CTPU_REG (0x06)84#define SCCNXP_CTPL_REG (0x07)85#define SCCNXP_IPR_REG (0x0d)86#define SCCNXP_OPCR_REG SCCNXP_IPR_REG87#define SCCNXP_SOP_REG (0x0e)88#define SCCNXP_START_COUNTER_REG SCCNXP_SOP_REG89#define SCCNXP_ROP_REG (0x0f)90 91/* Route helpers */92#define MCTRL_MASK(sig) (0xf << (sig))93#define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)94#define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)95 96#define SCCNXP_HAVE_IO 0x0000000197#define SCCNXP_HAVE_MR0 0x0000000298 99struct sccnxp_chip {100 const char *name;101 unsigned int nr;102 unsigned long freq_min;103 unsigned long freq_std;104 unsigned long freq_max;105 unsigned int flags;106 unsigned int fifosize;107 /* Time between read/write cycles */108 unsigned int trwd;109};110 111struct sccnxp_port {112 struct uart_driver uart;113 struct uart_port port[SCCNXP_MAX_UARTS];114 bool opened[SCCNXP_MAX_UARTS];115 116 int irq;117 u8 imr;118 119 struct sccnxp_chip *chip;120 121#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE122 struct console console;123#endif124 125 spinlock_t lock;126 127 bool poll;128 struct timer_list timer;129 130 struct sccnxp_pdata pdata;131 132 struct regulator *regulator;133};134 135static const struct sccnxp_chip sc2681 = {136 .name = "SC2681",137 .nr = 2,138 .freq_min = 1000000,139 .freq_std = 3686400,140 .freq_max = 4000000,141 .flags = SCCNXP_HAVE_IO,142 .fifosize = 3,143 .trwd = 200,144};145 146static const struct sccnxp_chip sc2691 = {147 .name = "SC2691",148 .nr = 1,149 .freq_min = 1000000,150 .freq_std = 3686400,151 .freq_max = 4000000,152 .flags = 0,153 .fifosize = 3,154 .trwd = 150,155};156 157static const struct sccnxp_chip sc2692 = {158 .name = "SC2692",159 .nr = 2,160 .freq_min = 1000000,161 .freq_std = 3686400,162 .freq_max = 4000000,163 .flags = SCCNXP_HAVE_IO,164 .fifosize = 3,165 .trwd = 30,166};167 168static const struct sccnxp_chip sc2891 = {169 .name = "SC2891",170 .nr = 1,171 .freq_min = 100000,172 .freq_std = 3686400,173 .freq_max = 8000000,174 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,175 .fifosize = 16,176 .trwd = 27,177};178 179static const struct sccnxp_chip sc2892 = {180 .name = "SC2892",181 .nr = 2,182 .freq_min = 100000,183 .freq_std = 3686400,184 .freq_max = 8000000,185 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,186 .fifosize = 16,187 .trwd = 17,188};189 190static const struct sccnxp_chip sc28202 = {191 .name = "SC28202",192 .nr = 2,193 .freq_min = 1000000,194 .freq_std = 14745600,195 .freq_max = 50000000,196 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,197 .fifosize = 256,198 .trwd = 10,199};200 201static const struct sccnxp_chip sc68681 = {202 .name = "SC68681",203 .nr = 2,204 .freq_min = 1000000,205 .freq_std = 3686400,206 .freq_max = 4000000,207 .flags = SCCNXP_HAVE_IO,208 .fifosize = 3,209 .trwd = 200,210};211 212static const struct sccnxp_chip sc68692 = {213 .name = "SC68692",214 .nr = 2,215 .freq_min = 1000000,216 .freq_std = 3686400,217 .freq_max = 4000000,218 .flags = SCCNXP_HAVE_IO,219 .fifosize = 3,220 .trwd = 200,221};222 223static u8 sccnxp_read(struct uart_port *port, u8 reg)224{225 struct sccnxp_port *s = dev_get_drvdata(port->dev);226 u8 ret;227 228 ret = readb(port->membase + (reg << port->regshift));229 230 ndelay(s->chip->trwd);231 232 return ret;233}234 235static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)236{237 struct sccnxp_port *s = dev_get_drvdata(port->dev);238 239 writeb(v, port->membase + (reg << port->regshift));240 241 ndelay(s->chip->trwd);242}243 244static u8 sccnxp_port_read(struct uart_port *port, u8 reg)245{246 return sccnxp_read(port, (port->line << 3) + reg);247}248 249static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)250{251 sccnxp_write(port, (port->line << 3) + reg, v);252}253 254static int sccnxp_update_best_err(int a, int b, int *besterr)255{256 int err = abs(a - b);257 258 if (*besterr > err) {259 *besterr = err;260 return 0;261 }262 263 return 1;264}265 266static const struct {267 u8 csr;268 u8 acr;269 u8 mr0;270 int baud;271} baud_std[] = {272 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },273 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },274 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },275 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },276 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },277 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },278 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },279 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },280 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },281 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },282 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },283 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },284 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },285 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },286 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },287 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },288 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },289 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },290 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },291 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },292 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },293 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },294 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },295 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },296 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },297 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },298 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },299 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },300 { 0, 0, 0, 0 }301};302 303static int sccnxp_set_baud(struct uart_port *port, int baud)304{305 struct sccnxp_port *s = dev_get_drvdata(port->dev);306 int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;307 struct sccnxp_chip *chip = s->chip;308 u8 i, acr = 0, csr = 0, mr0 = 0;309 310 /* Find divisor to load to the timer preset registers */311 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);312 if ((div_std >= 2) && (div_std <= 0xffff)) {313 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);314 sccnxp_update_best_err(baud, bestbaud, &besterr);315 csr = CSR_TIMER_MODE;316 sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);317 sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);318 /* Issue start timer/counter command */319 sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);320 }321 322 /* Find best baud from table */323 for (i = 0; baud_std[i].baud && besterr; i++) {324 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))325 continue;326 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);327 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);328 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {329 acr = baud_std[i].acr;330 csr = baud_std[i].csr;331 mr0 = baud_std[i].mr0;332 bestbaud = tmp_baud;333 }334 }335 336 if (chip->flags & SCCNXP_HAVE_MR0) {337 /* Enable FIFO, set half level for TX */338 mr0 |= MR0_FIFO | MR0_TXLVL;339 /* Update MR0 */340 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);341 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);342 }343 344 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);345 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);346 347 if (baud != bestbaud)348 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",349 baud, bestbaud);350 351 return bestbaud;352}353 354static void sccnxp_enable_irq(struct uart_port *port, int mask)355{356 struct sccnxp_port *s = dev_get_drvdata(port->dev);357 358 s->imr |= mask << (port->line * 4);359 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);360}361 362static void sccnxp_disable_irq(struct uart_port *port, int mask)363{364 struct sccnxp_port *s = dev_get_drvdata(port->dev);365 366 s->imr &= ~(mask << (port->line * 4));367 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);368}369 370static void sccnxp_set_bit(struct uart_port *port, int sig, int state)371{372 u8 bitmask;373 struct sccnxp_port *s = dev_get_drvdata(port->dev);374 375 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {376 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);377 if (state)378 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);379 else380 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);381 }382}383 384static void sccnxp_handle_rx(struct uart_port *port)385{386 u8 sr, ch, flag;387 388 for (;;) {389 sr = sccnxp_port_read(port, SCCNXP_SR_REG);390 if (!(sr & SR_RXRDY))391 break;392 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;393 394 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);395 396 port->icount.rx++;397 flag = TTY_NORMAL;398 399 if (unlikely(sr)) {400 if (sr & SR_BRK) {401 port->icount.brk++;402 sccnxp_port_write(port, SCCNXP_CR_REG,403 CR_CMD_BREAK_RESET);404 if (uart_handle_break(port))405 continue;406 } else if (sr & SR_PE)407 port->icount.parity++;408 else if (sr & SR_FE)409 port->icount.frame++;410 else if (sr & SR_OVR) {411 port->icount.overrun++;412 sccnxp_port_write(port, SCCNXP_CR_REG,413 CR_CMD_STATUS_RESET);414 }415 416 sr &= port->read_status_mask;417 if (sr & SR_BRK)418 flag = TTY_BREAK;419 else if (sr & SR_PE)420 flag = TTY_PARITY;421 else if (sr & SR_FE)422 flag = TTY_FRAME;423 else if (sr & SR_OVR)424 flag = TTY_OVERRUN;425 }426 427 if (uart_handle_sysrq_char(port, ch))428 continue;429 430 if (sr & port->ignore_status_mask)431 continue;432 433 uart_insert_char(port, sr, SR_OVR, ch, flag);434 }435 436 tty_flip_buffer_push(&port->state->port);437}438 439static void sccnxp_handle_tx(struct uart_port *port)440{441 u8 sr;442 struct tty_port *tport = &port->state->port;443 struct sccnxp_port *s = dev_get_drvdata(port->dev);444 445 if (unlikely(port->x_char)) {446 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);447 port->icount.tx++;448 port->x_char = 0;449 return;450 }451 452 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {453 /* Disable TX if FIFO is empty */454 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {455 sccnxp_disable_irq(port, IMR_TXRDY);456 457 /* Set direction to input */458 if (s->chip->flags & SCCNXP_HAVE_IO)459 sccnxp_set_bit(port, DIR_OP, 0);460 }461 return;462 }463 464 while (1) {465 unsigned char ch;466 467 sr = sccnxp_port_read(port, SCCNXP_SR_REG);468 if (!(sr & SR_TXRDY))469 break;470 471 if (!uart_fifo_get(port, &ch))472 break;473 474 sccnxp_port_write(port, SCCNXP_THR_REG, ch);475 }476 477 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)478 uart_write_wakeup(port);479}480 481static void sccnxp_handle_events(struct sccnxp_port *s)482{483 int i;484 u8 isr;485 486 do {487 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);488 isr &= s->imr;489 if (!isr)490 break;491 492 for (i = 0; i < s->uart.nr; i++) {493 if (s->opened[i] && (isr & ISR_RXRDY(i)))494 sccnxp_handle_rx(&s->port[i]);495 if (s->opened[i] && (isr & ISR_TXRDY(i)))496 sccnxp_handle_tx(&s->port[i]);497 }498 } while (1);499}500 501static void sccnxp_timer(struct timer_list *t)502{503 struct sccnxp_port *s = from_timer(s, t, timer);504 unsigned long flags;505 506 spin_lock_irqsave(&s->lock, flags);507 sccnxp_handle_events(s);508 spin_unlock_irqrestore(&s->lock, flags);509 510 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));511}512 513static irqreturn_t sccnxp_ist(int irq, void *dev_id)514{515 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;516 unsigned long flags;517 518 spin_lock_irqsave(&s->lock, flags);519 sccnxp_handle_events(s);520 spin_unlock_irqrestore(&s->lock, flags);521 522 return IRQ_HANDLED;523}524 525static void sccnxp_start_tx(struct uart_port *port)526{527 struct sccnxp_port *s = dev_get_drvdata(port->dev);528 unsigned long flags;529 530 spin_lock_irqsave(&s->lock, flags);531 532 /* Set direction to output */533 if (s->chip->flags & SCCNXP_HAVE_IO)534 sccnxp_set_bit(port, DIR_OP, 1);535 536 sccnxp_enable_irq(port, IMR_TXRDY);537 538 spin_unlock_irqrestore(&s->lock, flags);539}540 541static void sccnxp_stop_tx(struct uart_port *port)542{543 /* Do nothing */544}545 546static void sccnxp_stop_rx(struct uart_port *port)547{548 struct sccnxp_port *s = dev_get_drvdata(port->dev);549 unsigned long flags;550 551 spin_lock_irqsave(&s->lock, flags);552 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);553 spin_unlock_irqrestore(&s->lock, flags);554}555 556static unsigned int sccnxp_tx_empty(struct uart_port *port)557{558 u8 val;559 unsigned long flags;560 struct sccnxp_port *s = dev_get_drvdata(port->dev);561 562 spin_lock_irqsave(&s->lock, flags);563 val = sccnxp_port_read(port, SCCNXP_SR_REG);564 spin_unlock_irqrestore(&s->lock, flags);565 566 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;567}568 569static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)570{571 struct sccnxp_port *s = dev_get_drvdata(port->dev);572 unsigned long flags;573 574 if (!(s->chip->flags & SCCNXP_HAVE_IO))575 return;576 577 spin_lock_irqsave(&s->lock, flags);578 579 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);580 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);581 582 spin_unlock_irqrestore(&s->lock, flags);583}584 585static unsigned int sccnxp_get_mctrl(struct uart_port *port)586{587 u8 bitmask, ipr;588 unsigned long flags;589 struct sccnxp_port *s = dev_get_drvdata(port->dev);590 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;591 592 if (!(s->chip->flags & SCCNXP_HAVE_IO))593 return mctrl;594 595 spin_lock_irqsave(&s->lock, flags);596 597 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);598 599 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {600 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],601 DSR_IP);602 mctrl &= ~TIOCM_DSR;603 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;604 }605 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {606 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],607 CTS_IP);608 mctrl &= ~TIOCM_CTS;609 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;610 }611 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {612 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],613 DCD_IP);614 mctrl &= ~TIOCM_CAR;615 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;616 }617 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {618 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],619 RNG_IP);620 mctrl &= ~TIOCM_RNG;621 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;622 }623 624 spin_unlock_irqrestore(&s->lock, flags);625 626 return mctrl;627}628 629static void sccnxp_break_ctl(struct uart_port *port, int break_state)630{631 struct sccnxp_port *s = dev_get_drvdata(port->dev);632 unsigned long flags;633 634 spin_lock_irqsave(&s->lock, flags);635 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?636 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);637 spin_unlock_irqrestore(&s->lock, flags);638}639 640static void sccnxp_set_termios(struct uart_port *port,641 struct ktermios *termios,642 const struct ktermios *old)643{644 struct sccnxp_port *s = dev_get_drvdata(port->dev);645 unsigned long flags;646 u8 mr1, mr2;647 int baud;648 649 spin_lock_irqsave(&s->lock, flags);650 651 /* Mask termios capabilities we don't support */652 termios->c_cflag &= ~CMSPAR;653 654 /* Disable RX & TX, reset break condition, status and FIFOs */655 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |656 CR_RX_DISABLE | CR_TX_DISABLE);657 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);658 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);659 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);660 661 /* Word size */662 switch (termios->c_cflag & CSIZE) {663 case CS5:664 mr1 = MR1_BITS_5;665 break;666 case CS6:667 mr1 = MR1_BITS_6;668 break;669 case CS7:670 mr1 = MR1_BITS_7;671 break;672 case CS8:673 default:674 mr1 = MR1_BITS_8;675 break;676 }677 678 /* Parity */679 if (termios->c_cflag & PARENB) {680 if (termios->c_cflag & PARODD)681 mr1 |= MR1_PAR_ODD;682 } else683 mr1 |= MR1_PAR_NO;684 685 /* Stop bits */686 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;687 688 /* Update desired format */689 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);690 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);691 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);692 693 /* Set read status mask */694 port->read_status_mask = SR_OVR;695 if (termios->c_iflag & INPCK)696 port->read_status_mask |= SR_PE | SR_FE;697 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))698 port->read_status_mask |= SR_BRK;699 700 /* Set status ignore mask */701 port->ignore_status_mask = 0;702 if (termios->c_iflag & IGNBRK)703 port->ignore_status_mask |= SR_BRK;704 if (termios->c_iflag & IGNPAR)705 port->ignore_status_mask |= SR_PE;706 if (!(termios->c_cflag & CREAD))707 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;708 709 /* Setup baudrate */710 baud = uart_get_baud_rate(port, termios, old, 50,711 (s->chip->flags & SCCNXP_HAVE_MR0) ?712 230400 : 38400);713 baud = sccnxp_set_baud(port, baud);714 715 /* Update timeout according to new baud rate */716 uart_update_timeout(port, termios->c_cflag, baud);717 718 /* Report actual baudrate back to core */719 if (tty_termios_baud_rate(termios))720 tty_termios_encode_baud_rate(termios, baud, baud);721 722 /* Enable RX & TX */723 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);724 725 spin_unlock_irqrestore(&s->lock, flags);726}727 728static int sccnxp_startup(struct uart_port *port)729{730 struct sccnxp_port *s = dev_get_drvdata(port->dev);731 unsigned long flags;732 733 spin_lock_irqsave(&s->lock, flags);734 735 if (s->chip->flags & SCCNXP_HAVE_IO) {736 /* Outputs are controlled manually */737 sccnxp_write(port, SCCNXP_OPCR_REG, 0);738 }739 740 /* Reset break condition, status and FIFOs */741 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);742 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);743 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);744 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);745 746 /* Enable RX & TX */747 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);748 749 /* Enable RX interrupt */750 sccnxp_enable_irq(port, IMR_RXRDY);751 752 s->opened[port->line] = 1;753 754 spin_unlock_irqrestore(&s->lock, flags);755 756 return 0;757}758 759static void sccnxp_shutdown(struct uart_port *port)760{761 struct sccnxp_port *s = dev_get_drvdata(port->dev);762 unsigned long flags;763 764 spin_lock_irqsave(&s->lock, flags);765 766 s->opened[port->line] = 0;767 768 /* Disable interrupts */769 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);770 771 /* Disable TX & RX */772 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);773 774 /* Leave direction to input */775 if (s->chip->flags & SCCNXP_HAVE_IO)776 sccnxp_set_bit(port, DIR_OP, 0);777 778 spin_unlock_irqrestore(&s->lock, flags);779}780 781static const char *sccnxp_type(struct uart_port *port)782{783 struct sccnxp_port *s = dev_get_drvdata(port->dev);784 785 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;786}787 788static void sccnxp_release_port(struct uart_port *port)789{790 /* Do nothing */791}792 793static int sccnxp_request_port(struct uart_port *port)794{795 /* Do nothing */796 return 0;797}798 799static void sccnxp_config_port(struct uart_port *port, int flags)800{801 if (flags & UART_CONFIG_TYPE)802 port->type = PORT_SC26XX;803}804 805static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)806{807 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))808 return 0;809 if (s->irq == port->irq)810 return 0;811 812 return -EINVAL;813}814 815static const struct uart_ops sccnxp_ops = {816 .tx_empty = sccnxp_tx_empty,817 .set_mctrl = sccnxp_set_mctrl,818 .get_mctrl = sccnxp_get_mctrl,819 .stop_tx = sccnxp_stop_tx,820 .start_tx = sccnxp_start_tx,821 .stop_rx = sccnxp_stop_rx,822 .break_ctl = sccnxp_break_ctl,823 .startup = sccnxp_startup,824 .shutdown = sccnxp_shutdown,825 .set_termios = sccnxp_set_termios,826 .type = sccnxp_type,827 .release_port = sccnxp_release_port,828 .request_port = sccnxp_request_port,829 .config_port = sccnxp_config_port,830 .verify_port = sccnxp_verify_port,831};832 833#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE834static void sccnxp_console_putchar(struct uart_port *port, unsigned char c)835{836 int tryes = 100000;837 838 while (tryes--) {839 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {840 sccnxp_port_write(port, SCCNXP_THR_REG, c);841 break;842 }843 barrier();844 }845}846 847static void sccnxp_console_write(struct console *co, const char *c, unsigned n)848{849 struct sccnxp_port *s = (struct sccnxp_port *)co->data;850 struct uart_port *port = &s->port[co->index];851 unsigned long flags;852 853 spin_lock_irqsave(&s->lock, flags);854 uart_console_write(port, c, n, sccnxp_console_putchar);855 spin_unlock_irqrestore(&s->lock, flags);856}857 858static int sccnxp_console_setup(struct console *co, char *options)859{860 struct sccnxp_port *s = (struct sccnxp_port *)co->data;861 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];862 int baud = 9600, bits = 8, parity = 'n', flow = 'n';863 864 if (options)865 uart_parse_options(options, &baud, &parity, &bits, &flow);866 867 return uart_set_options(port, co, baud, parity, bits, flow);868}869#endif870 871static const struct platform_device_id sccnxp_id_table[] = {872 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },873 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },874 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },875 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },876 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },877 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },878 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },879 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },880 { }881};882MODULE_DEVICE_TABLE(platform, sccnxp_id_table);883 884static int sccnxp_probe(struct platform_device *pdev)885{886 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);887 struct resource *res;888 int i, ret, uartclk;889 struct sccnxp_port *s;890 void __iomem *membase;891 struct clk *clk;892 893 membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);894 if (IS_ERR(membase))895 return PTR_ERR(membase);896 897 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);898 if (!s) {899 dev_err(&pdev->dev, "Error allocating port structure\n");900 return -ENOMEM;901 }902 platform_set_drvdata(pdev, s);903 904 spin_lock_init(&s->lock);905 906 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;907 908 s->regulator = devm_regulator_get(&pdev->dev, "vcc");909 if (!IS_ERR(s->regulator)) {910 ret = regulator_enable(s->regulator);911 if (ret) {912 dev_err(&pdev->dev,913 "Failed to enable regulator: %i\n", ret);914 return ret;915 }916 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)917 return -EPROBE_DEFER;918 919 clk = devm_clk_get_enabled(&pdev->dev, NULL);920 if (IS_ERR(clk)) {921 ret = PTR_ERR(clk);922 if (ret == -EPROBE_DEFER)923 goto err_out;924 uartclk = 0;925 } else {926 uartclk = clk_get_rate(clk);927 }928 929 if (!uartclk) {930 dev_notice(&pdev->dev, "Using default clock frequency\n");931 uartclk = s->chip->freq_std;932 }933 934 /* Check input frequency */935 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {936 dev_err(&pdev->dev, "Frequency out of bounds\n");937 ret = -EINVAL;938 goto err_out;939 }940 941 if (pdata)942 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));943 944 if (s->pdata.poll_time_us) {945 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",946 s->pdata.poll_time_us);947 s->poll = 1;948 }949 950 if (!s->poll) {951 s->irq = platform_get_irq(pdev, 0);952 if (s->irq < 0) {953 ret = -ENXIO;954 goto err_out;955 }956 }957 958 s->uart.owner = THIS_MODULE;959 s->uart.dev_name = "ttySC";960 s->uart.major = SCCNXP_MAJOR;961 s->uart.minor = SCCNXP_MINOR;962 s->uart.nr = s->chip->nr;963#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE964 s->uart.cons = &s->console;965 s->uart.cons->device = uart_console_device;966 s->uart.cons->write = sccnxp_console_write;967 s->uart.cons->setup = sccnxp_console_setup;968 s->uart.cons->flags = CON_PRINTBUFFER;969 s->uart.cons->index = -1;970 s->uart.cons->data = s;971 strcpy(s->uart.cons->name, "ttySC");972#endif973 ret = uart_register_driver(&s->uart);974 if (ret) {975 dev_err(&pdev->dev, "Registering UART driver failed\n");976 goto err_out;977 }978 979 for (i = 0; i < s->uart.nr; i++) {980 s->port[i].line = i;981 s->port[i].dev = &pdev->dev;982 s->port[i].irq = s->irq;983 s->port[i].type = PORT_SC26XX;984 s->port[i].fifosize = s->chip->fifosize;985 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;986 s->port[i].iotype = UPIO_MEM;987 s->port[i].mapbase = res->start;988 s->port[i].membase = membase;989 s->port[i].regshift = s->pdata.reg_shift;990 s->port[i].uartclk = uartclk;991 s->port[i].ops = &sccnxp_ops;992 s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);993 uart_add_one_port(&s->uart, &s->port[i]);994 /* Set direction to input */995 if (s->chip->flags & SCCNXP_HAVE_IO)996 sccnxp_set_bit(&s->port[i], DIR_OP, 0);997 }998 999 /* Disable interrupts */1000 s->imr = 0;1001 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);1002 1003 if (!s->poll) {1004 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,1005 sccnxp_ist,1006 IRQF_TRIGGER_FALLING |1007 IRQF_ONESHOT,1008 dev_name(&pdev->dev), s);1009 if (!ret)1010 return 0;1011 1012 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);1013 } else {1014 timer_setup(&s->timer, sccnxp_timer, 0);1015 mod_timer(&s->timer, jiffies +1016 usecs_to_jiffies(s->pdata.poll_time_us));1017 return 0;1018 }1019 1020 uart_unregister_driver(&s->uart);1021err_out:1022 if (!IS_ERR(s->regulator))1023 regulator_disable(s->regulator);1024 1025 return ret;1026}1027 1028static void sccnxp_remove(struct platform_device *pdev)1029{1030 int i;1031 struct sccnxp_port *s = platform_get_drvdata(pdev);1032 1033 if (!s->poll)1034 devm_free_irq(&pdev->dev, s->irq, s);1035 else1036 del_timer_sync(&s->timer);1037 1038 for (i = 0; i < s->uart.nr; i++)1039 uart_remove_one_port(&s->uart, &s->port[i]);1040 1041 uart_unregister_driver(&s->uart);1042 1043 if (!IS_ERR(s->regulator)) {1044 int ret = regulator_disable(s->regulator);1045 if (ret)1046 dev_err(&pdev->dev, "Failed to disable regulator\n");1047 }1048}1049 1050static struct platform_driver sccnxp_uart_driver = {1051 .driver = {1052 .name = SCCNXP_NAME,1053 },1054 .probe = sccnxp_probe,1055 .remove_new = sccnxp_remove,1056 .id_table = sccnxp_id_table,1057};1058module_platform_driver(sccnxp_uart_driver);1059 1060MODULE_LICENSE("GPL v2");1061MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");1062MODULE_DESCRIPTION("SCCNXP serial driver");1063