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1// SPDX-License-Identifier: GPL-2.02/*3 * serial_tegra.c4 *5 * High-speed serial driver for NVIDIA Tegra SoCs6 *7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.8 *9 * Author: Laxman Dewangan <ldewangan@nvidia.com>10 */11 12#include <linux/clk.h>13#include <linux/debugfs.h>14#include <linux/delay.h>15#include <linux/dmaengine.h>16#include <linux/dma-mapping.h>17#include <linux/dmapool.h>18#include <linux/err.h>19#include <linux/io.h>20#include <linux/irq.h>21#include <linux/module.h>22#include <linux/of.h>23#include <linux/pagemap.h>24#include <linux/platform_device.h>25#include <linux/reset.h>26#include <linux/serial.h>27#include <linux/serial_8250.h>28#include <linux/serial_core.h>29#include <linux/serial_reg.h>30#include <linux/slab.h>31#include <linux/string.h>32#include <linux/termios.h>33#include <linux/tty.h>34#include <linux/tty_flip.h>35 36#define TEGRA_UART_TYPE "TEGRA_UART"37#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)38#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)39 40#define TEGRA_UART_RX_DMA_BUFFER_SIZE 409641#define TEGRA_UART_LSR_TXFIFO_FULL 0x10042#define TEGRA_UART_IER_EORD 0x2043#define TEGRA_UART_MCR_RTS_EN 0x4044#define TEGRA_UART_MCR_CTS_EN 0x2045#define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \46 UART_LSR_PE | UART_LSR_FE)47#define TEGRA_UART_IRDA_CSR 0x0848#define TEGRA_UART_SIR_ENABLED 0x8049 50#define TEGRA_UART_TX_PIO 151#define TEGRA_UART_TX_DMA 252#define TEGRA_UART_MIN_DMA 1653#define TEGRA_UART_FIFO_SIZE 3254 55/*56 * Tx fifo trigger level setting in tegra uart is in57 * reverse way then conventional uart.58 */59#define TEGRA_UART_TX_TRIG_16B 0x0060#define TEGRA_UART_TX_TRIG_8B 0x1061#define TEGRA_UART_TX_TRIG_4B 0x2062#define TEGRA_UART_TX_TRIG_1B 0x3063 64#define TEGRA_UART_MAXIMUM 865 66/* Default UART setting when started: 115200 no parity, stop, 8 data bits */67#define TEGRA_UART_DEFAULT_BAUD 11520068#define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN869 70/* Tx transfer mode */71#define TEGRA_TX_PIO 172#define TEGRA_TX_DMA 273 74#define TEGRA_UART_FCR_IIR_FIFO_EN 0x4075 76/**77 * struct tegra_uart_chip_data: SOC specific data.78 *79 * @tx_fifo_full_status: Status flag available for checking tx fifo full.80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.81 * Tegra30 does not allow this.82 * @support_clk_src_div: Clock source support the clock divider.83 * @fifo_mode_enable_status: Is FIFO mode enabled?84 * @uart_max_port: Maximum number of UART ports85 * @max_dma_burst_bytes: Maximum size of DMA bursts86 * @error_tolerance_low_range: Lowest number in the error tolerance range87 * @error_tolerance_high_range: Highest number in the error tolerance range88 */89struct tegra_uart_chip_data {90 bool tx_fifo_full_status;91 bool allow_txfifo_reset_fifo_mode;92 bool support_clk_src_div;93 bool fifo_mode_enable_status;94 int uart_max_port;95 int max_dma_burst_bytes;96 int error_tolerance_low_range;97 int error_tolerance_high_range;98};99 100struct tegra_baud_tolerance {101 u32 lower_range_baud;102 u32 upper_range_baud;103 s32 tolerance;104};105 106struct tegra_uart_port {107 struct uart_port uport;108 const struct tegra_uart_chip_data *cdata;109 110 struct clk *uart_clk;111 struct reset_control *rst;112 unsigned int current_baud;113 114 /* Register shadow */115 unsigned long fcr_shadow;116 unsigned long mcr_shadow;117 unsigned long lcr_shadow;118 unsigned long ier_shadow;119 bool rts_active;120 121 int tx_in_progress;122 unsigned int tx_bytes;123 124 bool enable_modem_interrupt;125 126 bool rx_timeout;127 int rx_in_progress;128 int symb_bit;129 130 struct dma_chan *rx_dma_chan;131 struct dma_chan *tx_dma_chan;132 dma_addr_t rx_dma_buf_phys;133 dma_addr_t tx_dma_buf_phys;134 unsigned char *rx_dma_buf_virt;135 unsigned char *tx_dma_buf_virt;136 struct dma_async_tx_descriptor *tx_dma_desc;137 struct dma_async_tx_descriptor *rx_dma_desc;138 dma_cookie_t tx_cookie;139 dma_cookie_t rx_cookie;140 unsigned int tx_bytes_requested;141 unsigned int rx_bytes_requested;142 struct tegra_baud_tolerance *baud_tolerance;143 int n_adjustable_baud_rates;144 int required_rate;145 int configured_rate;146 bool use_rx_pio;147 bool use_tx_pio;148 bool rx_dma_active;149};150 151static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);152static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);153static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,154 bool dma_to_memory);155 156static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,157 unsigned long reg)158{159 return readl(tup->uport.membase + (reg << tup->uport.regshift));160}161 162static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,163 unsigned long reg)164{165 writel(val, tup->uport.membase + (reg << tup->uport.regshift));166}167 168static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)169{170 return container_of(u, struct tegra_uart_port, uport);171}172 173static unsigned int tegra_uart_get_mctrl(struct uart_port *u)174{175 struct tegra_uart_port *tup = to_tegra_uport(u);176 177 /*178 * RI - Ring detector is active179 * CD/DCD/CAR - Carrier detect is always active. For some reason180 * linux has different names for carrier detect.181 * DSR - Data Set ready is active as the hardware doesn't support it.182 * Don't know if the linux support this yet?183 * CTS - Clear to send. Always set to active, as the hardware handles184 * CTS automatically.185 */186 if (tup->enable_modem_interrupt)187 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;188 return TIOCM_CTS;189}190 191static void set_rts(struct tegra_uart_port *tup, bool active)192{193 unsigned long mcr;194 195 mcr = tup->mcr_shadow;196 if (active)197 mcr |= TEGRA_UART_MCR_RTS_EN;198 else199 mcr &= ~TEGRA_UART_MCR_RTS_EN;200 if (mcr != tup->mcr_shadow) {201 tegra_uart_write(tup, mcr, UART_MCR);202 tup->mcr_shadow = mcr;203 }204}205 206static void set_dtr(struct tegra_uart_port *tup, bool active)207{208 unsigned long mcr;209 210 mcr = tup->mcr_shadow;211 if (active)212 mcr |= UART_MCR_DTR;213 else214 mcr &= ~UART_MCR_DTR;215 if (mcr != tup->mcr_shadow) {216 tegra_uart_write(tup, mcr, UART_MCR);217 tup->mcr_shadow = mcr;218 }219}220 221static void set_loopbk(struct tegra_uart_port *tup, bool active)222{223 unsigned long mcr = tup->mcr_shadow;224 225 if (active)226 mcr |= UART_MCR_LOOP;227 else228 mcr &= ~UART_MCR_LOOP;229 230 if (mcr != tup->mcr_shadow) {231 tegra_uart_write(tup, mcr, UART_MCR);232 tup->mcr_shadow = mcr;233 }234}235 236static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)237{238 struct tegra_uart_port *tup = to_tegra_uport(u);239 int enable;240 241 tup->rts_active = !!(mctrl & TIOCM_RTS);242 set_rts(tup, tup->rts_active);243 244 enable = !!(mctrl & TIOCM_DTR);245 set_dtr(tup, enable);246 247 enable = !!(mctrl & TIOCM_LOOP);248 set_loopbk(tup, enable);249}250 251static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)252{253 struct tegra_uart_port *tup = to_tegra_uport(u);254 unsigned long lcr;255 256 lcr = tup->lcr_shadow;257 if (break_ctl)258 lcr |= UART_LCR_SBC;259 else260 lcr &= ~UART_LCR_SBC;261 tegra_uart_write(tup, lcr, UART_LCR);262 tup->lcr_shadow = lcr;263}264 265/**266 * tegra_uart_wait_cycle_time: Wait for N UART clock periods267 *268 * @tup: Tegra serial port data structure.269 * @cycles: Number of clock periods to wait.270 *271 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART272 * clock speed is 16X the current baud rate.273 */274static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,275 unsigned int cycles)276{277 if (tup->current_baud)278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));279}280 281/* Wait for a symbol-time. */282static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,283 unsigned int syms)284{285 if (tup->current_baud)286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,287 tup->current_baud));288}289 290static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)291{292 unsigned long iir;293 unsigned int tmout = 100;294 295 do {296 iir = tegra_uart_read(tup, UART_IIR);297 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)298 return 0;299 udelay(1);300 } while (--tmout);301 302 return -ETIMEDOUT;303}304 305static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)306{307 unsigned long fcr = tup->fcr_shadow;308 unsigned int lsr, tmout = 10000;309 310 if (tup->rts_active)311 set_rts(tup, false);312 313 if (tup->cdata->allow_txfifo_reset_fifo_mode) {314 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);315 tegra_uart_write(tup, fcr, UART_FCR);316 } else {317 fcr &= ~UART_FCR_ENABLE_FIFO;318 tegra_uart_write(tup, fcr, UART_FCR);319 udelay(60);320 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);321 tegra_uart_write(tup, fcr, UART_FCR);322 fcr |= UART_FCR_ENABLE_FIFO;323 tegra_uart_write(tup, fcr, UART_FCR);324 if (tup->cdata->fifo_mode_enable_status)325 tegra_uart_wait_fifo_mode_enabled(tup);326 }327 328 /* Dummy read to ensure the write is posted */329 tegra_uart_read(tup, UART_SCR);330 331 /*332 * For all tegra devices (up to t210), there is a hardware issue that333 * requires software to wait for 32 UART clock periods for the flush334 * to propagate, otherwise data could be lost.335 */336 tegra_uart_wait_cycle_time(tup, 32);337 338 do {339 lsr = tegra_uart_read(tup, UART_LSR);340 if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))341 break;342 udelay(1);343 } while (--tmout);344 345 if (tup->rts_active)346 set_rts(tup, true);347}348 349static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,350 unsigned int baud, long rate)351{352 int i;353 354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {355 if (baud >= tup->baud_tolerance[i].lower_range_baud &&356 baud <= tup->baud_tolerance[i].upper_range_baud)357 return (rate + (rate *358 tup->baud_tolerance[i].tolerance) / 10000);359 }360 361 return rate;362}363 364static int tegra_check_rate_in_range(struct tegra_uart_port *tup)365{366 long diff;367 368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)369 / tup->required_rate;370 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||371 diff > (tup->cdata->error_tolerance_high_range * 100)) {372 dev_err(tup->uport.dev,373 "configured baud rate is out of range by %ld", diff);374 return -EIO;375 }376 377 return 0;378}379 380static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)381{382 unsigned long rate;383 unsigned int divisor;384 unsigned long lcr;385 unsigned long flags;386 int ret;387 388 if (tup->current_baud == baud)389 return 0;390 391 if (tup->cdata->support_clk_src_div) {392 rate = baud * 16;393 tup->required_rate = rate;394 395 if (tup->n_adjustable_baud_rates)396 rate = tegra_get_tolerance_rate(tup, baud, rate);397 398 ret = clk_set_rate(tup->uart_clk, rate);399 if (ret < 0) {400 dev_err(tup->uport.dev,401 "clk_set_rate() failed for rate %lu\n", rate);402 return ret;403 }404 tup->configured_rate = clk_get_rate(tup->uart_clk);405 divisor = 1;406 ret = tegra_check_rate_in_range(tup);407 if (ret < 0)408 return ret;409 } else {410 rate = clk_get_rate(tup->uart_clk);411 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);412 }413 414 uart_port_lock_irqsave(&tup->uport, &flags);415 lcr = tup->lcr_shadow;416 lcr |= UART_LCR_DLAB;417 tegra_uart_write(tup, lcr, UART_LCR);418 419 tegra_uart_write(tup, divisor & 0xFF, UART_TX);420 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);421 422 lcr &= ~UART_LCR_DLAB;423 tegra_uart_write(tup, lcr, UART_LCR);424 425 /* Dummy read to ensure the write is posted */426 tegra_uart_read(tup, UART_SCR);427 uart_port_unlock_irqrestore(&tup->uport, flags);428 429 tup->current_baud = baud;430 431 /* wait two character intervals at new rate */432 tegra_uart_wait_sym_time(tup, 2);433 return 0;434}435 436static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup,437 unsigned long lsr)438{439 u8 flag = TTY_NORMAL;440 441 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {442 if (lsr & UART_LSR_OE) {443 /* Overrun error */444 flag = TTY_OVERRUN;445 tup->uport.icount.overrun++;446 dev_dbg(tup->uport.dev, "Got overrun errors\n");447 } else if (lsr & UART_LSR_PE) {448 /* Parity error */449 flag = TTY_PARITY;450 tup->uport.icount.parity++;451 dev_dbg(tup->uport.dev, "Got Parity errors\n");452 } else if (lsr & UART_LSR_FE) {453 flag = TTY_FRAME;454 tup->uport.icount.frame++;455 dev_dbg(tup->uport.dev, "Got frame errors\n");456 } else if (lsr & UART_LSR_BI) {457 /*458 * Break error459 * If FIFO read error without any data, reset Rx FIFO460 */461 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))462 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);463 if (tup->uport.ignore_status_mask & UART_LSR_BI)464 return TTY_BREAK;465 flag = TTY_BREAK;466 tup->uport.icount.brk++;467 dev_dbg(tup->uport.dev, "Got Break\n");468 }469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);470 }471 472 return flag;473}474 475static int tegra_uart_request_port(struct uart_port *u)476{477 return 0;478}479 480static void tegra_uart_release_port(struct uart_port *u)481{482 /* Nothing to do here */483}484 485static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)486{487 unsigned char ch;488 int i;489 490 for (i = 0; i < max_bytes; i++) {491 if (tup->cdata->tx_fifo_full_status) {492 unsigned long lsr = tegra_uart_read(tup, UART_LSR);493 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))494 break;495 }496 if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch)))497 break;498 tegra_uart_write(tup, ch, UART_TX);499 }500}501 502static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,503 unsigned int bytes)504{505 if (bytes > TEGRA_UART_MIN_DMA)506 bytes = TEGRA_UART_MIN_DMA;507 508 tup->tx_in_progress = TEGRA_UART_TX_PIO;509 tup->tx_bytes = bytes;510 tup->ier_shadow |= UART_IER_THRI;511 tegra_uart_write(tup, tup->ier_shadow, UART_IER);512}513 514static void tegra_uart_tx_dma_complete(void *args)515{516 struct tegra_uart_port *tup = args;517 struct tty_port *tport = &tup->uport.state->port;518 struct dma_tx_state state;519 unsigned long flags;520 unsigned int count;521 522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);523 count = tup->tx_bytes_requested - state.residue;524 async_tx_ack(tup->tx_dma_desc);525 uart_port_lock_irqsave(&tup->uport, &flags);526 uart_xmit_advance(&tup->uport, count);527 tup->tx_in_progress = 0;528 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)529 uart_write_wakeup(&tup->uport);530 tegra_uart_start_next_tx(tup);531 uart_port_unlock_irqrestore(&tup->uport, flags);532}533 534static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,535 unsigned long count)536{537 struct tty_port *tport = &tup->uport.state->port;538 dma_addr_t tx_phys_addr;539 unsigned int tail;540 541 tup->tx_bytes = count & ~(0xF);542 WARN_ON_ONCE(kfifo_out_linear(&tport->xmit_fifo, &tail,543 UART_XMIT_SIZE) < count);544 tx_phys_addr = tup->tx_dma_buf_phys + tail;545 546 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,547 tup->tx_bytes, DMA_TO_DEVICE);548 549 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,550 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,551 DMA_PREP_INTERRUPT);552 if (!tup->tx_dma_desc) {553 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");554 return -EIO;555 }556 557 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;558 tup->tx_dma_desc->callback_param = tup;559 tup->tx_in_progress = TEGRA_UART_TX_DMA;560 tup->tx_bytes_requested = tup->tx_bytes;561 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);562 dma_async_issue_pending(tup->tx_dma_chan);563 return 0;564}565 566static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)567{568 struct tty_port *tport = &tup->uport.state->port;569 unsigned char *tail_ptr;570 unsigned long tail;571 unsigned int count;572 573 if (!tup->current_baud)574 return;575 576 count = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail_ptr,577 UART_XMIT_SIZE);578 if (!count)579 return;580 581 tail = (unsigned long)tail_ptr;582 583 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)584 tegra_uart_start_pio_tx(tup, count);585 else if (BYTES_TO_ALIGN(tail) > 0)586 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));587 else588 tegra_uart_start_tx_dma(tup, count);589}590 591/* Called by serial core driver with u->lock taken. */592static void tegra_uart_start_tx(struct uart_port *u)593{594 struct tegra_uart_port *tup = to_tegra_uport(u);595 struct tty_port *tport = &u->state->port;596 597 if (!kfifo_is_empty(&tport->xmit_fifo) && !tup->tx_in_progress)598 tegra_uart_start_next_tx(tup);599}600 601static unsigned int tegra_uart_tx_empty(struct uart_port *u)602{603 struct tegra_uart_port *tup = to_tegra_uport(u);604 unsigned int ret = 0;605 unsigned long flags;606 607 uart_port_lock_irqsave(u, &flags);608 if (!tup->tx_in_progress) {609 unsigned long lsr = tegra_uart_read(tup, UART_LSR);610 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)611 ret = TIOCSER_TEMT;612 }613 uart_port_unlock_irqrestore(u, flags);614 return ret;615}616 617static void tegra_uart_stop_tx(struct uart_port *u)618{619 struct tegra_uart_port *tup = to_tegra_uport(u);620 struct dma_tx_state state;621 unsigned int count;622 623 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)624 return;625 626 dmaengine_pause(tup->tx_dma_chan);627 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);628 dmaengine_terminate_all(tup->tx_dma_chan);629 count = tup->tx_bytes_requested - state.residue;630 async_tx_ack(tup->tx_dma_desc);631 uart_xmit_advance(&tup->uport, count);632 tup->tx_in_progress = 0;633}634 635static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)636{637 struct tty_port *tport = &tup->uport.state->port;638 639 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);640 tup->tx_in_progress = 0;641 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)642 uart_write_wakeup(&tup->uport);643 tegra_uart_start_next_tx(tup);644}645 646static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,647 struct tty_port *port)648{649 do {650 unsigned long lsr = 0;651 u8 ch, flag = TTY_NORMAL;652 653 lsr = tegra_uart_read(tup, UART_LSR);654 if (!(lsr & UART_LSR_DR))655 break;656 657 flag = tegra_uart_decode_rx_error(tup, lsr);658 if (flag != TTY_NORMAL)659 continue;660 661 ch = (unsigned char) tegra_uart_read(tup, UART_RX);662 tup->uport.icount.rx++;663 664 if (uart_handle_sysrq_char(&tup->uport, ch))665 continue;666 667 if (tup->uport.ignore_status_mask & UART_LSR_DR)668 continue;669 670 tty_insert_flip_char(port, ch, flag);671 } while (1);672}673 674static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,675 struct tty_port *port,676 unsigned int count)677{678 int copied;679 680 /* If count is zero, then there is no data to be copied */681 if (!count)682 return;683 684 tup->uport.icount.rx += count;685 686 if (tup->uport.ignore_status_mask & UART_LSR_DR)687 return;688 689 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,690 count, DMA_FROM_DEVICE);691 copied = tty_insert_flip_string(port,692 ((unsigned char *)(tup->rx_dma_buf_virt)), count);693 if (copied != count) {694 WARN_ON(1);695 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");696 }697 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,698 count, DMA_TO_DEVICE);699}700 701static void do_handle_rx_pio(struct tegra_uart_port *tup)702{703 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);704 struct tty_port *port = &tup->uport.state->port;705 706 tegra_uart_handle_rx_pio(tup, port);707 if (tty) {708 tty_flip_buffer_push(port);709 tty_kref_put(tty);710 }711}712 713static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,714 unsigned int residue)715{716 struct tty_port *port = &tup->uport.state->port;717 unsigned int count;718 719 async_tx_ack(tup->rx_dma_desc);720 count = tup->rx_bytes_requested - residue;721 722 /* If we are here, DMA is stopped */723 tegra_uart_copy_rx_to_tty(tup, port, count);724 725 do_handle_rx_pio(tup);726}727 728static void tegra_uart_rx_dma_complete(void *args)729{730 struct tegra_uart_port *tup = args;731 struct uart_port *u = &tup->uport;732 unsigned long flags;733 struct dma_tx_state state;734 enum dma_status status;735 736 uart_port_lock_irqsave(u, &flags);737 738 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);739 740 if (status == DMA_IN_PROGRESS) {741 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");742 goto done;743 }744 745 /* Deactivate flow control to stop sender */746 if (tup->rts_active)747 set_rts(tup, false);748 749 tup->rx_dma_active = false;750 tegra_uart_rx_buffer_push(tup, 0);751 tegra_uart_start_rx_dma(tup);752 753 /* Activate flow control to start transfer */754 if (tup->rts_active)755 set_rts(tup, true);756 757done:758 uart_port_unlock_irqrestore(u, flags);759}760 761static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)762{763 struct dma_tx_state state;764 765 if (!tup->rx_dma_active) {766 do_handle_rx_pio(tup);767 return;768 }769 770 dmaengine_pause(tup->rx_dma_chan);771 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);772 dmaengine_terminate_all(tup->rx_dma_chan);773 774 tegra_uart_rx_buffer_push(tup, state.residue);775 tup->rx_dma_active = false;776}777 778static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)779{780 /* Deactivate flow control to stop sender */781 if (tup->rts_active)782 set_rts(tup, false);783 784 tegra_uart_terminate_rx_dma(tup);785 786 if (tup->rts_active)787 set_rts(tup, true);788}789 790static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)791{792 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;793 794 if (tup->rx_dma_active)795 return 0;796 797 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,798 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,799 DMA_PREP_INTERRUPT);800 if (!tup->rx_dma_desc) {801 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");802 return -EIO;803 }804 805 tup->rx_dma_active = true;806 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;807 tup->rx_dma_desc->callback_param = tup;808 tup->rx_bytes_requested = count;809 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);810 dma_async_issue_pending(tup->rx_dma_chan);811 return 0;812}813 814static void tegra_uart_handle_modem_signal_change(struct uart_port *u)815{816 struct tegra_uart_port *tup = to_tegra_uport(u);817 unsigned long msr;818 819 msr = tegra_uart_read(tup, UART_MSR);820 if (!(msr & UART_MSR_ANY_DELTA))821 return;822 823 if (msr & UART_MSR_TERI)824 tup->uport.icount.rng++;825 if (msr & UART_MSR_DDSR)826 tup->uport.icount.dsr++;827 /* We may only get DDCD when HW init and reset */828 if (msr & UART_MSR_DDCD)829 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);830 /* Will start/stop_tx accordingly */831 if (msr & UART_MSR_DCTS)832 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);833}834 835static irqreturn_t tegra_uart_isr(int irq, void *data)836{837 struct tegra_uart_port *tup = data;838 struct uart_port *u = &tup->uport;839 unsigned long iir;840 unsigned long ier;841 bool is_rx_start = false;842 bool is_rx_int = false;843 unsigned long flags;844 845 uart_port_lock_irqsave(u, &flags);846 while (1) {847 iir = tegra_uart_read(tup, UART_IIR);848 if (iir & UART_IIR_NO_INT) {849 if (!tup->use_rx_pio && is_rx_int) {850 tegra_uart_handle_rx_dma(tup);851 if (tup->rx_in_progress) {852 ier = tup->ier_shadow;853 ier |= (UART_IER_RLSI | UART_IER_RTOIE |854 TEGRA_UART_IER_EORD | UART_IER_RDI);855 tup->ier_shadow = ier;856 tegra_uart_write(tup, ier, UART_IER);857 }858 } else if (is_rx_start) {859 tegra_uart_start_rx_dma(tup);860 }861 uart_port_unlock_irqrestore(u, flags);862 return IRQ_HANDLED;863 }864 865 switch ((iir >> 1) & 0x7) {866 case 0: /* Modem signal change interrupt */867 tegra_uart_handle_modem_signal_change(u);868 break;869 870 case 1: /* Transmit interrupt only triggered when using PIO */871 tup->ier_shadow &= ~UART_IER_THRI;872 tegra_uart_write(tup, tup->ier_shadow, UART_IER);873 tegra_uart_handle_tx_pio(tup);874 break;875 876 case 4: /* End of data */877 case 6: /* Rx timeout */878 if (!tup->use_rx_pio) {879 is_rx_int = tup->rx_in_progress;880 /* Disable Rx interrupts */881 ier = tup->ier_shadow;882 ier &= ~(UART_IER_RDI | UART_IER_RLSI |883 UART_IER_RTOIE | TEGRA_UART_IER_EORD);884 tup->ier_shadow = ier;885 tegra_uart_write(tup, ier, UART_IER);886 break;887 }888 fallthrough;889 case 2: /* Receive */890 if (!tup->use_rx_pio) {891 is_rx_start = tup->rx_in_progress;892 tup->ier_shadow &= ~UART_IER_RDI;893 tegra_uart_write(tup, tup->ier_shadow,894 UART_IER);895 } else {896 do_handle_rx_pio(tup);897 }898 break;899 900 case 3: /* Receive error */901 tegra_uart_decode_rx_error(tup,902 tegra_uart_read(tup, UART_LSR));903 break;904 905 case 5: /* break nothing to handle */906 case 7: /* break nothing to handle */907 break;908 }909 }910}911 912static void tegra_uart_stop_rx(struct uart_port *u)913{914 struct tegra_uart_port *tup = to_tegra_uport(u);915 struct tty_port *port = &tup->uport.state->port;916 unsigned long ier;917 918 if (tup->rts_active)919 set_rts(tup, false);920 921 if (!tup->rx_in_progress)922 return;923 924 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */925 926 ier = tup->ier_shadow;927 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |928 TEGRA_UART_IER_EORD);929 tup->ier_shadow = ier;930 tegra_uart_write(tup, ier, UART_IER);931 tup->rx_in_progress = 0;932 933 if (!tup->use_rx_pio)934 tegra_uart_terminate_rx_dma(tup);935 else936 tegra_uart_handle_rx_pio(tup, port);937}938 939static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)940{941 unsigned long flags;942 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);943 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;944 unsigned long wait_time;945 unsigned long lsr;946 unsigned long msr;947 unsigned long mcr;948 949 /* Disable interrupts */950 tegra_uart_write(tup, 0, UART_IER);951 952 lsr = tegra_uart_read(tup, UART_LSR);953 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {954 msr = tegra_uart_read(tup, UART_MSR);955 mcr = tegra_uart_read(tup, UART_MCR);956 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))957 dev_err(tup->uport.dev,958 "Tx Fifo not empty, CTS disabled, waiting\n");959 960 /* Wait for Tx fifo to be empty */961 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {962 wait_time = min(fifo_empty_time, 100lu);963 udelay(wait_time);964 fifo_empty_time -= wait_time;965 if (!fifo_empty_time) {966 msr = tegra_uart_read(tup, UART_MSR);967 mcr = tegra_uart_read(tup, UART_MCR);968 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&969 (msr & UART_MSR_CTS))970 dev_err(tup->uport.dev,971 "Slave not ready\n");972 break;973 }974 lsr = tegra_uart_read(tup, UART_LSR);975 }976 }977 978 uart_port_lock_irqsave(&tup->uport, &flags);979 /* Reset the Rx and Tx FIFOs */980 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);981 tup->current_baud = 0;982 uart_port_unlock_irqrestore(&tup->uport, flags);983 984 tup->rx_in_progress = 0;985 tup->tx_in_progress = 0;986 987 if (!tup->use_rx_pio)988 tegra_uart_dma_channel_free(tup, true);989 if (!tup->use_tx_pio)990 tegra_uart_dma_channel_free(tup, false);991 992 clk_disable_unprepare(tup->uart_clk);993}994 995static int tegra_uart_hw_init(struct tegra_uart_port *tup)996{997 int ret;998 999 tup->fcr_shadow = 0;1000 tup->mcr_shadow = 0;1001 tup->lcr_shadow = 0;1002 tup->ier_shadow = 0;1003 tup->current_baud = 0;1004 1005 ret = clk_prepare_enable(tup->uart_clk);1006 if (ret) {1007 dev_err(tup->uport.dev, "could not enable clk\n");1008 return ret;1009 }1010 1011 /* Reset the UART controller to clear all previous status.*/1012 reset_control_assert(tup->rst);1013 udelay(10);1014 reset_control_deassert(tup->rst);1015 1016 tup->rx_in_progress = 0;1017 tup->tx_in_progress = 0;1018 1019 /*1020 * Set the trigger level1021 *1022 * For PIO mode:1023 *1024 * For receive, this will interrupt the CPU after that many number of1025 * bytes are received, for the remaining bytes the receive timeout1026 * interrupt is received. Rx high watermark is set to 4.1027 *1028 * For transmit, if the trasnmit interrupt is enabled, this will1029 * interrupt the CPU when the number of entries in the FIFO reaches the1030 * low watermark. Tx low watermark is set to 16 bytes.1031 *1032 * For DMA mode:1033 *1034 * Set the Tx trigger to 16. This should match the DMA burst size that1035 * programmed in the DMA registers.1036 */1037 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;1038 1039 if (tup->use_rx_pio) {1040 tup->fcr_shadow |= UART_FCR_R_TRIG_11;1041 } else {1042 if (tup->cdata->max_dma_burst_bytes == 8)1043 tup->fcr_shadow |= UART_FCR_R_TRIG_10;1044 else1045 tup->fcr_shadow |= UART_FCR_R_TRIG_01;1046 }1047 1048 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;1049 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);1050 1051 /* Dummy read to ensure the write is posted */1052 tegra_uart_read(tup, UART_SCR);1053 1054 if (tup->cdata->fifo_mode_enable_status) {1055 ret = tegra_uart_wait_fifo_mode_enabled(tup);1056 if (ret < 0) {1057 clk_disable_unprepare(tup->uart_clk);1058 dev_err(tup->uport.dev,1059 "Failed to enable FIFO mode: %d\n", ret);1060 return ret;1061 }1062 } else {1063 /*1064 * For all tegra devices (up to t210), there is a hardware1065 * issue that requires software to wait for 3 UART clock1066 * periods after enabling the TX fifo, otherwise data could1067 * be lost.1068 */1069 tegra_uart_wait_cycle_time(tup, 3);1070 }1071 1072 /*1073 * Initialize the UART with default configuration1074 * (115200, N, 8, 1) so that the receive DMA buffer may be1075 * enqueued1076 */1077 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);1078 if (ret < 0) {1079 clk_disable_unprepare(tup->uart_clk);1080 dev_err(tup->uport.dev, "Failed to set baud rate\n");1081 return ret;1082 }1083 if (!tup->use_rx_pio) {1084 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;1085 tup->fcr_shadow |= UART_FCR_DMA_SELECT;1086 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);1087 } else {1088 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);1089 }1090 tup->rx_in_progress = 1;1091 1092 /*1093 * Enable IE_RXS for the receive status interrupts like line errors.1094 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.1095 *1096 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when1097 * the DATA is sitting in the FIFO and couldn't be transferred to the1098 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be1099 * triggered when there is a pause of the incomming data stream for 41100 * characters long.1101 *1102 * For pauses in the data which is not aligned to 4 bytes, we get1103 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first1104 * then the EORD.1105 */1106 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;1107 1108 /*1109 * If using DMA mode, enable EORD interrupt to notify about RX1110 * completion.1111 */1112 if (!tup->use_rx_pio)1113 tup->ier_shadow |= TEGRA_UART_IER_EORD;1114 1115 tegra_uart_write(tup, tup->ier_shadow, UART_IER);1116 return 0;1117}1118 1119static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,1120 bool dma_to_memory)1121{1122 if (dma_to_memory) {1123 dmaengine_terminate_all(tup->rx_dma_chan);1124 dma_release_channel(tup->rx_dma_chan);1125 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,1126 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);1127 tup->rx_dma_chan = NULL;1128 tup->rx_dma_buf_phys = 0;1129 tup->rx_dma_buf_virt = NULL;1130 } else {1131 dmaengine_terminate_all(tup->tx_dma_chan);1132 dma_release_channel(tup->tx_dma_chan);1133 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,1134 UART_XMIT_SIZE, DMA_TO_DEVICE);1135 tup->tx_dma_chan = NULL;1136 tup->tx_dma_buf_phys = 0;1137 tup->tx_dma_buf_virt = NULL;1138 }1139}1140 1141static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,1142 bool dma_to_memory)1143{1144 struct dma_chan *dma_chan;1145 unsigned char *dma_buf;1146 dma_addr_t dma_phys;1147 int ret;1148 struct dma_slave_config dma_sconfig;1149 1150 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");1151 if (IS_ERR(dma_chan)) {1152 ret = PTR_ERR(dma_chan);1153 dev_err(tup->uport.dev,1154 "DMA channel alloc failed: %d\n", ret);1155 return ret;1156 }1157 1158 if (dma_to_memory) {1159 dma_buf = dma_alloc_coherent(tup->uport.dev,1160 TEGRA_UART_RX_DMA_BUFFER_SIZE,1161 &dma_phys, GFP_KERNEL);1162 if (!dma_buf) {1163 dev_err(tup->uport.dev,1164 "Not able to allocate the dma buffer\n");1165 dma_release_channel(dma_chan);1166 return -ENOMEM;1167 }1168 dma_sync_single_for_device(tup->uport.dev, dma_phys,1169 TEGRA_UART_RX_DMA_BUFFER_SIZE,1170 DMA_TO_DEVICE);1171 dma_sconfig.src_addr = tup->uport.mapbase;1172 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;1173 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;1174 tup->rx_dma_chan = dma_chan;1175 tup->rx_dma_buf_virt = dma_buf;1176 tup->rx_dma_buf_phys = dma_phys;1177 } else {1178 dma_buf = tup->uport.state->port.xmit_buf;1179 dma_phys = dma_map_single(tup->uport.dev,1180 dma_buf, UART_XMIT_SIZE, DMA_TO_DEVICE);1181 if (dma_mapping_error(tup->uport.dev, dma_phys)) {1182 dev_err(tup->uport.dev, "dma_map_single tx failed\n");1183 dma_release_channel(dma_chan);1184 return -ENOMEM;1185 }1186 dma_sconfig.dst_addr = tup->uport.mapbase;1187 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;1188 dma_sconfig.dst_maxburst = 16;1189 tup->tx_dma_chan = dma_chan;1190 tup->tx_dma_buf_virt = dma_buf;1191 tup->tx_dma_buf_phys = dma_phys;1192 }1193 1194 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);1195 if (ret < 0) {1196 dev_err(tup->uport.dev,1197 "Dma slave config failed, err = %d\n", ret);1198 tegra_uart_dma_channel_free(tup, dma_to_memory);1199 return ret;1200 }1201 1202 return 0;1203}1204 1205static int tegra_uart_startup(struct uart_port *u)1206{1207 struct tegra_uart_port *tup = to_tegra_uport(u);1208 int ret;1209 1210 if (!tup->use_tx_pio) {1211 ret = tegra_uart_dma_channel_allocate(tup, false);1212 if (ret < 0) {1213 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",1214 ret);1215 return ret;1216 }1217 }1218 1219 if (!tup->use_rx_pio) {1220 ret = tegra_uart_dma_channel_allocate(tup, true);1221 if (ret < 0) {1222 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",1223 ret);1224 goto fail_rx_dma;1225 }1226 }1227 1228 ret = tegra_uart_hw_init(tup);1229 if (ret < 0) {1230 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);1231 goto fail_hw_init;1232 }1233 1234 ret = request_irq(u->irq, tegra_uart_isr, 0,1235 dev_name(u->dev), tup);1236 if (ret < 0) {1237 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);1238 goto fail_request_irq;1239 }1240 return 0;1241 1242fail_request_irq:1243 /* tup->uart_clk is already enabled in tegra_uart_hw_init */1244 clk_disable_unprepare(tup->uart_clk);1245fail_hw_init:1246 if (!tup->use_rx_pio)1247 tegra_uart_dma_channel_free(tup, true);1248fail_rx_dma:1249 if (!tup->use_tx_pio)1250 tegra_uart_dma_channel_free(tup, false);1251 return ret;1252}1253 1254/*1255 * Flush any TX data submitted for DMA and PIO. Called when the1256 * TX circular buffer is reset.1257 */1258static void tegra_uart_flush_buffer(struct uart_port *u)1259{1260 struct tegra_uart_port *tup = to_tegra_uport(u);1261 1262 tup->tx_bytes = 0;1263 if (tup->tx_dma_chan)1264 dmaengine_terminate_all(tup->tx_dma_chan);1265}1266 1267static void tegra_uart_shutdown(struct uart_port *u)1268{1269 struct tegra_uart_port *tup = to_tegra_uport(u);1270 1271 tegra_uart_hw_deinit(tup);1272 free_irq(u->irq, tup);1273}1274 1275static void tegra_uart_enable_ms(struct uart_port *u)1276{1277 struct tegra_uart_port *tup = to_tegra_uport(u);1278 1279 if (tup->enable_modem_interrupt) {1280 tup->ier_shadow |= UART_IER_MSI;1281 tegra_uart_write(tup, tup->ier_shadow, UART_IER);1282 }1283}1284 1285static void tegra_uart_set_termios(struct uart_port *u,1286 struct ktermios *termios,1287 const struct ktermios *oldtermios)1288{1289 struct tegra_uart_port *tup = to_tegra_uport(u);1290 unsigned int baud;1291 unsigned long flags;1292 unsigned int lcr;1293 unsigned char char_bits;1294 struct clk *parent_clk = clk_get_parent(tup->uart_clk);1295 unsigned long parent_clk_rate = clk_get_rate(parent_clk);1296 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;1297 int ret;1298 1299 max_divider *= 16;1300 uart_port_lock_irqsave(u, &flags);1301 1302 /* Changing configuration, it is safe to stop any rx now */1303 if (tup->rts_active)1304 set_rts(tup, false);1305 1306 /* Clear all interrupts as configuration is going to be changed */1307 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);1308 tegra_uart_read(tup, UART_IER);1309 tegra_uart_write(tup, 0, UART_IER);1310 tegra_uart_read(tup, UART_IER);1311 1312 /* Parity */1313 lcr = tup->lcr_shadow;1314 lcr &= ~UART_LCR_PARITY;1315 1316 /* CMSPAR isn't supported by this driver */1317 termios->c_cflag &= ~CMSPAR;1318 1319 if ((termios->c_cflag & PARENB) == PARENB) {1320 if (termios->c_cflag & PARODD) {1321 lcr |= UART_LCR_PARITY;1322 lcr &= ~UART_LCR_EPAR;1323 lcr &= ~UART_LCR_SPAR;1324 } else {1325 lcr |= UART_LCR_PARITY;1326 lcr |= UART_LCR_EPAR;1327 lcr &= ~UART_LCR_SPAR;1328 }1329 }1330 1331 char_bits = tty_get_char_size(termios->c_cflag);1332 lcr &= ~UART_LCR_WLEN8;1333 lcr |= UART_LCR_WLEN(char_bits);1334 1335 /* Stop bits */1336 if (termios->c_cflag & CSTOPB)1337 lcr |= UART_LCR_STOP;1338 else1339 lcr &= ~UART_LCR_STOP;1340 1341 tegra_uart_write(tup, lcr, UART_LCR);1342 tup->lcr_shadow = lcr;1343 tup->symb_bit = tty_get_frame_size(termios->c_cflag);1344 1345 /* Baud rate. */1346 baud = uart_get_baud_rate(u, termios, oldtermios,1347 parent_clk_rate/max_divider,1348 parent_clk_rate/16);1349 uart_port_unlock_irqrestore(u, flags);1350 ret = tegra_set_baudrate(tup, baud);1351 if (ret < 0) {1352 dev_err(tup->uport.dev, "Failed to set baud rate\n");1353 return;1354 }1355 if (tty_termios_baud_rate(termios))1356 tty_termios_encode_baud_rate(termios, baud, baud);1357 uart_port_lock_irqsave(u, &flags);1358 1359 /* Flow control */1360 if (termios->c_cflag & CRTSCTS) {1361 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;1362 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;1363 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);1364 /* if top layer has asked to set rts active then do so here */1365 if (tup->rts_active)1366 set_rts(tup, true);1367 } else {1368 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);1371 }1372 1373 /* update the port timeout based on new settings */1374 uart_update_timeout(u, termios->c_cflag, baud);1375 1376 /* Make sure all writes have completed */1377 tegra_uart_read(tup, UART_IER);1378 1379 /* Re-enable interrupt */1380 tegra_uart_write(tup, tup->ier_shadow, UART_IER);1381 tegra_uart_read(tup, UART_IER);1382 1383 tup->uport.ignore_status_mask = 0;1384 /* Ignore all characters if CREAD is not set */1385 if ((termios->c_cflag & CREAD) == 0)1386 tup->uport.ignore_status_mask |= UART_LSR_DR;1387 if (termios->c_iflag & IGNBRK)1388 tup->uport.ignore_status_mask |= UART_LSR_BI;1389 1390 uart_port_unlock_irqrestore(u, flags);1391}1392 1393static const char *tegra_uart_type(struct uart_port *u)1394{1395 return TEGRA_UART_TYPE;1396}1397 1398static const struct uart_ops tegra_uart_ops = {1399 .tx_empty = tegra_uart_tx_empty,1400 .set_mctrl = tegra_uart_set_mctrl,1401 .get_mctrl = tegra_uart_get_mctrl,1402 .stop_tx = tegra_uart_stop_tx,1403 .start_tx = tegra_uart_start_tx,1404 .stop_rx = tegra_uart_stop_rx,1405 .flush_buffer = tegra_uart_flush_buffer,1406 .enable_ms = tegra_uart_enable_ms,1407 .break_ctl = tegra_uart_break_ctl,1408 .startup = tegra_uart_startup,1409 .shutdown = tegra_uart_shutdown,1410 .set_termios = tegra_uart_set_termios,1411 .type = tegra_uart_type,1412 .request_port = tegra_uart_request_port,1413 .release_port = tegra_uart_release_port,1414};1415 1416static struct uart_driver tegra_uart_driver = {1417 .owner = THIS_MODULE,1418 .driver_name = "tegra_hsuart",1419 .dev_name = "ttyTHS",1420 .cons = NULL,1421 .nr = TEGRA_UART_MAXIMUM,1422};1423 1424static int tegra_uart_parse_dt(struct platform_device *pdev,1425 struct tegra_uart_port *tup)1426{1427 struct device_node *np = pdev->dev.of_node;1428 int port;1429 int ret;1430 int index;1431 u32 pval;1432 int count;1433 int n_entries;1434 1435 port = of_alias_get_id(np, "serial");1436 if (port < 0) {1437 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);1438 return port;1439 }1440 tup->uport.line = port;1441 1442 tup->enable_modem_interrupt = of_property_read_bool(np,1443 "nvidia,enable-modem-interrupt");1444 1445 index = of_property_match_string(np, "dma-names", "rx");1446 if (index < 0) {1447 tup->use_rx_pio = true;1448 dev_info(&pdev->dev, "RX in PIO mode\n");1449 }1450 index = of_property_match_string(np, "dma-names", "tx");1451 if (index < 0) {1452 tup->use_tx_pio = true;1453 dev_info(&pdev->dev, "TX in PIO mode\n");1454 }1455 1456 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");1457 if (n_entries > 0) {1458 tup->n_adjustable_baud_rates = n_entries / 3;1459 tup->baud_tolerance =1460 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *1461 sizeof(*tup->baud_tolerance), GFP_KERNEL);1462 if (!tup->baud_tolerance)1463 return -ENOMEM;1464 for (count = 0, index = 0; count < n_entries; count += 3,1465 index++) {1466 ret =1467 of_property_read_u32_index(np,1468 "nvidia,adjust-baud-rates",1469 count, &pval);1470 if (!ret)1471 tup->baud_tolerance[index].lower_range_baud =1472 pval;1473 ret =1474 of_property_read_u32_index(np,1475 "nvidia,adjust-baud-rates",1476 count + 1, &pval);1477 if (!ret)1478 tup->baud_tolerance[index].upper_range_baud =1479 pval;1480 ret =1481 of_property_read_u32_index(np,1482 "nvidia,adjust-baud-rates",1483 count + 2, &pval);1484 if (!ret)1485 tup->baud_tolerance[index].tolerance =1486 (s32)pval;1487 }1488 } else {1489 tup->n_adjustable_baud_rates = 0;1490 }1491 1492 return 0;1493}1494 1495static struct tegra_uart_chip_data tegra20_uart_chip_data = {1496 .tx_fifo_full_status = false,1497 .allow_txfifo_reset_fifo_mode = true,1498 .support_clk_src_div = false,1499 .fifo_mode_enable_status = false,1500 .uart_max_port = 5,1501 .max_dma_burst_bytes = 4,1502 .error_tolerance_low_range = -4,1503 .error_tolerance_high_range = 4,1504};1505 1506static struct tegra_uart_chip_data tegra30_uart_chip_data = {1507 .tx_fifo_full_status = true,1508 .allow_txfifo_reset_fifo_mode = false,1509 .support_clk_src_div = true,1510 .fifo_mode_enable_status = false,1511 .uart_max_port = 5,1512 .max_dma_burst_bytes = 4,1513 .error_tolerance_low_range = -4,1514 .error_tolerance_high_range = 4,1515};1516 1517static struct tegra_uart_chip_data tegra186_uart_chip_data = {1518 .tx_fifo_full_status = true,1519 .allow_txfifo_reset_fifo_mode = false,1520 .support_clk_src_div = true,1521 .fifo_mode_enable_status = true,1522 .uart_max_port = 8,1523 .max_dma_burst_bytes = 8,1524 .error_tolerance_low_range = 0,1525 .error_tolerance_high_range = 4,1526};1527 1528static struct tegra_uart_chip_data tegra194_uart_chip_data = {1529 .tx_fifo_full_status = true,1530 .allow_txfifo_reset_fifo_mode = false,1531 .support_clk_src_div = true,1532 .fifo_mode_enable_status = true,1533 .uart_max_port = 8,1534 .max_dma_burst_bytes = 8,1535 .error_tolerance_low_range = -2,1536 .error_tolerance_high_range = 2,1537};1538 1539static const struct of_device_id tegra_uart_of_match[] = {1540 {1541 .compatible = "nvidia,tegra30-hsuart",1542 .data = &tegra30_uart_chip_data,1543 }, {1544 .compatible = "nvidia,tegra20-hsuart",1545 .data = &tegra20_uart_chip_data,1546 }, {1547 .compatible = "nvidia,tegra186-hsuart",1548 .data = &tegra186_uart_chip_data,1549 }, {1550 .compatible = "nvidia,tegra194-hsuart",1551 .data = &tegra194_uart_chip_data,1552 }, {1553 },1554};1555MODULE_DEVICE_TABLE(of, tegra_uart_of_match);1556 1557static int tegra_uart_probe(struct platform_device *pdev)1558{1559 struct tegra_uart_port *tup;1560 struct uart_port *u;1561 struct resource *resource;1562 int ret;1563 const struct tegra_uart_chip_data *cdata;1564 1565 cdata = of_device_get_match_data(&pdev->dev);1566 if (!cdata) {1567 dev_err(&pdev->dev, "Error: No device match found\n");1568 return -ENODEV;1569 }1570 1571 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);1572 if (!tup) {1573 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");1574 return -ENOMEM;1575 }1576 1577 ret = tegra_uart_parse_dt(pdev, tup);1578 if (ret < 0)1579 return ret;1580 1581 u = &tup->uport;1582 u->dev = &pdev->dev;1583 u->ops = &tegra_uart_ops;1584 u->type = PORT_TEGRA;1585 u->fifosize = 32;1586 tup->cdata = cdata;1587 1588 platform_set_drvdata(pdev, tup);1589 1590 u->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &resource);1591 if (IS_ERR(u->membase))1592 return PTR_ERR(u->membase);1593 u->mapbase = resource->start;1594 1595 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);1596 if (IS_ERR(tup->uart_clk))1597 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock");1598 1599 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");1600 if (IS_ERR(tup->rst)) {1601 dev_err(&pdev->dev, "Couldn't get the reset\n");1602 return PTR_ERR(tup->rst);1603 }1604 1605 u->iotype = UPIO_MEM32;1606 ret = platform_get_irq(pdev, 0);1607 if (ret < 0)1608 return ret;1609 u->irq = ret;1610 u->regshift = 2;1611 ret = uart_add_one_port(&tegra_uart_driver, u);1612 if (ret < 0) {1613 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);1614 return ret;1615 }1616 return ret;1617}1618 1619static void tegra_uart_remove(struct platform_device *pdev)1620{1621 struct tegra_uart_port *tup = platform_get_drvdata(pdev);1622 struct uart_port *u = &tup->uport;1623 1624 uart_remove_one_port(&tegra_uart_driver, u);1625}1626 1627#ifdef CONFIG_PM_SLEEP1628static int tegra_uart_suspend(struct device *dev)1629{1630 struct tegra_uart_port *tup = dev_get_drvdata(dev);1631 struct uart_port *u = &tup->uport;1632 1633 return uart_suspend_port(&tegra_uart_driver, u);1634}1635 1636static int tegra_uart_resume(struct device *dev)1637{1638 struct tegra_uart_port *tup = dev_get_drvdata(dev);1639 struct uart_port *u = &tup->uport;1640 1641 return uart_resume_port(&tegra_uart_driver, u);1642}1643#endif1644 1645static const struct dev_pm_ops tegra_uart_pm_ops = {1646 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)1647};1648 1649static struct platform_driver tegra_uart_platform_driver = {1650 .probe = tegra_uart_probe,1651 .remove_new = tegra_uart_remove,1652 .driver = {1653 .name = "serial-tegra",1654 .of_match_table = tegra_uart_of_match,1655 .pm = &tegra_uart_pm_ops,1656 },1657};1658 1659static int __init tegra_uart_init(void)1660{1661 int ret;1662 struct device_node *node;1663 const struct of_device_id *match = NULL;1664 const struct tegra_uart_chip_data *cdata = NULL;1665 1666 node = of_find_matching_node(NULL, tegra_uart_of_match);1667 if (node)1668 match = of_match_node(tegra_uart_of_match, node);1669 of_node_put(node);1670 if (match)1671 cdata = match->data;1672 if (cdata)1673 tegra_uart_driver.nr = cdata->uart_max_port;1674 1675 ret = uart_register_driver(&tegra_uart_driver);1676 if (ret < 0) {1677 pr_err("Could not register %s driver\n",1678 tegra_uart_driver.driver_name);1679 return ret;1680 }1681 1682 ret = platform_driver_register(&tegra_uart_platform_driver);1683 if (ret < 0) {1684 pr_err("Uart platform driver register failed, e = %d\n", ret);1685 uart_unregister_driver(&tegra_uart_driver);1686 return ret;1687 }1688 return 0;1689}1690 1691static void __exit tegra_uart_exit(void)1692{1693 pr_info("Unloading tegra uart driver\n");1694 platform_driver_unregister(&tegra_uart_platform_driver);1695 uart_unregister_driver(&tegra_uart_driver);1696}1697 1698module_init(tegra_uart_init);1699module_exit(tegra_uart_exit);1700 1701MODULE_ALIAS("platform:serial-tegra");1702MODULE_DESCRIPTION("High speed UART driver for tegra chipset");1703MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");1704MODULE_LICENSE("GPL v2");1705