227 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) Maxime Coquelin 20154 * Copyright (C) STMicroelectronics SA 20175 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>6 * Gerald Baeza <gerald_baeza@yahoo.fr>7 */8 9#define DRIVER_NAME "stm32-usart"10 11struct stm32_usart_offsets {12 u16 cr1;13 u16 cr2;14 u16 cr3;15 u16 brr;16 u16 gtpr;17 u16 rtor;18 u16 rqr;19 u16 isr;20 u16 icr;21 u16 rdr;22 u16 tdr;23 u16 presc;24 u16 hwcfgr1;25};26 27struct stm32_usart_config {28 u8 uart_enable_bit; /* USART_CR1_UE */29 bool has_7bits_data;30 bool has_swap;31 bool has_wakeup;32 bool has_fifo;33};34 35struct stm32_usart_info {36 struct stm32_usart_offsets ofs;37 struct stm32_usart_config cfg;38};39 40#define UNDEF_REG 0xffff41 42/* USART_SR (F4) / USART_ISR (F7) */43#define USART_SR_PE BIT(0)44#define USART_SR_FE BIT(1)45#define USART_SR_NE BIT(2) /* F7 (NF for F4) */46#define USART_SR_ORE BIT(3)47#define USART_SR_IDLE BIT(4)48#define USART_SR_RXNE BIT(5)49#define USART_SR_TC BIT(6)50#define USART_SR_TXE BIT(7)51#define USART_SR_CTSIF BIT(9)52#define USART_SR_CTS BIT(10) /* F7 */53#define USART_SR_RTOF BIT(11) /* F7 */54#define USART_SR_EOBF BIT(12) /* F7 */55#define USART_SR_ABRE BIT(14) /* F7 */56#define USART_SR_ABRF BIT(15) /* F7 */57#define USART_SR_BUSY BIT(16) /* F7 */58#define USART_SR_CMF BIT(17) /* F7 */59#define USART_SR_SBKF BIT(18) /* F7 */60#define USART_SR_WUF BIT(20) /* H7 */61#define USART_SR_TEACK BIT(21) /* F7 */62#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_NE | USART_SR_FE |\63 USART_SR_PE)64/* Dummy bits */65#define USART_SR_DUMMY_RX BIT(16)66 67/* USART_DR */68#define USART_DR_MASK GENMASK(8, 0)69 70/* USART_BRR */71#define USART_BRR_DIV_F_MASK GENMASK(3, 0)72#define USART_BRR_DIV_M_MASK GENMASK(15, 4)73#define USART_BRR_DIV_M_SHIFT 474#define USART_BRR_04_R_SHIFT 175#define USART_BRR_MASK (USART_BRR_DIV_M_MASK | USART_BRR_DIV_F_MASK)76 77/* USART_CR1 */78#define USART_CR1_SBK BIT(0)79#define USART_CR1_RWU BIT(1) /* F4 */80#define USART_CR1_UESM BIT(1) /* H7 */81#define USART_CR1_RE BIT(2)82#define USART_CR1_TE BIT(3)83#define USART_CR1_IDLEIE BIT(4)84#define USART_CR1_RXNEIE BIT(5)85#define USART_CR1_TCIE BIT(6)86#define USART_CR1_TXEIE BIT(7)87#define USART_CR1_PEIE BIT(8)88#define USART_CR1_PS BIT(9)89#define USART_CR1_PCE BIT(10)90#define USART_CR1_WAKE BIT(11)91#define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */92#define USART_CR1_MME BIT(13) /* F7 */93#define USART_CR1_CMIE BIT(14) /* F7 */94#define USART_CR1_OVER8 BIT(15)95#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */96#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */97#define USART_CR1_RTOIE BIT(26) /* F7 */98#define USART_CR1_EOBIE BIT(27) /* F7 */99#define USART_CR1_M1 BIT(28) /* F7 */100#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))101#define USART_CR1_FIFOEN BIT(29) /* H7 */102#define USART_CR1_DEAT_SHIFT 21103#define USART_CR1_DEDT_SHIFT 16104 105/* USART_CR2 */106#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */107#define USART_CR2_ADDM7 BIT(4) /* F7 */108#define USART_CR2_LBCL BIT(8)109#define USART_CR2_CPHA BIT(9)110#define USART_CR2_CPOL BIT(10)111#define USART_CR2_CLKEN BIT(11)112#define USART_CR2_STOP_2B BIT(13)113#define USART_CR2_STOP_MASK GENMASK(13, 12)114#define USART_CR2_LINEN BIT(14)115#define USART_CR2_SWAP BIT(15) /* F7 */116#define USART_CR2_RXINV BIT(16) /* F7 */117#define USART_CR2_TXINV BIT(17) /* F7 */118#define USART_CR2_DATAINV BIT(18) /* F7 */119#define USART_CR2_MSBFIRST BIT(19) /* F7 */120#define USART_CR2_ABREN BIT(20) /* F7 */121#define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */122#define USART_CR2_RTOEN BIT(23) /* F7 */123#define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */124 125/* USART_CR3 */126#define USART_CR3_EIE BIT(0)127#define USART_CR3_IREN BIT(1)128#define USART_CR3_IRLP BIT(2)129#define USART_CR3_HDSEL BIT(3)130#define USART_CR3_NACK BIT(4)131#define USART_CR3_SCEN BIT(5)132#define USART_CR3_DMAR BIT(6)133#define USART_CR3_DMAT BIT(7)134#define USART_CR3_RTSE BIT(8)135#define USART_CR3_CTSE BIT(9)136#define USART_CR3_CTSIE BIT(10)137#define USART_CR3_ONEBIT BIT(11)138#define USART_CR3_OVRDIS BIT(12) /* F7 */139#define USART_CR3_DDRE BIT(13) /* F7 */140#define USART_CR3_DEM BIT(14) /* F7 */141#define USART_CR3_DEP BIT(15) /* F7 */142#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */143#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */144#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */145#define USART_CR3_WUFIE BIT(22) /* H7 */146#define USART_CR3_TXFTIE BIT(23) /* H7 */147#define USART_CR3_TCBGTIE BIT(24) /* H7 */148#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */149#define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */150#define USART_CR3_RXFTIE BIT(28) /* H7 */151#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */152#define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */153 154/* USART_GTPR */155#define USART_GTPR_PSC_MASK GENMASK(7, 0)156#define USART_GTPR_GT_MASK GENMASK(15, 8)157 158/* USART_RTOR */159#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */160#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */161 162/* USART_RQR */163#define USART_RQR_ABRRQ BIT(0) /* F7 */164#define USART_RQR_SBKRQ BIT(1) /* F7 */165#define USART_RQR_MMRQ BIT(2) /* F7 */166#define USART_RQR_RXFRQ BIT(3) /* F7 */167#define USART_RQR_TXFRQ BIT(4) /* F7 */168 169/* USART_ICR */170#define USART_ICR_PECF BIT(0) /* F7 */171#define USART_ICR_FECF BIT(1) /* F7 */172#define USART_ICR_ORECF BIT(3) /* F7 */173#define USART_ICR_IDLECF BIT(4) /* F7 */174#define USART_ICR_TCCF BIT(6) /* F7 */175#define USART_ICR_CTSCF BIT(9) /* F7 */176#define USART_ICR_RTOCF BIT(11) /* F7 */177#define USART_ICR_EOBCF BIT(12) /* F7 */178#define USART_ICR_CMCF BIT(17) /* F7 */179#define USART_ICR_WUCF BIT(20) /* H7 */180 181/* USART_PRESC */182#define USART_PRESC GENMASK(3, 0) /* H7 */183#define USART_PRESC_MAX 0b1011184 185/* USART_HWCFCR1 */186#define USART_HWCFGR1_CFG8 GENMASK(31, 28) /* MP1 */187 188#define STM32_SERIAL_NAME "ttySTM"189#define STM32_MAX_PORTS 9190#define STM32H7_USART_FIFO_SIZE 16191 192#define RX_BUF_L 4096 /* dma rx buffer length */193#define RX_BUF_P (RX_BUF_L / 2) /* dma rx buffer period */194#define TX_BUF_L RX_BUF_L /* dma tx buffer length */195 196#define STM32_USART_TIMEOUT_USEC USEC_PER_SEC /* 1s timeout in µs */197 198struct stm32_port {199 struct uart_port port;200 struct clk *clk;201 const struct stm32_usart_info *info;202 struct dma_chan *rx_ch; /* dma rx channel */203 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */204 unsigned char *rx_buf; /* dma rx buffer cpu address */205 struct dma_chan *tx_ch; /* dma tx channel */206 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */207 unsigned char *tx_buf; /* dma tx buffer cpu address */208 u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */209 u32 cr3_irq; /* USART_CR3_RXFTIE */210 int last_res;211 bool tx_dma_busy; /* dma tx transaction in progress */212 bool rx_dma_busy; /* dma rx transaction in progress */213 bool throttled; /* port throttled */214 bool hw_flow_control;215 bool swap; /* swap RX & TX pins */216 bool fifoen;217 int rxftcfg; /* RX FIFO threshold CFG */218 int txftcfg; /* TX FIFO threshold CFG */219 bool wakeup_src;220 int rdr_mask; /* receive data register mask */221 struct mctrl_gpios *gpios; /* modem control gpios */222 struct dma_tx_state rx_dma_state;223};224 225static struct stm32_port stm32_ports[STM32_MAX_PORTS];226static struct uart_driver stm32_usart_driver;227