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1// SPDX-License-Identifier: GPL-2.02/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.3 *4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)5 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)6 *7 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.8 * Maxim Krasnyanskiy <maxk@qualcomm.com>9 *10 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud11 * rates to be programmed into the UART. Also eliminated a lot of12 * duplicated code in the console setup.13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-1214 *15 * Ported to new 2.5.x UART layer.16 * David S. Miller <davem@davemloft.net>17 */18 19#include <linux/module.h>20#include <linux/kernel.h>21#include <linux/errno.h>22#include <linux/tty.h>23#include <linux/tty_flip.h>24#include <linux/major.h>25#include <linux/string.h>26#include <linux/ptrace.h>27#include <linux/ioport.h>28#include <linux/circ_buf.h>29#include <linux/serial.h>30#include <linux/sysrq.h>31#include <linux/console.h>32#include <linux/spinlock.h>33#include <linux/slab.h>34#include <linux/delay.h>35#include <linux/init.h>36#include <linux/of.h>37#include <linux/platform_device.h>38 39#include <linux/io.h>40#include <asm/irq.h>41#include <asm/prom.h>42#include <asm/setup.h>43 44#include <linux/serial_core.h>45#include <linux/sunserialcore.h>46 47#include "sunsab.h"48 49struct uart_sunsab_port {50 struct uart_port port; /* Generic UART port */51 union sab82532_async_regs __iomem *regs; /* Chip registers */52 unsigned long irqflags; /* IRQ state flags */53 int dsr; /* Current DSR state */54 unsigned int cec_timeout; /* Chip poll timeout... */55 unsigned int tec_timeout; /* likewise */56 unsigned char interrupt_mask0;/* ISR0 masking */57 unsigned char interrupt_mask1;/* ISR1 masking */58 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */59 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */60 unsigned int gis_shift;61 int type; /* SAB82532 version */62 63 /* Setting configuration bits while the transmitter is active64 * can cause garbage characters to get emitted by the chip.65 * Therefore, we cache such writes here and do the real register66 * write the next time the transmitter becomes idle.67 */68 unsigned int cached_ebrg;69 unsigned char cached_mode;70 unsigned char cached_pvr;71 unsigned char cached_dafo;72};73 74/*75 * This assumes you have a 29.4912 MHz clock for your UART.76 */77#define SAB_BASE_BAUD ( 29491200 / 16 )78 79static char *sab82532_version[16] = {80 "V1.0", "V2.0", "V3.2", "V(0x03)",81 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",82 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",83 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"84};85 86#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */87#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */88 89#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */90#define SAB82532_XMIT_FIFO_SIZE 3291 92static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)93{94 int timeout = up->tec_timeout;95 96 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)97 udelay(1);98}99 100static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)101{102 int timeout = up->cec_timeout;103 104 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)105 udelay(1);106}107 108static struct tty_port *109receive_chars(struct uart_sunsab_port *up,110 union sab82532_irq_status *stat)111{112 struct tty_port *port = NULL;113 unsigned char buf[32];114 int saw_console_brk = 0;115 int free_fifo = 0;116 int count = 0;117 int i;118 119 if (up->port.state != NULL) /* Unopened serial console */120 port = &up->port.state->port;121 122 /* Read number of BYTES (Character + Status) available. */123 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {124 count = SAB82532_RECV_FIFO_SIZE;125 free_fifo++;126 }127 128 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {129 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);130 free_fifo++;131 }132 133 /* Issue a FIFO read command in case we where idle. */134 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {135 sunsab_cec_wait(up);136 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);137 return port;138 }139 140 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)141 free_fifo++;142 143 /* Read the FIFO. */144 for (i = 0; i < count; i++)145 buf[i] = readb(&up->regs->r.rfifo[i]);146 147 /* Issue Receive Message Complete command. */148 if (free_fifo) {149 sunsab_cec_wait(up);150 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);151 }152 153 /* Count may be zero for BRK, so we check for it here */154 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&155 (up->port.line == up->port.cons->index))156 saw_console_brk = 1;157 158 if (count == 0) {159 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {160 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |161 SAB82532_ISR0_FERR);162 up->port.icount.brk++;163 uart_handle_break(&up->port);164 }165 }166 167 for (i = 0; i < count; i++) {168 unsigned char ch = buf[i], flag;169 170 flag = TTY_NORMAL;171 up->port.icount.rx++;172 173 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |174 SAB82532_ISR0_FERR |175 SAB82532_ISR0_RFO)) ||176 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {177 /*178 * For statistics only179 */180 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {181 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |182 SAB82532_ISR0_FERR);183 up->port.icount.brk++;184 /*185 * We do the SysRQ and SAK checking186 * here because otherwise the break187 * may get masked by ignore_status_mask188 * or read_status_mask.189 */190 if (uart_handle_break(&up->port))191 continue;192 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)193 up->port.icount.parity++;194 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)195 up->port.icount.frame++;196 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)197 up->port.icount.overrun++;198 199 /*200 * Mask off conditions which should be ingored.201 */202 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);203 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);204 205 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {206 flag = TTY_BREAK;207 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)208 flag = TTY_PARITY;209 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)210 flag = TTY_FRAME;211 }212 213 if (uart_handle_sysrq_char(&up->port, ch) || !port)214 continue;215 216 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&217 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)218 tty_insert_flip_char(port, ch, flag);219 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)220 tty_insert_flip_char(port, 0, TTY_OVERRUN);221 }222 223 if (saw_console_brk)224 sun_do_break();225 226 return port;227}228 229static void sunsab_stop_tx(struct uart_port *);230static void sunsab_tx_idle(struct uart_sunsab_port *);231 232static void transmit_chars(struct uart_sunsab_port *up,233 union sab82532_irq_status *stat)234{235 struct tty_port *tport = &up->port.state->port;236 int i;237 238 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {239 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;240 writeb(up->interrupt_mask1, &up->regs->w.imr1);241 set_bit(SAB82532_ALLS, &up->irqflags);242 }243 244#if 0 /* bde@nwlink.com says this check causes problems */245 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))246 return;247#endif248 249 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))250 return;251 252 set_bit(SAB82532_XPR, &up->irqflags);253 sunsab_tx_idle(up);254 255 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&up->port)) {256 up->interrupt_mask1 |= SAB82532_IMR1_XPR;257 writeb(up->interrupt_mask1, &up->regs->w.imr1);258 return;259 }260 261 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);262 writeb(up->interrupt_mask1, &up->regs->w.imr1);263 clear_bit(SAB82532_ALLS, &up->irqflags);264 265 /* Stuff 32 bytes into Transmit FIFO. */266 clear_bit(SAB82532_XPR, &up->irqflags);267 for (i = 0; i < up->port.fifosize; i++) {268 unsigned char ch;269 270 if (!uart_fifo_get(&up->port, &ch))271 break;272 273 writeb(ch, &up->regs->w.xfifo[i]);274 }275 276 /* Issue a Transmit Frame command. */277 sunsab_cec_wait(up);278 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);279 280 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)281 uart_write_wakeup(&up->port);282 283 if (kfifo_is_empty(&tport->xmit_fifo))284 sunsab_stop_tx(&up->port);285}286 287static void check_status(struct uart_sunsab_port *up,288 union sab82532_irq_status *stat)289{290 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)291 uart_handle_dcd_change(&up->port,292 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));293 294 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)295 uart_handle_cts_change(&up->port,296 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));297 298 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {299 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;300 up->port.icount.dsr++;301 }302 303 wake_up_interruptible(&up->port.state->port.delta_msr_wait);304}305 306static irqreturn_t sunsab_interrupt(int irq, void *dev_id)307{308 struct uart_sunsab_port *up = dev_id;309 struct tty_port *port = NULL;310 union sab82532_irq_status status;311 unsigned long flags;312 unsigned char gis;313 314 uart_port_lock_irqsave(&up->port, &flags);315 316 status.stat = 0;317 gis = readb(&up->regs->r.gis) >> up->gis_shift;318 if (gis & 1)319 status.sreg.isr0 = readb(&up->regs->r.isr0);320 if (gis & 2)321 status.sreg.isr1 = readb(&up->regs->r.isr1);322 323 if (status.stat) {324 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |325 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||326 (status.sreg.isr1 & SAB82532_ISR1_BRK))327 port = receive_chars(up, &status);328 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||329 (status.sreg.isr1 & SAB82532_ISR1_CSC))330 check_status(up, &status);331 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))332 transmit_chars(up, &status);333 }334 335 uart_port_unlock_irqrestore(&up->port, flags);336 337 if (port)338 tty_flip_buffer_push(port);339 340 return IRQ_HANDLED;341}342 343/* port->lock is not held. */344static unsigned int sunsab_tx_empty(struct uart_port *port)345{346 struct uart_sunsab_port *up =347 container_of(port, struct uart_sunsab_port, port);348 int ret;349 350 /* Do not need a lock for a state test like this. */351 if (test_bit(SAB82532_ALLS, &up->irqflags))352 ret = TIOCSER_TEMT;353 else354 ret = 0;355 356 return ret;357}358 359/* port->lock held by caller. */360static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)361{362 struct uart_sunsab_port *up =363 container_of(port, struct uart_sunsab_port, port);364 365 if (mctrl & TIOCM_RTS) {366 up->cached_mode &= ~SAB82532_MODE_FRTS;367 up->cached_mode |= SAB82532_MODE_RTS;368 } else {369 up->cached_mode |= (SAB82532_MODE_FRTS |370 SAB82532_MODE_RTS);371 }372 if (mctrl & TIOCM_DTR) {373 up->cached_pvr &= ~(up->pvr_dtr_bit);374 } else {375 up->cached_pvr |= up->pvr_dtr_bit;376 }377 378 set_bit(SAB82532_REGS_PENDING, &up->irqflags);379 if (test_bit(SAB82532_XPR, &up->irqflags))380 sunsab_tx_idle(up);381}382 383/* port->lock is held by caller and interrupts are disabled. */384static unsigned int sunsab_get_mctrl(struct uart_port *port)385{386 struct uart_sunsab_port *up =387 container_of(port, struct uart_sunsab_port, port);388 unsigned char val;389 unsigned int result;390 391 result = 0;392 393 val = readb(&up->regs->r.pvr);394 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;395 396 val = readb(&up->regs->r.vstr);397 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;398 399 val = readb(&up->regs->r.star);400 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;401 402 return result;403}404 405/* port->lock held by caller. */406static void sunsab_stop_tx(struct uart_port *port)407{408 struct uart_sunsab_port *up =409 container_of(port, struct uart_sunsab_port, port);410 411 up->interrupt_mask1 |= SAB82532_IMR1_XPR;412 writeb(up->interrupt_mask1, &up->regs->w.imr1);413}414 415/* port->lock held by caller. */416static void sunsab_tx_idle(struct uart_sunsab_port *up)417{418 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {419 u8 tmp;420 421 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);422 writeb(up->cached_mode, &up->regs->rw.mode);423 writeb(up->cached_pvr, &up->regs->rw.pvr);424 writeb(up->cached_dafo, &up->regs->w.dafo);425 426 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);427 tmp = readb(&up->regs->rw.ccr2);428 tmp &= ~0xc0;429 tmp |= (up->cached_ebrg >> 2) & 0xc0;430 writeb(tmp, &up->regs->rw.ccr2);431 }432}433 434/* port->lock held by caller. */435static void sunsab_start_tx(struct uart_port *port)436{437 struct uart_sunsab_port *up =438 container_of(port, struct uart_sunsab_port, port);439 struct tty_port *tport = &up->port.state->port;440 int i;441 442 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port))443 return;444 445 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);446 writeb(up->interrupt_mask1, &up->regs->w.imr1);447 448 if (!test_bit(SAB82532_XPR, &up->irqflags))449 return;450 451 clear_bit(SAB82532_ALLS, &up->irqflags);452 clear_bit(SAB82532_XPR, &up->irqflags);453 454 for (i = 0; i < up->port.fifosize; i++) {455 unsigned char ch;456 457 if (!uart_fifo_get(&up->port, &ch))458 break;459 460 writeb(ch, &up->regs->w.xfifo[i]);461 }462 463 /* Issue a Transmit Frame command. */464 sunsab_cec_wait(up);465 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);466}467 468/* port->lock is not held. */469static void sunsab_send_xchar(struct uart_port *port, char ch)470{471 struct uart_sunsab_port *up =472 container_of(port, struct uart_sunsab_port, port);473 unsigned long flags;474 475 if (ch == __DISABLED_CHAR)476 return;477 478 uart_port_lock_irqsave(&up->port, &flags);479 480 sunsab_tec_wait(up);481 writeb(ch, &up->regs->w.tic);482 483 uart_port_unlock_irqrestore(&up->port, flags);484}485 486/* port->lock held by caller. */487static void sunsab_stop_rx(struct uart_port *port)488{489 struct uart_sunsab_port *up =490 container_of(port, struct uart_sunsab_port, port);491 492 up->interrupt_mask0 |= SAB82532_IMR0_TCD;493 writeb(up->interrupt_mask1, &up->regs->w.imr0);494}495 496/* port->lock is not held. */497static void sunsab_break_ctl(struct uart_port *port, int break_state)498{499 struct uart_sunsab_port *up =500 container_of(port, struct uart_sunsab_port, port);501 unsigned long flags;502 unsigned char val;503 504 uart_port_lock_irqsave(&up->port, &flags);505 506 val = up->cached_dafo;507 if (break_state)508 val |= SAB82532_DAFO_XBRK;509 else510 val &= ~SAB82532_DAFO_XBRK;511 up->cached_dafo = val;512 513 set_bit(SAB82532_REGS_PENDING, &up->irqflags);514 if (test_bit(SAB82532_XPR, &up->irqflags))515 sunsab_tx_idle(up);516 517 uart_port_unlock_irqrestore(&up->port, flags);518}519 520/* port->lock is not held. */521static int sunsab_startup(struct uart_port *port)522{523 struct uart_sunsab_port *up =524 container_of(port, struct uart_sunsab_port, port);525 unsigned long flags;526 unsigned char tmp;527 int err = request_irq(up->port.irq, sunsab_interrupt,528 IRQF_SHARED, "sab", up);529 if (err)530 return err;531 532 uart_port_lock_irqsave(&up->port, &flags);533 534 /*535 * Wait for any commands or immediate characters536 */537 sunsab_cec_wait(up);538 sunsab_tec_wait(up);539 540 /*541 * Clear the FIFO buffers.542 */543 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);544 sunsab_cec_wait(up);545 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);546 547 /*548 * Clear the interrupt registers.549 */550 (void) readb(&up->regs->r.isr0);551 (void) readb(&up->regs->r.isr1);552 553 /*554 * Now, initialize the UART555 */556 writeb(0, &up->regs->w.ccr0); /* power-down */557 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |558 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);559 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);560 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |561 SAB82532_CCR2_TOE, &up->regs->w.ccr2);562 writeb(0, &up->regs->w.ccr3);563 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);564 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |565 SAB82532_MODE_RAC);566 writeb(up->cached_mode, &up->regs->w.mode);567 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);568 569 tmp = readb(&up->regs->rw.ccr0);570 tmp |= SAB82532_CCR0_PU; /* power-up */571 writeb(tmp, &up->regs->rw.ccr0);572 573 /*574 * Finally, enable interrupts575 */576 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |577 SAB82532_IMR0_PLLA);578 writeb(up->interrupt_mask0, &up->regs->w.imr0);579 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |580 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |581 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |582 SAB82532_IMR1_XPR);583 writeb(up->interrupt_mask1, &up->regs->w.imr1);584 set_bit(SAB82532_ALLS, &up->irqflags);585 set_bit(SAB82532_XPR, &up->irqflags);586 587 uart_port_unlock_irqrestore(&up->port, flags);588 589 return 0;590}591 592/* port->lock is not held. */593static void sunsab_shutdown(struct uart_port *port)594{595 struct uart_sunsab_port *up =596 container_of(port, struct uart_sunsab_port, port);597 unsigned long flags;598 599 uart_port_lock_irqsave(&up->port, &flags);600 601 /* Disable Interrupts */602 up->interrupt_mask0 = 0xff;603 writeb(up->interrupt_mask0, &up->regs->w.imr0);604 up->interrupt_mask1 = 0xff;605 writeb(up->interrupt_mask1, &up->regs->w.imr1);606 607 /* Disable break condition */608 up->cached_dafo = readb(&up->regs->rw.dafo);609 up->cached_dafo &= ~SAB82532_DAFO_XBRK;610 writeb(up->cached_dafo, &up->regs->rw.dafo);611 612 /* Disable Receiver */613 up->cached_mode &= ~SAB82532_MODE_RAC;614 writeb(up->cached_mode, &up->regs->rw.mode);615 616 /*617 * XXX FIXME618 *619 * If the chip is powered down here the system hangs/crashes during620 * reboot or shutdown. This needs to be investigated further,621 * similar behaviour occurs in 2.4 when the driver is configured622 * as a module only. One hint may be that data is sometimes623 * transmitted at 9600 baud during shutdown (regardless of the624 * speed the chip was configured for when the port was open).625 */626#if 0627 /* Power Down */628 tmp = readb(&up->regs->rw.ccr0);629 tmp &= ~SAB82532_CCR0_PU;630 writeb(tmp, &up->regs->rw.ccr0);631#endif632 633 uart_port_unlock_irqrestore(&up->port, flags);634 free_irq(up->port.irq, up);635}636 637/*638 * This is used to figure out the divisor speeds.639 *640 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),641 *642 * with 0 <= N < 64 and 0 <= M < 16643 */644 645static void calc_ebrg(int baud, int *n_ret, int *m_ret)646{647 int n, m;648 649 if (baud == 0) {650 *n_ret = 0;651 *m_ret = 0;652 return;653 }654 655 /*656 * We scale numbers by 10 so that we get better accuracy657 * without having to use floating point. Here we increment m658 * until n is within the valid range.659 */660 n = (SAB_BASE_BAUD * 10) / baud;661 m = 0;662 while (n >= 640) {663 n = n / 2;664 m++;665 }666 n = (n+5) / 10;667 /*668 * We try very hard to avoid speeds with M == 0 since they may669 * not work correctly for XTAL frequences above 10 MHz.670 */671 if ((m == 0) && ((n & 1) == 0)) {672 n = n / 2;673 m++;674 }675 *n_ret = n - 1;676 *m_ret = m;677}678 679/* Internal routine, port->lock is held and local interrupts are disabled. */680static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,681 unsigned int iflag, unsigned int baud,682 unsigned int quot)683{684 unsigned char dafo;685 int n, m;686 687 /* Byte size and parity */688 switch (cflag & CSIZE) {689 case CS5: dafo = SAB82532_DAFO_CHL5; break;690 case CS6: dafo = SAB82532_DAFO_CHL6; break;691 case CS7: dafo = SAB82532_DAFO_CHL7; break;692 case CS8: dafo = SAB82532_DAFO_CHL8; break;693 /* Never happens, but GCC is too dumb to figure it out */694 default: dafo = SAB82532_DAFO_CHL5; break;695 }696 697 if (cflag & CSTOPB)698 dafo |= SAB82532_DAFO_STOP;699 700 if (cflag & PARENB)701 dafo |= SAB82532_DAFO_PARE;702 703 if (cflag & PARODD) {704 dafo |= SAB82532_DAFO_PAR_ODD;705 } else {706 dafo |= SAB82532_DAFO_PAR_EVEN;707 }708 up->cached_dafo = dafo;709 710 calc_ebrg(baud, &n, &m);711 712 up->cached_ebrg = n | (m << 6);713 714 up->tec_timeout = (10 * 1000000) / baud;715 up->cec_timeout = up->tec_timeout >> 2;716 717 /* CTS flow control flags */718 /* We encode read_status_mask and ignore_status_mask like so:719 *720 * ---------------------721 * | ... | ISR1 | ISR0 |722 * ---------------------723 * .. 15 8 7 0724 */725 726 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |727 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |728 SAB82532_ISR0_CDSC);729 up->port.read_status_mask |= (SAB82532_ISR1_CSC |730 SAB82532_ISR1_ALLS |731 SAB82532_ISR1_XPR) << 8;732 if (iflag & INPCK)733 up->port.read_status_mask |= (SAB82532_ISR0_PERR |734 SAB82532_ISR0_FERR);735 if (iflag & (IGNBRK | BRKINT | PARMRK))736 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);737 738 /*739 * Characteres to ignore740 */741 up->port.ignore_status_mask = 0;742 if (iflag & IGNPAR)743 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |744 SAB82532_ISR0_FERR);745 if (iflag & IGNBRK) {746 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);747 /*748 * If we're ignoring parity and break indicators,749 * ignore overruns too (for real raw support).750 */751 if (iflag & IGNPAR)752 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;753 }754 755 /*756 * ignore all characters if CREAD is not set757 */758 if ((cflag & CREAD) == 0)759 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |760 SAB82532_ISR0_TCD);761 762 uart_update_timeout(&up->port, cflag,763 (up->port.uartclk / (16 * quot)));764 765 /* Now schedule a register update when the chip's766 * transmitter is idle.767 */768 up->cached_mode |= SAB82532_MODE_RAC;769 set_bit(SAB82532_REGS_PENDING, &up->irqflags);770 if (test_bit(SAB82532_XPR, &up->irqflags))771 sunsab_tx_idle(up);772}773 774/* port->lock is not held. */775static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,776 const struct ktermios *old)777{778 struct uart_sunsab_port *up =779 container_of(port, struct uart_sunsab_port, port);780 unsigned long flags;781 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);782 unsigned int quot = uart_get_divisor(port, baud);783 784 uart_port_lock_irqsave(&up->port, &flags);785 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);786 uart_port_unlock_irqrestore(&up->port, flags);787}788 789static const char *sunsab_type(struct uart_port *port)790{791 struct uart_sunsab_port *up = (void *)port;792 static char buf[36];793 794 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);795 return buf;796}797 798static void sunsab_release_port(struct uart_port *port)799{800}801 802static int sunsab_request_port(struct uart_port *port)803{804 return 0;805}806 807static void sunsab_config_port(struct uart_port *port, int flags)808{809}810 811static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)812{813 return -EINVAL;814}815 816static const struct uart_ops sunsab_pops = {817 .tx_empty = sunsab_tx_empty,818 .set_mctrl = sunsab_set_mctrl,819 .get_mctrl = sunsab_get_mctrl,820 .stop_tx = sunsab_stop_tx,821 .start_tx = sunsab_start_tx,822 .send_xchar = sunsab_send_xchar,823 .stop_rx = sunsab_stop_rx,824 .break_ctl = sunsab_break_ctl,825 .startup = sunsab_startup,826 .shutdown = sunsab_shutdown,827 .set_termios = sunsab_set_termios,828 .type = sunsab_type,829 .release_port = sunsab_release_port,830 .request_port = sunsab_request_port,831 .config_port = sunsab_config_port,832 .verify_port = sunsab_verify_port,833};834 835static struct uart_driver sunsab_reg = {836 .owner = THIS_MODULE,837 .driver_name = "sunsab",838 .dev_name = "ttyS",839 .major = TTY_MAJOR,840};841 842static struct uart_sunsab_port *sunsab_ports;843 844#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE845 846static void sunsab_console_putchar(struct uart_port *port, unsigned char c)847{848 struct uart_sunsab_port *up =849 container_of(port, struct uart_sunsab_port, port);850 851 sunsab_tec_wait(up);852 writeb(c, &up->regs->w.tic);853}854 855static void sunsab_console_write(struct console *con, const char *s, unsigned n)856{857 struct uart_sunsab_port *up = &sunsab_ports[con->index];858 unsigned long flags;859 int locked = 1;860 861 if (up->port.sysrq || oops_in_progress)862 locked = uart_port_trylock_irqsave(&up->port, &flags);863 else864 uart_port_lock_irqsave(&up->port, &flags);865 866 uart_console_write(&up->port, s, n, sunsab_console_putchar);867 sunsab_tec_wait(up);868 869 if (locked)870 uart_port_unlock_irqrestore(&up->port, flags);871}872 873static int sunsab_console_setup(struct console *con, char *options)874{875 struct uart_sunsab_port *up = &sunsab_ports[con->index];876 unsigned long flags;877 unsigned int baud, quot;878 879 /*880 * The console framework calls us for each and every port881 * registered. Defer the console setup until the requested882 * port has been properly discovered. A bit of a hack,883 * though...884 */885 if (up->port.type != PORT_SUNSAB)886 return -EINVAL;887 888 printk("Console: ttyS%d (SAB82532)\n",889 (sunsab_reg.minor - 64) + con->index);890 891 sunserial_console_termios(con, up->port.dev->of_node);892 893 switch (con->cflag & CBAUD) {894 case B150: baud = 150; break;895 case B300: baud = 300; break;896 case B600: baud = 600; break;897 case B1200: baud = 1200; break;898 case B2400: baud = 2400; break;899 case B4800: baud = 4800; break;900 default: case B9600: baud = 9600; break;901 case B19200: baud = 19200; break;902 case B38400: baud = 38400; break;903 case B57600: baud = 57600; break;904 case B115200: baud = 115200; break;905 case B230400: baud = 230400; break;906 case B460800: baud = 460800; break;907 }908 909 /*910 * Temporary fix.911 */912 spin_lock_init(&up->port.lock);913 914 /*915 * Initialize the hardware916 */917 sunsab_startup(&up->port);918 919 uart_port_lock_irqsave(&up->port, &flags);920 921 /*922 * Finally, enable interrupts923 */924 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |925 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;926 writeb(up->interrupt_mask0, &up->regs->w.imr0);927 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |928 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |929 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |930 SAB82532_IMR1_XPR;931 writeb(up->interrupt_mask1, &up->regs->w.imr1);932 933 quot = uart_get_divisor(&up->port, baud);934 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);935 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);936 937 uart_port_unlock_irqrestore(&up->port, flags);938 939 return 0;940}941 942static struct console sunsab_console = {943 .name = "ttyS",944 .write = sunsab_console_write,945 .device = uart_console_device,946 .setup = sunsab_console_setup,947 .flags = CON_PRINTBUFFER,948 .index = -1,949 .data = &sunsab_reg,950};951 952static inline struct console *SUNSAB_CONSOLE(void)953{954 return &sunsab_console;955}956#else957#define SUNSAB_CONSOLE() (NULL)958#define sunsab_console_init() do { } while (0)959#endif960 961static int sunsab_init_one(struct uart_sunsab_port *up,962 struct platform_device *op,963 unsigned long offset,964 int line)965{966 up->port.line = line;967 up->port.dev = &op->dev;968 969 up->port.mapbase = op->resource[0].start + offset;970 up->port.membase = of_ioremap(&op->resource[0], offset,971 sizeof(union sab82532_async_regs),972 "sab");973 if (!up->port.membase)974 return -ENOMEM;975 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;976 977 up->port.irq = op->archdata.irqs[0];978 979 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;980 up->port.iotype = UPIO_MEM;981 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);982 983 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);984 985 up->port.ops = &sunsab_pops;986 up->port.type = PORT_SUNSAB;987 up->port.uartclk = SAB_BASE_BAUD;988 989 up->type = readb(&up->regs->r.vstr) & 0x0f;990 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);991 writeb(0xff, &up->regs->w.pim);992 if ((up->port.line & 0x1) == 0) {993 up->pvr_dsr_bit = (1 << 0);994 up->pvr_dtr_bit = (1 << 1);995 up->gis_shift = 2;996 } else {997 up->pvr_dsr_bit = (1 << 3);998 up->pvr_dtr_bit = (1 << 2);999 up->gis_shift = 0;1000 }1001 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);1002 writeb(up->cached_pvr, &up->regs->w.pvr);1003 up->cached_mode = readb(&up->regs->rw.mode);1004 up->cached_mode |= SAB82532_MODE_FRTS;1005 writeb(up->cached_mode, &up->regs->rw.mode);1006 up->cached_mode |= SAB82532_MODE_RTS;1007 writeb(up->cached_mode, &up->regs->rw.mode);1008 1009 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;1010 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;1011 1012 return 0;1013}1014 1015static int sab_probe(struct platform_device *op)1016{1017 static int inst;1018 struct uart_sunsab_port *up;1019 int err;1020 1021 up = &sunsab_ports[inst * 2];1022 1023 err = sunsab_init_one(&up[0], op,1024 0,1025 (inst * 2) + 0);1026 if (err)1027 goto out;1028 1029 err = sunsab_init_one(&up[1], op,1030 sizeof(union sab82532_async_regs),1031 (inst * 2) + 1);1032 if (err)1033 goto out1;1034 1035 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,1036 &sunsab_reg, up[0].port.line,1037 false);1038 1039 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,1040 &sunsab_reg, up[1].port.line,1041 false);1042 1043 err = uart_add_one_port(&sunsab_reg, &up[0].port);1044 if (err)1045 goto out2;1046 1047 err = uart_add_one_port(&sunsab_reg, &up[1].port);1048 if (err)1049 goto out3;1050 1051 platform_set_drvdata(op, &up[0]);1052 1053 inst++;1054 1055 return 0;1056 1057out3:1058 uart_remove_one_port(&sunsab_reg, &up[0].port);1059out2:1060 of_iounmap(&op->resource[0],1061 up[1].port.membase,1062 sizeof(union sab82532_async_regs));1063out1:1064 of_iounmap(&op->resource[0],1065 up[0].port.membase,1066 sizeof(union sab82532_async_regs));1067out:1068 return err;1069}1070 1071static void sab_remove(struct platform_device *op)1072{1073 struct uart_sunsab_port *up = platform_get_drvdata(op);1074 1075 uart_remove_one_port(&sunsab_reg, &up[1].port);1076 uart_remove_one_port(&sunsab_reg, &up[0].port);1077 of_iounmap(&op->resource[0],1078 up[1].port.membase,1079 sizeof(union sab82532_async_regs));1080 of_iounmap(&op->resource[0],1081 up[0].port.membase,1082 sizeof(union sab82532_async_regs));1083}1084 1085static const struct of_device_id sab_match[] = {1086 {1087 .name = "se",1088 },1089 {1090 .name = "serial",1091 .compatible = "sab82532",1092 },1093 {},1094};1095MODULE_DEVICE_TABLE(of, sab_match);1096 1097static struct platform_driver sab_driver = {1098 .driver = {1099 .name = "sab",1100 .of_match_table = sab_match,1101 },1102 .probe = sab_probe,1103 .remove_new = sab_remove,1104};1105 1106static int __init sunsab_init(void)1107{1108 struct device_node *dp;1109 int err;1110 int num_channels = 0;1111 1112 for_each_node_by_name(dp, "se")1113 num_channels += 2;1114 for_each_node_by_name(dp, "serial") {1115 if (of_device_is_compatible(dp, "sab82532"))1116 num_channels += 2;1117 }1118 1119 if (num_channels) {1120 sunsab_ports = kcalloc(num_channels,1121 sizeof(struct uart_sunsab_port),1122 GFP_KERNEL);1123 if (!sunsab_ports)1124 return -ENOMEM;1125 1126 err = sunserial_register_minors(&sunsab_reg, num_channels);1127 if (err) {1128 kfree(sunsab_ports);1129 sunsab_ports = NULL;1130 1131 return err;1132 }1133 }1134 1135 err = platform_driver_register(&sab_driver);1136 if (err) {1137 kfree(sunsab_ports);1138 sunsab_ports = NULL;1139 }1140 1141 return err;1142}1143 1144static void __exit sunsab_exit(void)1145{1146 platform_driver_unregister(&sab_driver);1147 if (sunsab_reg.nr) {1148 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);1149 }1150 1151 kfree(sunsab_ports);1152 sunsab_ports = NULL;1153}1154 1155module_init(sunsab_init);1156module_exit(sunsab_exit);1157 1158MODULE_AUTHOR("Eddie C. Dost and David S. Miller");1159MODULE_DESCRIPTION("Sun SAB82532 serial port driver");1160MODULE_LICENSE("GPL");1161