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1/* SPDX-License-Identifier: GPL-2.0 */2/* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC3 *4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)5 */6 7#ifndef _SUNSAB_H8#define _SUNSAB_H9 10struct sab82532_async_rd_regs {11 u8 rfifo[0x20]; /* Receive FIFO */12 u8 star; /* Status Register */13 u8 __pad1;14 u8 mode; /* Mode Register */15 u8 timr; /* Timer Register */16 u8 xon; /* XON Character */17 u8 xoff; /* XOFF Character */18 u8 tcr; /* Termination Character Register */19 u8 dafo; /* Data Format */20 u8 rfc; /* RFIFO Control Register */21 u8 __pad2;22 u8 rbcl; /* Receive Byte Count Low */23 u8 rbch; /* Receive Byte Count High */24 u8 ccr0; /* Channel Configuration Register 0 */25 u8 ccr1; /* Channel Configuration Register 1 */26 u8 ccr2; /* Channel Configuration Register 2 */27 u8 ccr3; /* Channel Configuration Register 3 */28 u8 __pad3[4];29 u8 vstr; /* Version Status Register */30 u8 __pad4[3];31 u8 gis; /* Global Interrupt Status */32 u8 ipc; /* Interrupt Port Configuration */33 u8 isr0; /* Interrupt Status 0 */34 u8 isr1; /* Interrupt Status 1 */35 u8 pvr; /* Port Value Register */36 u8 pis; /* Port Interrupt Status */37 u8 pcr; /* Port Configuration Register */38 u8 ccr4; /* Channel Configuration Register 4 */39};40 41struct sab82532_async_wr_regs {42 u8 xfifo[0x20]; /* Transmit FIFO */43 u8 cmdr; /* Command Register */44 u8 __pad1;45 u8 mode;46 u8 timr;47 u8 xon;48 u8 xoff;49 u8 tcr;50 u8 dafo;51 u8 rfc;52 u8 __pad2;53 u8 xbcl; /* Transmit Byte Count Low */54 u8 xbch; /* Transmit Byte Count High */55 u8 ccr0;56 u8 ccr1;57 u8 ccr2;58 u8 ccr3;59 u8 tsax; /* Time-Slot Assignment Reg. Transmit */60 u8 tsar; /* Time-Slot Assignment Reg. Receive */61 u8 xccr; /* Transmit Channel Capacity Register */62 u8 rccr; /* Receive Channel Capacity Register */63 u8 bgr; /* Baud Rate Generator Register */64 u8 tic; /* Transmit Immediate Character */65 u8 mxn; /* Mask XON Character */66 u8 mxf; /* Mask XOFF Character */67 u8 iva; /* Interrupt Vector Address */68 u8 ipc;69 u8 imr0; /* Interrupt Mask Register 0 */70 u8 imr1; /* Interrupt Mask Register 1 */71 u8 pvr;72 u8 pim; /* Port Interrupt Mask */73 u8 pcr;74 u8 ccr4;75};76 77struct sab82532_async_rw_regs { /* Read/Write registers */78 u8 __pad1[0x20];79 u8 __pad2;80 u8 __pad3;81 u8 mode;82 u8 timr;83 u8 xon;84 u8 xoff;85 u8 tcr;86 u8 dafo;87 u8 rfc;88 u8 __pad4;89 u8 __pad5;90 u8 __pad6;91 u8 ccr0;92 u8 ccr1;93 u8 ccr2;94 u8 ccr3;95 u8 __pad7;96 u8 __pad8;97 u8 __pad9;98 u8 __pad10;99 u8 __pad11;100 u8 __pad12;101 u8 __pad13;102 u8 __pad14;103 u8 __pad15;104 u8 ipc;105 u8 __pad16;106 u8 __pad17;107 u8 pvr;108 u8 __pad18;109 u8 pcr;110 u8 ccr4;111};112 113union sab82532_async_regs {114 __volatile__ struct sab82532_async_rd_regs r;115 __volatile__ struct sab82532_async_wr_regs w;116 __volatile__ struct sab82532_async_rw_regs rw;117};118 119union sab82532_irq_status {120 unsigned short stat;121 struct {122 unsigned char isr0;123 unsigned char isr1;124 } sreg;125};126 127/* irqflags bits */128#define SAB82532_ALLS 0x00000001129#define SAB82532_XPR 0x00000002130#define SAB82532_REGS_PENDING 0x00000004131 132/* RFIFO Status Byte */133#define SAB82532_RSTAT_PE 0x80134#define SAB82532_RSTAT_FE 0x40135#define SAB82532_RSTAT_PARITY 0x01136 137/* Status Register (STAR) */138#define SAB82532_STAR_XDOV 0x80139#define SAB82532_STAR_XFW 0x40140#define SAB82532_STAR_RFNE 0x20141#define SAB82532_STAR_FCS 0x10142#define SAB82532_STAR_TEC 0x08143#define SAB82532_STAR_CEC 0x04144#define SAB82532_STAR_CTS 0x02145 146/* Command Register (CMDR) */147#define SAB82532_CMDR_RMC 0x80148#define SAB82532_CMDR_RRES 0x40149#define SAB82532_CMDR_RFRD 0x20150#define SAB82532_CMDR_STI 0x10151#define SAB82532_CMDR_XF 0x08152#define SAB82532_CMDR_XRES 0x01153 154/* Mode Register (MODE) */155#define SAB82532_MODE_FRTS 0x40156#define SAB82532_MODE_FCTS 0x20157#define SAB82532_MODE_FLON 0x10158#define SAB82532_MODE_RAC 0x08159#define SAB82532_MODE_RTS 0x04160#define SAB82532_MODE_TRS 0x02161#define SAB82532_MODE_TLP 0x01162 163/* Timer Register (TIMR) */164#define SAB82532_TIMR_CNT_MASK 0xe0165#define SAB82532_TIMR_VALUE_MASK 0x1f166 167/* Data Format (DAFO) */168#define SAB82532_DAFO_XBRK 0x40169#define SAB82532_DAFO_STOP 0x20170#define SAB82532_DAFO_PAR_SPACE 0x00171#define SAB82532_DAFO_PAR_ODD 0x08172#define SAB82532_DAFO_PAR_EVEN 0x10173#define SAB82532_DAFO_PAR_MARK 0x18174#define SAB82532_DAFO_PARE 0x04175#define SAB82532_DAFO_CHL8 0x00176#define SAB82532_DAFO_CHL7 0x01177#define SAB82532_DAFO_CHL6 0x02178#define SAB82532_DAFO_CHL5 0x03179 180/* RFIFO Control Register (RFC) */181#define SAB82532_RFC_DPS 0x40182#define SAB82532_RFC_DXS 0x20183#define SAB82532_RFC_RFDF 0x10184#define SAB82532_RFC_RFTH_1 0x00185#define SAB82532_RFC_RFTH_4 0x04186#define SAB82532_RFC_RFTH_16 0x08187#define SAB82532_RFC_RFTH_32 0x0c188#define SAB82532_RFC_TCDE 0x01189 190/* Received Byte Count High (RBCH) */191#define SAB82532_RBCH_DMA 0x80192#define SAB82532_RBCH_CAS 0x20193 194/* Transmit Byte Count High (XBCH) */195#define SAB82532_XBCH_DMA 0x80196#define SAB82532_XBCH_CAS 0x20197#define SAB82532_XBCH_XC 0x10198 199/* Channel Configuration Register 0 (CCR0) */200#define SAB82532_CCR0_PU 0x80201#define SAB82532_CCR0_MCE 0x40202#define SAB82532_CCR0_SC_NRZ 0x00203#define SAB82532_CCR0_SC_NRZI 0x08204#define SAB82532_CCR0_SC_FM0 0x10205#define SAB82532_CCR0_SC_FM1 0x14206#define SAB82532_CCR0_SC_MANCH 0x18207#define SAB82532_CCR0_SM_HDLC 0x00208#define SAB82532_CCR0_SM_SDLC_LOOP 0x01209#define SAB82532_CCR0_SM_BISYNC 0x02210#define SAB82532_CCR0_SM_ASYNC 0x03211 212/* Channel Configuration Register 1 (CCR1) */213#define SAB82532_CCR1_ODS 0x10214#define SAB82532_CCR1_BCR 0x08215#define SAB82532_CCR1_CM_MASK 0x07216 217/* Channel Configuration Register 2 (CCR2) */218#define SAB82532_CCR2_SOC1 0x80219#define SAB82532_CCR2_SOC0 0x40220#define SAB82532_CCR2_BR9 0x80221#define SAB82532_CCR2_BR8 0x40222#define SAB82532_CCR2_BDF 0x20223#define SAB82532_CCR2_SSEL 0x10224#define SAB82532_CCR2_XCS0 0x20225#define SAB82532_CCR2_RCS0 0x10226#define SAB82532_CCR2_TOE 0x08227#define SAB82532_CCR2_RWX 0x04228#define SAB82532_CCR2_DIV 0x01229 230/* Channel Configuration Register 3 (CCR3) */231#define SAB82532_CCR3_PSD 0x01232 233/* Time Slot Assignment Register Transmit (TSAX) */234#define SAB82532_TSAX_TSNX_MASK 0xfc235#define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */236#define SAB82532_TSAX_XCS1 0x01237 238/* Time Slot Assignment Register Receive (TSAR) */239#define SAB82532_TSAR_TSNR_MASK 0xfc240#define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */241#define SAB82532_TSAR_RCS1 0x01242 243/* Version Status Register (VSTR) */244#define SAB82532_VSTR_CD 0x80245#define SAB82532_VSTR_DPLA 0x40246#define SAB82532_VSTR_VN_MASK 0x0f247#define SAB82532_VSTR_VN_1 0x00248#define SAB82532_VSTR_VN_2 0x01249#define SAB82532_VSTR_VN_3_2 0x02250 251/* Global Interrupt Status Register (GIS) */252#define SAB82532_GIS_PI 0x80253#define SAB82532_GIS_ISA1 0x08254#define SAB82532_GIS_ISA0 0x04255#define SAB82532_GIS_ISB1 0x02256#define SAB82532_GIS_ISB0 0x01257 258/* Interrupt Vector Address (IVA) */259#define SAB82532_IVA_MASK 0xf1260 261/* Interrupt Port Configuration (IPC) */262#define SAB82532_IPC_VIS 0x80263#define SAB82532_IPC_SLA1 0x10264#define SAB82532_IPC_SLA0 0x08265#define SAB82532_IPC_CASM 0x04266#define SAB82532_IPC_IC_OPEN_DRAIN 0x00267#define SAB82532_IPC_IC_ACT_LOW 0x01268#define SAB82532_IPC_IC_ACT_HIGH 0x03269 270/* Interrupt Status Register 0 (ISR0) */271#define SAB82532_ISR0_TCD 0x80272#define SAB82532_ISR0_TIME 0x40273#define SAB82532_ISR0_PERR 0x20274#define SAB82532_ISR0_FERR 0x10275#define SAB82532_ISR0_PLLA 0x08276#define SAB82532_ISR0_CDSC 0x04277#define SAB82532_ISR0_RFO 0x02278#define SAB82532_ISR0_RPF 0x01279 280/* Interrupt Status Register 1 (ISR1) */281#define SAB82532_ISR1_BRK 0x80282#define SAB82532_ISR1_BRKT 0x40283#define SAB82532_ISR1_ALLS 0x20284#define SAB82532_ISR1_XOFF 0x10285#define SAB82532_ISR1_TIN 0x08286#define SAB82532_ISR1_CSC 0x04287#define SAB82532_ISR1_XON 0x02288#define SAB82532_ISR1_XPR 0x01289 290/* Interrupt Mask Register 0 (IMR0) */291#define SAB82532_IMR0_TCD 0x80292#define SAB82532_IMR0_TIME 0x40293#define SAB82532_IMR0_PERR 0x20294#define SAB82532_IMR0_FERR 0x10295#define SAB82532_IMR0_PLLA 0x08296#define SAB82532_IMR0_CDSC 0x04297#define SAB82532_IMR0_RFO 0x02298#define SAB82532_IMR0_RPF 0x01299 300/* Interrupt Mask Register 1 (IMR1) */301#define SAB82532_IMR1_BRK 0x80302#define SAB82532_IMR1_BRKT 0x40303#define SAB82532_IMR1_ALLS 0x20304#define SAB82532_IMR1_XOFF 0x10305#define SAB82532_IMR1_TIN 0x08306#define SAB82532_IMR1_CSC 0x04307#define SAB82532_IMR1_XON 0x02308#define SAB82532_IMR1_XPR 0x01309 310/* Port Interrupt Status Register (PIS) */311#define SAB82532_PIS_SYNC_B 0x08312#define SAB82532_PIS_DTR_B 0x04313#define SAB82532_PIS_DTR_A 0x02314#define SAB82532_PIS_SYNC_A 0x01315 316/* Channel Configuration Register 4 (CCR4) */317#define SAB82532_CCR4_MCK4 0x80318#define SAB82532_CCR4_EBRG 0x40319#define SAB82532_CCR4_TST1 0x20320#define SAB82532_CCR4_ICD 0x10321 322 323#endif /* !(_SUNSAB_H) */324