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1// SPDX-License-Identifier: GPL-2.02/* sunzilog.c: Zilog serial driver for Sparc systems.3 *4 * Driver for Zilog serial chips found on Sun workstations and5 * servers. This driver could actually be made more generic.6 *7 * This is based on the old drivers/sbus/char/zs.c code. A lot8 * of code has been simply moved over directly from there but9 * much has been rewritten. Credits therefore go out to Eddie10 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their11 * work there.12 *13 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)14 */15 16#include <linux/module.h>17#include <linux/kernel.h>18#include <linux/errno.h>19#include <linux/delay.h>20#include <linux/tty.h>21#include <linux/tty_flip.h>22#include <linux/major.h>23#include <linux/string.h>24#include <linux/ptrace.h>25#include <linux/ioport.h>26#include <linux/slab.h>27#include <linux/circ_buf.h>28#include <linux/serial.h>29#include <linux/sysrq.h>30#include <linux/console.h>31#include <linux/spinlock.h>32#ifdef CONFIG_SERIO33#include <linux/serio.h>34#endif35#include <linux/init.h>36#include <linux/of.h>37#include <linux/platform_device.h>38 39#include <linux/io.h>40#include <asm/irq.h>41#include <asm/setup.h>42 43#include <linux/serial_core.h>44#include <linux/sunserialcore.h>45 46#include "sunzilog.h"47 48/* On 32-bit sparcs we need to delay after register accesses49 * to accommodate sun4 systems, but we do not need to flush writes.50 * On 64-bit sparc we only need to flush single writes to ensure51 * completion.52 */53#ifndef CONFIG_SPARC6454#define ZSDELAY() udelay(5)55#define ZSDELAY_LONG() udelay(20)56#define ZS_WSYNC(channel) do { } while (0)57#else58#define ZSDELAY()59#define ZSDELAY_LONG()60#define ZS_WSYNC(__channel) \61 readb(&((__channel)->control))62#endif63 64#define ZS_CLOCK 4915200 /* Zilog input clock rate. */65#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */66 67/*68 * We wrap our port structure around the generic uart_port.69 */70struct uart_sunzilog_port {71 struct uart_port port;72 73 /* IRQ servicing chain. */74 struct uart_sunzilog_port *next;75 76 /* Current values of Zilog write registers. */77 unsigned char curregs[NUM_ZSREGS];78 79 unsigned int flags;80#define SUNZILOG_FLAG_CONS_KEYB 0x0000000181#define SUNZILOG_FLAG_CONS_MOUSE 0x0000000282#define SUNZILOG_FLAG_IS_CONS 0x0000000483#define SUNZILOG_FLAG_IS_KGDB 0x0000000884#define SUNZILOG_FLAG_MODEM_STATUS 0x0000001085#define SUNZILOG_FLAG_IS_CHANNEL_A 0x0000002086#define SUNZILOG_FLAG_REGS_HELD 0x0000004087#define SUNZILOG_FLAG_TX_STOPPED 0x0000008088#define SUNZILOG_FLAG_TX_ACTIVE 0x0000010089#define SUNZILOG_FLAG_ESCC 0x0000020090#define SUNZILOG_FLAG_ISR_HANDLER 0x0000040091 92 unsigned int cflag;93 94 unsigned char parity_mask;95 unsigned char prev_status;96 97#ifdef CONFIG_SERIO98 struct serio serio;99 int serio_open;100#endif101};102 103static void sunzilog_putchar(struct uart_port *port, unsigned char ch);104 105#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))106#define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))107 108#define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)109#define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)110#define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)111#define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)112#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)113#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)114#define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)115#define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)116#define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)117 118/* Reading and writing Zilog8530 registers. The delays are to make this119 * driver work on the Sun4 which needs a settling delay after each chip120 * register access, other machines handle this in hardware via auxiliary121 * flip-flops which implement the settle time we do in software.122 *123 * The port lock must be held and local IRQs must be disabled124 * when {read,write}_zsreg is invoked.125 */126static unsigned char read_zsreg(struct zilog_channel __iomem *channel,127 unsigned char reg)128{129 unsigned char retval;130 131 writeb(reg, &channel->control);132 ZSDELAY();133 retval = readb(&channel->control);134 ZSDELAY();135 136 return retval;137}138 139static void write_zsreg(struct zilog_channel __iomem *channel,140 unsigned char reg, unsigned char value)141{142 writeb(reg, &channel->control);143 ZSDELAY();144 writeb(value, &channel->control);145 ZSDELAY();146}147 148static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)149{150 int i;151 152 for (i = 0; i < 32; i++) {153 unsigned char regval;154 155 regval = readb(&channel->control);156 ZSDELAY();157 if (regval & Rx_CH_AV)158 break;159 160 regval = read_zsreg(channel, R1);161 readb(&channel->data);162 ZSDELAY();163 164 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {165 writeb(ERR_RES, &channel->control);166 ZSDELAY();167 ZS_WSYNC(channel);168 }169 }170}171 172/* This function must only be called when the TX is not busy. The UART173 * port lock must be held and local interrupts disabled.174 */175static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)176{177 int i;178 int escc;179 unsigned char r15;180 181 /* Let pending transmits finish. */182 for (i = 0; i < 1000; i++) {183 unsigned char stat = read_zsreg(channel, R1);184 if (stat & ALL_SNT)185 break;186 udelay(100);187 }188 189 writeb(ERR_RES, &channel->control);190 ZSDELAY();191 ZS_WSYNC(channel);192 193 sunzilog_clear_fifo(channel);194 195 /* Disable all interrupts. */196 write_zsreg(channel, R1,197 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));198 199 /* Set parity, sync config, stop bits, and clock divisor. */200 write_zsreg(channel, R4, regs[R4]);201 202 /* Set misc. TX/RX control bits. */203 write_zsreg(channel, R10, regs[R10]);204 205 /* Set TX/RX controls sans the enable bits. */206 write_zsreg(channel, R3, regs[R3] & ~RxENAB);207 write_zsreg(channel, R5, regs[R5] & ~TxENAB);208 209 /* Synchronous mode config. */210 write_zsreg(channel, R6, regs[R6]);211 write_zsreg(channel, R7, regs[R7]);212 213 /* Don't mess with the interrupt vector (R2, unused by us) and214 * master interrupt control (R9). We make sure this is setup215 * properly at probe time then never touch it again.216 */217 218 /* Disable baud generator. */219 write_zsreg(channel, R14, regs[R14] & ~BRENAB);220 221 /* Clock mode control. */222 write_zsreg(channel, R11, regs[R11]);223 224 /* Lower and upper byte of baud rate generator divisor. */225 write_zsreg(channel, R12, regs[R12]);226 write_zsreg(channel, R13, regs[R13]);227 228 /* Now rewrite R14, with BRENAB (if set). */229 write_zsreg(channel, R14, regs[R14]);230 231 /* External status interrupt control. */232 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);233 234 /* ESCC Extension Register */235 r15 = read_zsreg(channel, R15);236 if (r15 & 0x01) {237 write_zsreg(channel, R7, regs[R7p]);238 239 /* External status interrupt and FIFO control. */240 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);241 escc = 1;242 } else {243 /* Clear FIFO bit case it is an issue */244 regs[R15] &= ~FIFOEN;245 escc = 0;246 }247 248 /* Reset external status interrupts. */249 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */250 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */251 252 /* Rewrite R3/R5, this time without enables masked. */253 write_zsreg(channel, R3, regs[R3]);254 write_zsreg(channel, R5, regs[R5]);255 256 /* Rewrite R1, this time without IRQ enabled masked. */257 write_zsreg(channel, R1, regs[R1]);258 259 return escc;260}261 262/* Reprogram the Zilog channel HW registers with the copies found in the263 * software state struct. If the transmitter is busy, we defer this update264 * until the next TX complete interrupt. Else, we do it right now.265 *266 * The UART port lock must be held and local interrupts disabled.267 */268static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,269 struct zilog_channel __iomem *channel)270{271 if (!ZS_REGS_HELD(up)) {272 if (ZS_TX_ACTIVE(up)) {273 up->flags |= SUNZILOG_FLAG_REGS_HELD;274 } else {275 __load_zsregs(channel, up->curregs);276 }277 }278}279 280static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)281{282 unsigned int cur_cflag = up->cflag;283 int brg, new_baud;284 285 up->cflag &= ~CBAUD;286 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);287 288 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);289 up->curregs[R12] = (brg & 0xff);290 up->curregs[R13] = (brg >> 8) & 0xff;291 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));292}293 294static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,295 unsigned char ch, int is_break)296{297 if (ZS_IS_KEYB(up)) {298 /* Stop-A is handled by drivers/char/keyboard.c now. */299#ifdef CONFIG_SERIO300 if (up->serio_open)301 serio_interrupt(&up->serio, ch, 0);302#endif303 } else if (ZS_IS_MOUSE(up)) {304 int ret = suncore_mouse_baud_detection(ch, is_break);305 306 switch (ret) {307 case 2:308 sunzilog_change_mouse_baud(up);309 fallthrough;310 case 1:311 break;312 313 case 0:314#ifdef CONFIG_SERIO315 if (up->serio_open)316 serio_interrupt(&up->serio, ch, 0);317#endif318 break;319 }320 }321}322 323static struct tty_port *324sunzilog_receive_chars(struct uart_sunzilog_port *up,325 struct zilog_channel __iomem *channel)326{327 struct tty_port *port = NULL;328 unsigned char ch, r1, flag;329 330 if (up->port.state != NULL) /* Unopened serial console */331 port = &up->port.state->port;332 333 for (;;) {334 335 r1 = read_zsreg(channel, R1);336 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {337 writeb(ERR_RES, &channel->control);338 ZSDELAY();339 ZS_WSYNC(channel);340 }341 342 ch = readb(&channel->control);343 ZSDELAY();344 345 /* This funny hack depends upon BRK_ABRT not interfering346 * with the other bits we care about in R1.347 */348 if (ch & BRK_ABRT)349 r1 |= BRK_ABRT;350 351 if (!(ch & Rx_CH_AV))352 break;353 354 ch = readb(&channel->data);355 ZSDELAY();356 357 ch &= up->parity_mask;358 359 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {360 sunzilog_kbdms_receive_chars(up, ch, 0);361 continue;362 }363 364 /* A real serial line, record the character and status. */365 flag = TTY_NORMAL;366 up->port.icount.rx++;367 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {368 if (r1 & BRK_ABRT) {369 r1 &= ~(PAR_ERR | CRC_ERR);370 up->port.icount.brk++;371 if (uart_handle_break(&up->port))372 continue;373 }374 else if (r1 & PAR_ERR)375 up->port.icount.parity++;376 else if (r1 & CRC_ERR)377 up->port.icount.frame++;378 if (r1 & Rx_OVR)379 up->port.icount.overrun++;380 r1 &= up->port.read_status_mask;381 if (r1 & BRK_ABRT)382 flag = TTY_BREAK;383 else if (r1 & PAR_ERR)384 flag = TTY_PARITY;385 else if (r1 & CRC_ERR)386 flag = TTY_FRAME;387 }388 if (uart_handle_sysrq_char(&up->port, ch) || !port)389 continue;390 391 if (up->port.ignore_status_mask == 0xff ||392 (r1 & up->port.ignore_status_mask) == 0) {393 tty_insert_flip_char(port, ch, flag);394 }395 if (r1 & Rx_OVR)396 tty_insert_flip_char(port, 0, TTY_OVERRUN);397 }398 399 return port;400}401 402static void sunzilog_status_handle(struct uart_sunzilog_port *up,403 struct zilog_channel __iomem *channel)404{405 unsigned char status;406 407 status = readb(&channel->control);408 ZSDELAY();409 410 writeb(RES_EXT_INT, &channel->control);411 ZSDELAY();412 ZS_WSYNC(channel);413 414 if (status & BRK_ABRT) {415 if (ZS_IS_MOUSE(up))416 sunzilog_kbdms_receive_chars(up, 0, 1);417 if (ZS_IS_CONS(up)) {418 /* Wait for BREAK to deassert to avoid potentially419 * confusing the PROM.420 */421 while (1) {422 status = readb(&channel->control);423 ZSDELAY();424 if (!(status & BRK_ABRT))425 break;426 }427 sun_do_break();428 return;429 }430 }431 432 if (ZS_WANTS_MODEM_STATUS(up)) {433 if (status & SYNC)434 up->port.icount.dsr++;435 436 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.437 * But it does not tell us which bit has changed, we have to keep438 * track of this ourselves.439 */440 if ((status ^ up->prev_status) ^ DCD)441 uart_handle_dcd_change(&up->port,442 (status & DCD));443 if ((status ^ up->prev_status) ^ CTS)444 uart_handle_cts_change(&up->port,445 (status & CTS));446 447 wake_up_interruptible(&up->port.state->port.delta_msr_wait);448 }449 450 up->prev_status = status;451}452 453static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,454 struct zilog_channel __iomem *channel)455{456 struct tty_port *tport;457 unsigned char ch;458 459 if (ZS_IS_CONS(up)) {460 unsigned char status = readb(&channel->control);461 ZSDELAY();462 463 /* TX still busy? Just wait for the next TX done interrupt.464 *465 * It can occur because of how we do serial console writes. It would466 * be nice to transmit console writes just like we normally would for467 * a TTY line. (ie. buffered and TX interrupt driven). That is not468 * easy because console writes cannot sleep. One solution might be469 * to poll on enough port->xmit space becoming free. -DaveM470 */471 if (!(status & Tx_BUF_EMP))472 return;473 }474 475 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;476 477 if (ZS_REGS_HELD(up)) {478 __load_zsregs(channel, up->curregs);479 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;480 }481 482 if (ZS_TX_STOPPED(up)) {483 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;484 goto ack_tx_int;485 }486 487 if (up->port.x_char) {488 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;489 writeb(up->port.x_char, &channel->data);490 ZSDELAY();491 ZS_WSYNC(channel);492 493 up->port.icount.tx++;494 up->port.x_char = 0;495 return;496 }497 498 if (up->port.state == NULL)499 goto ack_tx_int;500 tport = &up->port.state->port;501 502 if (uart_tx_stopped(&up->port))503 goto ack_tx_int;504 505 if (!uart_fifo_get(&up->port, &ch))506 goto ack_tx_int;507 508 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;509 writeb(ch, &channel->data);510 ZSDELAY();511 ZS_WSYNC(channel);512 513 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)514 uart_write_wakeup(&up->port);515 516 return;517 518ack_tx_int:519 writeb(RES_Tx_P, &channel->control);520 ZSDELAY();521 ZS_WSYNC(channel);522}523 524static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)525{526 struct uart_sunzilog_port *up = dev_id;527 528 while (up) {529 struct zilog_channel __iomem *channel530 = ZILOG_CHANNEL_FROM_PORT(&up->port);531 struct tty_port *port;532 unsigned char r3;533 534 uart_port_lock(&up->port);535 r3 = read_zsreg(channel, R3);536 537 /* Channel A */538 port = NULL;539 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {540 writeb(RES_H_IUS, &channel->control);541 ZSDELAY();542 ZS_WSYNC(channel);543 544 if (r3 & CHARxIP)545 port = sunzilog_receive_chars(up, channel);546 if (r3 & CHAEXT)547 sunzilog_status_handle(up, channel);548 if (r3 & CHATxIP)549 sunzilog_transmit_chars(up, channel);550 }551 uart_port_unlock(&up->port);552 553 if (port)554 tty_flip_buffer_push(port);555 556 /* Channel B */557 up = up->next;558 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);559 560 uart_port_lock(&up->port);561 port = NULL;562 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {563 writeb(RES_H_IUS, &channel->control);564 ZSDELAY();565 ZS_WSYNC(channel);566 567 if (r3 & CHBRxIP)568 port = sunzilog_receive_chars(up, channel);569 if (r3 & CHBEXT)570 sunzilog_status_handle(up, channel);571 if (r3 & CHBTxIP)572 sunzilog_transmit_chars(up, channel);573 }574 uart_port_unlock(&up->port);575 576 if (port)577 tty_flip_buffer_push(port);578 579 up = up->next;580 }581 582 return IRQ_HANDLED;583}584 585/* A convenient way to quickly get R0 status. The caller must _not_ hold the586 * port lock, it is acquired here.587 */588static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)589{590 struct zilog_channel __iomem *channel;591 unsigned char status;592 593 channel = ZILOG_CHANNEL_FROM_PORT(port);594 status = readb(&channel->control);595 ZSDELAY();596 597 return status;598}599 600/* The port lock is not held. */601static unsigned int sunzilog_tx_empty(struct uart_port *port)602{603 unsigned long flags;604 unsigned char status;605 unsigned int ret;606 607 uart_port_lock_irqsave(port, &flags);608 609 status = sunzilog_read_channel_status(port);610 611 uart_port_unlock_irqrestore(port, flags);612 613 if (status & Tx_BUF_EMP)614 ret = TIOCSER_TEMT;615 else616 ret = 0;617 618 return ret;619}620 621/* The port lock is held and interrupts are disabled. */622static unsigned int sunzilog_get_mctrl(struct uart_port *port)623{624 unsigned char status;625 unsigned int ret;626 627 status = sunzilog_read_channel_status(port);628 629 ret = 0;630 if (status & DCD)631 ret |= TIOCM_CAR;632 if (status & SYNC)633 ret |= TIOCM_DSR;634 if (status & CTS)635 ret |= TIOCM_CTS;636 637 return ret;638}639 640/* The port lock is held and interrupts are disabled. */641static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)642{643 struct uart_sunzilog_port *up =644 container_of(port, struct uart_sunzilog_port, port);645 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);646 unsigned char set_bits, clear_bits;647 648 set_bits = clear_bits = 0;649 650 if (mctrl & TIOCM_RTS)651 set_bits |= RTS;652 else653 clear_bits |= RTS;654 if (mctrl & TIOCM_DTR)655 set_bits |= DTR;656 else657 clear_bits |= DTR;658 659 /* NOTE: Not subject to 'transmitter active' rule. */ 660 up->curregs[R5] |= set_bits;661 up->curregs[R5] &= ~clear_bits;662 write_zsreg(channel, R5, up->curregs[R5]);663}664 665/* The port lock is held and interrupts are disabled. */666static void sunzilog_stop_tx(struct uart_port *port)667{668 struct uart_sunzilog_port *up =669 container_of(port, struct uart_sunzilog_port, port);670 671 up->flags |= SUNZILOG_FLAG_TX_STOPPED;672}673 674/* The port lock is held and interrupts are disabled. */675static void sunzilog_start_tx(struct uart_port *port)676{677 struct uart_sunzilog_port *up =678 container_of(port, struct uart_sunzilog_port, port);679 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);680 unsigned char status;681 682 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;683 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;684 685 status = readb(&channel->control);686 ZSDELAY();687 688 /* TX busy? Just wait for the TX done interrupt. */689 if (!(status & Tx_BUF_EMP))690 return;691 692 /* Send the first character to jump-start the TX done693 * IRQ sending engine.694 */695 if (port->x_char) {696 writeb(port->x_char, &channel->data);697 ZSDELAY();698 ZS_WSYNC(channel);699 700 port->icount.tx++;701 port->x_char = 0;702 } else {703 struct tty_port *tport = &port->state->port;704 unsigned char ch;705 706 if (!uart_fifo_get(&up->port, &ch))707 return;708 writeb(ch, &channel->data);709 ZSDELAY();710 ZS_WSYNC(channel);711 712 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)713 uart_write_wakeup(&up->port);714 }715}716 717/* The port lock is held. */718static void sunzilog_stop_rx(struct uart_port *port)719{720 struct uart_sunzilog_port *up = UART_ZILOG(port);721 struct zilog_channel __iomem *channel;722 723 if (ZS_IS_CONS(up))724 return;725 726 channel = ZILOG_CHANNEL_FROM_PORT(port);727 728 /* Disable all RX interrupts. */729 up->curregs[R1] &= ~RxINT_MASK;730 sunzilog_maybe_update_regs(up, channel);731}732 733/* The port lock is held. */734static void sunzilog_enable_ms(struct uart_port *port)735{736 struct uart_sunzilog_port *up =737 container_of(port, struct uart_sunzilog_port, port);738 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);739 unsigned char new_reg;740 741 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);742 if (new_reg != up->curregs[R15]) {743 up->curregs[R15] = new_reg;744 745 /* NOTE: Not subject to 'transmitter active' rule. */ 746 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);747 }748}749 750/* The port lock is not held. */751static void sunzilog_break_ctl(struct uart_port *port, int break_state)752{753 struct uart_sunzilog_port *up =754 container_of(port, struct uart_sunzilog_port, port);755 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);756 unsigned char set_bits, clear_bits, new_reg;757 unsigned long flags;758 759 set_bits = clear_bits = 0;760 761 if (break_state)762 set_bits |= SND_BRK;763 else764 clear_bits |= SND_BRK;765 766 uart_port_lock_irqsave(port, &flags);767 768 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;769 if (new_reg != up->curregs[R5]) {770 up->curregs[R5] = new_reg;771 772 /* NOTE: Not subject to 'transmitter active' rule. */ 773 write_zsreg(channel, R5, up->curregs[R5]);774 }775 776 uart_port_unlock_irqrestore(port, flags);777}778 779static void __sunzilog_startup(struct uart_sunzilog_port *up)780{781 struct zilog_channel __iomem *channel;782 783 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);784 up->prev_status = readb(&channel->control);785 786 /* Enable receiver and transmitter. */787 up->curregs[R3] |= RxENAB;788 up->curregs[R5] |= TxENAB;789 790 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;791 sunzilog_maybe_update_regs(up, channel);792}793 794static int sunzilog_startup(struct uart_port *port)795{796 struct uart_sunzilog_port *up = UART_ZILOG(port);797 unsigned long flags;798 799 if (ZS_IS_CONS(up))800 return 0;801 802 uart_port_lock_irqsave(port, &flags);803 __sunzilog_startup(up);804 uart_port_unlock_irqrestore(port, flags);805 return 0;806}807 808/*809 * The test for ZS_IS_CONS is explained by the following e-mail:810 *****811 * From: Russell King <rmk@arm.linux.org.uk>812 * Date: Sun, 8 Dec 2002 10:18:38 +0000813 *814 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:815 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,816 * > and I noticed that something is not right with reference817 * > counting in this case. It seems that when the console818 * > is open by kernel initially, this is not accounted819 * > as an open, and uart_startup is not called.820 *821 * That is correct. We are unable to call uart_startup when the serial822 * console is initialised because it may need to allocate memory (as823 * request_irq does) and the memory allocators may not have been824 * initialised.825 *826 * 1. initialise the port into a state where it can send characters in the827 * console write method.828 *829 * 2. don't do the actual hardware shutdown in your shutdown() method (but830 * do the normal software shutdown - ie, free irqs etc)831 *****832 */833static void sunzilog_shutdown(struct uart_port *port)834{835 struct uart_sunzilog_port *up = UART_ZILOG(port);836 struct zilog_channel __iomem *channel;837 unsigned long flags;838 839 if (ZS_IS_CONS(up))840 return;841 842 uart_port_lock_irqsave(port, &flags);843 844 channel = ZILOG_CHANNEL_FROM_PORT(port);845 846 /* Disable receiver and transmitter. */847 up->curregs[R3] &= ~RxENAB;848 up->curregs[R5] &= ~TxENAB;849 850 /* Disable all interrupts and BRK assertion. */851 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);852 up->curregs[R5] &= ~SND_BRK;853 sunzilog_maybe_update_regs(up, channel);854 855 uart_port_unlock_irqrestore(port, flags);856}857 858/* Shared by TTY driver and serial console setup. The port lock is held859 * and local interrupts are disabled.860 */861static void862sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,863 unsigned int iflag, int brg)864{865 866 up->curregs[R10] = NRZ;867 up->curregs[R11] = TCBR | RCBR;868 869 /* Program BAUD and clock source. */870 up->curregs[R4] &= ~XCLK_MASK;871 up->curregs[R4] |= X16CLK;872 up->curregs[R12] = brg & 0xff;873 up->curregs[R13] = (brg >> 8) & 0xff;874 up->curregs[R14] = BRSRC | BRENAB;875 876 /* Character size, stop bits, and parity. */877 up->curregs[R3] &= ~RxN_MASK;878 up->curregs[R5] &= ~TxN_MASK;879 switch (cflag & CSIZE) {880 case CS5:881 up->curregs[R3] |= Rx5;882 up->curregs[R5] |= Tx5;883 up->parity_mask = 0x1f;884 break;885 case CS6:886 up->curregs[R3] |= Rx6;887 up->curregs[R5] |= Tx6;888 up->parity_mask = 0x3f;889 break;890 case CS7:891 up->curregs[R3] |= Rx7;892 up->curregs[R5] |= Tx7;893 up->parity_mask = 0x7f;894 break;895 case CS8:896 default:897 up->curregs[R3] |= Rx8;898 up->curregs[R5] |= Tx8;899 up->parity_mask = 0xff;900 break;901 }902 up->curregs[R4] &= ~0x0c;903 if (cflag & CSTOPB)904 up->curregs[R4] |= SB2;905 else906 up->curregs[R4] |= SB1;907 if (cflag & PARENB)908 up->curregs[R4] |= PAR_ENAB;909 else910 up->curregs[R4] &= ~PAR_ENAB;911 if (!(cflag & PARODD))912 up->curregs[R4] |= PAR_EVEN;913 else914 up->curregs[R4] &= ~PAR_EVEN;915 916 up->port.read_status_mask = Rx_OVR;917 if (iflag & INPCK)918 up->port.read_status_mask |= CRC_ERR | PAR_ERR;919 if (iflag & (IGNBRK | BRKINT | PARMRK))920 up->port.read_status_mask |= BRK_ABRT;921 922 up->port.ignore_status_mask = 0;923 if (iflag & IGNPAR)924 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;925 if (iflag & IGNBRK) {926 up->port.ignore_status_mask |= BRK_ABRT;927 if (iflag & IGNPAR)928 up->port.ignore_status_mask |= Rx_OVR;929 }930 931 if ((cflag & CREAD) == 0)932 up->port.ignore_status_mask = 0xff;933}934 935/* The port lock is not held. */936static void937sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,938 const struct ktermios *old)939{940 struct uart_sunzilog_port *up =941 container_of(port, struct uart_sunzilog_port, port);942 unsigned long flags;943 int baud, brg;944 945 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);946 947 uart_port_lock_irqsave(&up->port, &flags);948 949 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);950 951 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);952 953 if (UART_ENABLE_MS(&up->port, termios->c_cflag))954 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;955 else956 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;957 958 up->cflag = termios->c_cflag;959 960 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));961 962 uart_update_timeout(port, termios->c_cflag, baud);963 964 uart_port_unlock_irqrestore(&up->port, flags);965}966 967static const char *sunzilog_type(struct uart_port *port)968{969 struct uart_sunzilog_port *up = UART_ZILOG(port);970 971 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";972}973 974/* We do not request/release mappings of the registers here, this975 * happens at early serial probe time.976 */977static void sunzilog_release_port(struct uart_port *port)978{979}980 981static int sunzilog_request_port(struct uart_port *port)982{983 return 0;984}985 986/* These do not need to do anything interesting either. */987static void sunzilog_config_port(struct uart_port *port, int flags)988{989}990 991/* We do not support letting the user mess with the divisor, IRQ, etc. */992static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)993{994 return -EINVAL;995}996 997#ifdef CONFIG_CONSOLE_POLL998static int sunzilog_get_poll_char(struct uart_port *port)999{1000 unsigned char ch, r1;1001 struct uart_sunzilog_port *up =1002 container_of(port, struct uart_sunzilog_port, port);1003 struct zilog_channel __iomem *channel1004 = ZILOG_CHANNEL_FROM_PORT(&up->port);1005 1006 1007 r1 = read_zsreg(channel, R1);1008 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {1009 writeb(ERR_RES, &channel->control);1010 ZSDELAY();1011 ZS_WSYNC(channel);1012 }1013 1014 ch = readb(&channel->control);1015 ZSDELAY();1016 1017 /* This funny hack depends upon BRK_ABRT not interfering1018 * with the other bits we care about in R1.1019 */1020 if (ch & BRK_ABRT)1021 r1 |= BRK_ABRT;1022 1023 if (!(ch & Rx_CH_AV))1024 return NO_POLL_CHAR;1025 1026 ch = readb(&channel->data);1027 ZSDELAY();1028 1029 ch &= up->parity_mask;1030 return ch;1031}1032 1033static void sunzilog_put_poll_char(struct uart_port *port,1034 unsigned char ch)1035{1036 struct uart_sunzilog_port *up =1037 container_of(port, struct uart_sunzilog_port, port);1038 1039 sunzilog_putchar(&up->port, ch);1040}1041#endif /* CONFIG_CONSOLE_POLL */1042 1043static const struct uart_ops sunzilog_pops = {1044 .tx_empty = sunzilog_tx_empty,1045 .set_mctrl = sunzilog_set_mctrl,1046 .get_mctrl = sunzilog_get_mctrl,1047 .stop_tx = sunzilog_stop_tx,1048 .start_tx = sunzilog_start_tx,1049 .stop_rx = sunzilog_stop_rx,1050 .enable_ms = sunzilog_enable_ms,1051 .break_ctl = sunzilog_break_ctl,1052 .startup = sunzilog_startup,1053 .shutdown = sunzilog_shutdown,1054 .set_termios = sunzilog_set_termios,1055 .type = sunzilog_type,1056 .release_port = sunzilog_release_port,1057 .request_port = sunzilog_request_port,1058 .config_port = sunzilog_config_port,1059 .verify_port = sunzilog_verify_port,1060#ifdef CONFIG_CONSOLE_POLL1061 .poll_get_char = sunzilog_get_poll_char,1062 .poll_put_char = sunzilog_put_poll_char,1063#endif1064};1065 1066static int uart_chip_count;1067static struct uart_sunzilog_port *sunzilog_port_table;1068static struct zilog_layout __iomem **sunzilog_chip_regs;1069 1070static struct uart_sunzilog_port *sunzilog_irq_chain;1071 1072static struct uart_driver sunzilog_reg = {1073 .owner = THIS_MODULE,1074 .driver_name = "sunzilog",1075 .dev_name = "ttyS",1076 .major = TTY_MAJOR,1077};1078 1079static int __init sunzilog_alloc_tables(int num_sunzilog)1080{1081 struct uart_sunzilog_port *up;1082 unsigned long size;1083 int num_channels = num_sunzilog * 2;1084 int i;1085 1086 size = num_channels * sizeof(struct uart_sunzilog_port);1087 sunzilog_port_table = kzalloc(size, GFP_KERNEL);1088 if (!sunzilog_port_table)1089 return -ENOMEM;1090 1091 for (i = 0; i < num_channels; i++) {1092 up = &sunzilog_port_table[i];1093 1094 spin_lock_init(&up->port.lock);1095 1096 if (i == 0)1097 sunzilog_irq_chain = up;1098 1099 if (i < num_channels - 1)1100 up->next = up + 1;1101 else1102 up->next = NULL;1103 }1104 1105 size = num_sunzilog * sizeof(struct zilog_layout __iomem *);1106 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);1107 if (!sunzilog_chip_regs) {1108 kfree(sunzilog_port_table);1109 sunzilog_irq_chain = NULL;1110 return -ENOMEM;1111 }1112 1113 return 0;1114}1115 1116static void sunzilog_free_tables(void)1117{1118 kfree(sunzilog_port_table);1119 sunzilog_irq_chain = NULL;1120 kfree(sunzilog_chip_regs);1121}1122 1123#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */1124 1125static void __maybe_unused sunzilog_putchar(struct uart_port *port, unsigned char ch)1126{1127 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);1128 int loops = ZS_PUT_CHAR_MAX_DELAY;1129 1130 /* This is a timed polling loop so do not switch the explicit1131 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM1132 */1133 do {1134 unsigned char val = readb(&channel->control);1135 if (val & Tx_BUF_EMP) {1136 ZSDELAY();1137 break;1138 }1139 udelay(5);1140 } while (--loops);1141 1142 writeb(ch, &channel->data);1143 ZSDELAY();1144 ZS_WSYNC(channel);1145}1146 1147#ifdef CONFIG_SERIO1148 1149static DEFINE_SPINLOCK(sunzilog_serio_lock);1150 1151static int sunzilog_serio_write(struct serio *serio, unsigned char ch)1152{1153 struct uart_sunzilog_port *up = serio->port_data;1154 unsigned long flags;1155 1156 spin_lock_irqsave(&sunzilog_serio_lock, flags);1157 1158 sunzilog_putchar(&up->port, ch);1159 1160 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);1161 1162 return 0;1163}1164 1165static int sunzilog_serio_open(struct serio *serio)1166{1167 struct uart_sunzilog_port *up = serio->port_data;1168 unsigned long flags;1169 int ret;1170 1171 spin_lock_irqsave(&sunzilog_serio_lock, flags);1172 if (!up->serio_open) {1173 up->serio_open = 1;1174 ret = 0;1175 } else1176 ret = -EBUSY;1177 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);1178 1179 return ret;1180}1181 1182static void sunzilog_serio_close(struct serio *serio)1183{1184 struct uart_sunzilog_port *up = serio->port_data;1185 unsigned long flags;1186 1187 spin_lock_irqsave(&sunzilog_serio_lock, flags);1188 up->serio_open = 0;1189 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);1190}1191 1192#endif /* CONFIG_SERIO */1193 1194#ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE1195static void1196sunzilog_console_write(struct console *con, const char *s, unsigned int count)1197{1198 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];1199 unsigned long flags;1200 int locked = 1;1201 1202 if (up->port.sysrq || oops_in_progress)1203 locked = uart_port_trylock_irqsave(&up->port, &flags);1204 else1205 uart_port_lock_irqsave(&up->port, &flags);1206 1207 uart_console_write(&up->port, s, count, sunzilog_putchar);1208 udelay(2);1209 1210 if (locked)1211 uart_port_unlock_irqrestore(&up->port, flags);1212}1213 1214static int __init sunzilog_console_setup(struct console *con, char *options)1215{1216 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];1217 unsigned long flags;1218 int baud, brg;1219 1220 if (up->port.type != PORT_SUNZILOG)1221 return -EINVAL;1222 1223 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",1224 (sunzilog_reg.minor - 64) + con->index, con->index);1225 1226 /* Get firmware console settings. */1227 sunserial_console_termios(con, up->port.dev->of_node);1228 1229 /* Firmware console speed is limited to 150-->38400 baud so1230 * this hackish cflag thing is OK.1231 */1232 switch (con->cflag & CBAUD) {1233 case B150: baud = 150; break;1234 case B300: baud = 300; break;1235 case B600: baud = 600; break;1236 case B1200: baud = 1200; break;1237 case B2400: baud = 2400; break;1238 case B4800: baud = 4800; break;1239 default: case B9600: baud = 9600; break;1240 case B19200: baud = 19200; break;1241 case B38400: baud = 38400; break;1242 }1243 1244 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);1245 1246 uart_port_lock_irqsave(&up->port, &flags);1247 1248 up->curregs[R15] |= BRKIE;1249 sunzilog_convert_to_zs(up, con->cflag, 0, brg);1250 1251 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);1252 __sunzilog_startup(up);1253 1254 uart_port_unlock_irqrestore(&up->port, flags);1255 1256 return 0;1257}1258 1259static struct console sunzilog_console_ops = {1260 .name = "ttyS",1261 .write = sunzilog_console_write,1262 .device = uart_console_device,1263 .setup = sunzilog_console_setup,1264 .flags = CON_PRINTBUFFER,1265 .index = -1,1266 .data = &sunzilog_reg,1267};1268 1269static inline struct console *SUNZILOG_CONSOLE(void)1270{1271 return &sunzilog_console_ops;1272}1273 1274#else1275#define SUNZILOG_CONSOLE() (NULL)1276#endif1277 1278static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)1279{1280 int baud, brg;1281 1282 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {1283 up->cflag = B1200 | CS8 | CLOCAL | CREAD;1284 baud = 1200;1285 } else {1286 up->cflag = B4800 | CS8 | CLOCAL | CREAD;1287 baud = 4800;1288 }1289 1290 up->curregs[R15] |= BRKIE;1291 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);1292 sunzilog_convert_to_zs(up, up->cflag, 0, brg);1293 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);1294 __sunzilog_startup(up);1295}1296 1297#ifdef CONFIG_SERIO1298static void sunzilog_register_serio(struct uart_sunzilog_port *up)1299{1300 struct serio *serio = &up->serio;1301 1302 serio->port_data = up;1303 1304 serio->id.type = SERIO_RS232;1305 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {1306 serio->id.proto = SERIO_SUNKBD;1307 strscpy(serio->name, "zskbd", sizeof(serio->name));1308 } else {1309 serio->id.proto = SERIO_SUN;1310 serio->id.extra = 1;1311 strscpy(serio->name, "zsms", sizeof(serio->name));1312 }1313 strscpy(serio->phys,1314 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?1315 "zs/serio0" : "zs/serio1"),1316 sizeof(serio->phys));1317 1318 serio->write = sunzilog_serio_write;1319 serio->open = sunzilog_serio_open;1320 serio->close = sunzilog_serio_close;1321 serio->dev.parent = up->port.dev;1322 1323 serio_register_port(serio);1324}1325#endif1326 1327static void sunzilog_init_hw(struct uart_sunzilog_port *up)1328{1329 struct zilog_channel __iomem *channel;1330 unsigned long flags;1331 int baud, brg;1332 1333 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);1334 1335 uart_port_lock_irqsave(&up->port, &flags);1336 if (ZS_IS_CHANNEL_A(up)) {1337 write_zsreg(channel, R9, FHWRES);1338 ZSDELAY_LONG();1339 (void) read_zsreg(channel, R0);1340 }1341 1342 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |1343 SUNZILOG_FLAG_CONS_MOUSE)) {1344 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;1345 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;1346 up->curregs[R3] = RxENAB | Rx8;1347 up->curregs[R5] = TxENAB | Tx8;1348 up->curregs[R6] = 0x00; /* SDLC Address */1349 up->curregs[R7] = 0x7E; /* SDLC Flag */1350 up->curregs[R9] = NV;1351 up->curregs[R7p] = 0x00;1352 sunzilog_init_kbdms(up);1353 /* Only enable interrupts if an ISR handler available */1354 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)1355 up->curregs[R9] |= MIE;1356 write_zsreg(channel, R9, up->curregs[R9]);1357 } else {1358 /* Normal serial TTY. */1359 up->parity_mask = 0xff;1360 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;1361 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;1362 up->curregs[R3] = RxENAB | Rx8;1363 up->curregs[R5] = TxENAB | Tx8;1364 up->curregs[R6] = 0x00; /* SDLC Address */1365 up->curregs[R7] = 0x7E; /* SDLC Flag */1366 up->curregs[R9] = NV;1367 up->curregs[R10] = NRZ;1368 up->curregs[R11] = TCBR | RCBR;1369 baud = 9600;1370 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);1371 up->curregs[R12] = (brg & 0xff);1372 up->curregs[R13] = (brg >> 8) & 0xff;1373 up->curregs[R14] = BRSRC | BRENAB;1374 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */1375 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;1376 if (__load_zsregs(channel, up->curregs)) {1377 up->flags |= SUNZILOG_FLAG_ESCC;1378 }1379 /* Only enable interrupts if an ISR handler available */1380 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)1381 up->curregs[R9] |= MIE;1382 write_zsreg(channel, R9, up->curregs[R9]);1383 }1384 1385 uart_port_unlock_irqrestore(&up->port, flags);1386 1387#ifdef CONFIG_SERIO1388 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |1389 SUNZILOG_FLAG_CONS_MOUSE))1390 sunzilog_register_serio(up);1391#endif1392}1393 1394static int zilog_irq;1395 1396static int zs_probe(struct platform_device *op)1397{1398 static int kbm_inst, uart_inst;1399 int inst;1400 struct uart_sunzilog_port *up;1401 struct zilog_layout __iomem *rp;1402 int keyboard_mouse = 0;1403 int err;1404 1405 if (of_property_present(op->dev.of_node, "keyboard"))1406 keyboard_mouse = 1;1407 1408 /* uarts must come before keyboards/mice */1409 if (keyboard_mouse)1410 inst = uart_chip_count + kbm_inst;1411 else1412 inst = uart_inst;1413 1414 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,1415 sizeof(struct zilog_layout),1416 "zs");1417 if (!sunzilog_chip_regs[inst])1418 return -ENOMEM;1419 1420 rp = sunzilog_chip_regs[inst];1421 1422 if (!zilog_irq)1423 zilog_irq = op->archdata.irqs[0];1424 1425 up = &sunzilog_port_table[inst * 2];1426 1427 /* Channel A */1428 up[0].port.mapbase = op->resource[0].start + 0x00;1429 up[0].port.membase = (void __iomem *) &rp->channelA;1430 up[0].port.iotype = UPIO_MEM;1431 up[0].port.irq = op->archdata.irqs[0];1432 up[0].port.uartclk = ZS_CLOCK;1433 up[0].port.fifosize = 1;1434 up[0].port.ops = &sunzilog_pops;1435 up[0].port.type = PORT_SUNZILOG;1436 up[0].port.flags = 0;1437 up[0].port.line = (inst * 2) + 0;1438 up[0].port.dev = &op->dev;1439 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;1440 up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);1441 if (keyboard_mouse)1442 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;1443 sunzilog_init_hw(&up[0]);1444 1445 /* Channel B */1446 up[1].port.mapbase = op->resource[0].start + 0x04;1447 up[1].port.membase = (void __iomem *) &rp->channelB;1448 up[1].port.iotype = UPIO_MEM;1449 up[1].port.irq = op->archdata.irqs[0];1450 up[1].port.uartclk = ZS_CLOCK;1451 up[1].port.fifosize = 1;1452 up[1].port.ops = &sunzilog_pops;1453 up[1].port.type = PORT_SUNZILOG;1454 up[1].port.flags = 0;1455 up[1].port.line = (inst * 2) + 1;1456 up[1].port.dev = &op->dev;1457 up[1].flags |= 0;1458 up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);1459 if (keyboard_mouse)1460 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;1461 sunzilog_init_hw(&up[1]);1462 1463 if (!keyboard_mouse) {1464 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,1465 &sunzilog_reg, up[0].port.line,1466 false))1467 up->flags |= SUNZILOG_FLAG_IS_CONS;1468 err = uart_add_one_port(&sunzilog_reg, &up[0].port);1469 if (err) {1470 of_iounmap(&op->resource[0],1471 rp, sizeof(struct zilog_layout));1472 return err;1473 }1474 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,1475 &sunzilog_reg, up[1].port.line,1476 false))1477 up->flags |= SUNZILOG_FLAG_IS_CONS;1478 err = uart_add_one_port(&sunzilog_reg, &up[1].port);1479 if (err) {1480 uart_remove_one_port(&sunzilog_reg, &up[0].port);1481 of_iounmap(&op->resource[0],1482 rp, sizeof(struct zilog_layout));1483 return err;1484 }1485 uart_inst++;1486 } else {1487 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "1488 "is a %s\n",1489 dev_name(&op->dev),1490 (unsigned long long) up[0].port.mapbase,1491 op->archdata.irqs[0], sunzilog_type(&up[0].port));1492 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "1493 "is a %s\n",1494 dev_name(&op->dev),1495 (unsigned long long) up[1].port.mapbase,1496 op->archdata.irqs[0], sunzilog_type(&up[1].port));1497 kbm_inst++;1498 }1499 1500 platform_set_drvdata(op, &up[0]);1501 1502 return 0;1503}1504 1505static void zs_remove_one(struct uart_sunzilog_port *up)1506{1507 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {1508#ifdef CONFIG_SERIO1509 serio_unregister_port(&up->serio);1510#endif1511 } else1512 uart_remove_one_port(&sunzilog_reg, &up->port);1513}1514 1515static void zs_remove(struct platform_device *op)1516{1517 struct uart_sunzilog_port *up = platform_get_drvdata(op);1518 struct zilog_layout __iomem *regs;1519 1520 zs_remove_one(&up[0]);1521 zs_remove_one(&up[1]);1522 1523 regs = sunzilog_chip_regs[up[0].port.line / 2];1524 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));1525}1526 1527static const struct of_device_id zs_match[] = {1528 {1529 .name = "zs",1530 },1531 {},1532};1533MODULE_DEVICE_TABLE(of, zs_match);1534 1535static struct platform_driver zs_driver = {1536 .driver = {1537 .name = "zs",1538 .of_match_table = zs_match,1539 },1540 .probe = zs_probe,1541 .remove_new = zs_remove,1542};1543 1544static int __init sunzilog_init(void)1545{1546 struct device_node *dp;1547 int err;1548 int num_keybms = 0;1549 int num_sunzilog = 0;1550 1551 for_each_node_by_name(dp, "zs") {1552 num_sunzilog++;1553 if (of_property_present(dp, "keyboard"))1554 num_keybms++;1555 }1556 1557 if (num_sunzilog) {1558 err = sunzilog_alloc_tables(num_sunzilog);1559 if (err)1560 goto out;1561 1562 uart_chip_count = num_sunzilog - num_keybms;1563 1564 err = sunserial_register_minors(&sunzilog_reg,1565 uart_chip_count * 2);1566 if (err)1567 goto out_free_tables;1568 }1569 1570 err = platform_driver_register(&zs_driver);1571 if (err)1572 goto out_unregister_uart;1573 1574 if (zilog_irq) {1575 struct uart_sunzilog_port *up = sunzilog_irq_chain;1576 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,1577 "zs", sunzilog_irq_chain);1578 if (err)1579 goto out_unregister_driver;1580 1581 /* Enable Interrupts */1582 while (up) {1583 struct zilog_channel __iomem *channel;1584 1585 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */1586 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);1587 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;1588 up->curregs[R9] |= MIE;1589 write_zsreg(channel, R9, up->curregs[R9]);1590 up = up->next;1591 }1592 }1593 1594out:1595 return err;1596 1597out_unregister_driver:1598 platform_driver_unregister(&zs_driver);1599 1600out_unregister_uart:1601 if (num_sunzilog) {1602 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);1603 sunzilog_reg.cons = NULL;1604 }1605 1606out_free_tables:1607 sunzilog_free_tables();1608 goto out;1609}1610 1611static void __exit sunzilog_exit(void)1612{1613 platform_driver_unregister(&zs_driver);1614 1615 if (zilog_irq) {1616 struct uart_sunzilog_port *up = sunzilog_irq_chain;1617 1618 /* Disable Interrupts */1619 while (up) {1620 struct zilog_channel __iomem *channel;1621 1622 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */1623 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);1624 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;1625 up->curregs[R9] &= ~MIE;1626 write_zsreg(channel, R9, up->curregs[R9]);1627 up = up->next;1628 }1629 1630 free_irq(zilog_irq, sunzilog_irq_chain);1631 zilog_irq = 0;1632 }1633 1634 if (sunzilog_reg.nr) {1635 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);1636 sunzilog_free_tables();1637 }1638}1639 1640module_init(sunzilog_init);1641module_exit(sunzilog_exit);1642 1643MODULE_AUTHOR("David S. Miller");1644MODULE_DESCRIPTION("Sun Zilog serial port driver");1645MODULE_VERSION("2.0");1646MODULE_LICENSE("GPL");1647