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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef _SUNZILOG_H3#define _SUNZILOG_H4 5struct zilog_channel {6 volatile unsigned char control;7 volatile unsigned char __pad1;8 volatile unsigned char data;9 volatile unsigned char __pad2;10};11 12struct zilog_layout {13 struct zilog_channel channelB;14 struct zilog_channel channelA;15};16 17#define NUM_ZSREGS 1718#define R7p 16 /* Written as R7 with P15 bit 0 set */19 20/* Conversion routines to/from brg time constants from/to bits21 * per second.22 */23#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))24#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)25 26/* The Zilog register set */27 28#define FLAG 0x7e29 30/* Write Register 0 */31#define R0 0 /* Register selects */32#define R1 133#define R2 234#define R3 335#define R4 436#define R5 537#define R6 638#define R7 739#define R8 840#define R9 941#define R10 1042#define R11 1143#define R12 1244#define R13 1345#define R14 1446#define R15 1547 48#define NULLCODE 0 /* Null Code */49#define POINT_HIGH 0x8 /* Select upper half of registers */50#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */51#define SEND_ABORT 0x18 /* HDLC Abort */52#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */53#define RES_Tx_P 0x28 /* Reset TxINT Pending */54#define ERR_RES 0x30 /* Error Reset */55#define RES_H_IUS 0x38 /* Reset highest IUS */56 57#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */58#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */59#define RES_EOM_L 0xC0 /* Reset EOM latch */60 61/* Write Register 1 */62 63#define EXT_INT_ENAB 0x1 /* Ext Int Enable */64#define TxINT_ENAB 0x2 /* Tx Int Enable */65#define PAR_SPEC 0x4 /* Parity is special condition */66 67#define RxINT_DISAB 0 /* Rx Int Disable */68#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */69#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */70#define INT_ERR_Rx 0x18 /* Int on error only */71#define RxINT_MASK 0x1872 73#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */74#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */75#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */76 77/* Write Register #2 (Interrupt Vector) */78 79/* Write Register 3 */80 81#define RxENAB 0x1 /* Rx Enable */82#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */83#define ADD_SM 0x4 /* Address Search Mode (SDLC) */84#define RxCRC_ENAB 0x8 /* Rx CRC Enable */85#define ENT_HM 0x10 /* Enter Hunt Mode */86#define AUTO_ENAB 0x20 /* Auto Enables */87#define Rx5 0x0 /* Rx 5 Bits/Character */88#define Rx7 0x40 /* Rx 7 Bits/Character */89#define Rx6 0x80 /* Rx 6 Bits/Character */90#define Rx8 0xc0 /* Rx 8 Bits/Character */91#define RxN_MASK 0xc092 93/* Write Register 4 */94 95#define PAR_ENAB 0x1 /* Parity Enable */96#define PAR_EVEN 0x2 /* Parity Even/Odd* */97 98#define SYNC_ENAB 0 /* Sync Modes Enable */99#define SB1 0x4 /* 1 stop bit/char */100#define SB15 0x8 /* 1.5 stop bits/char */101#define SB2 0xc /* 2 stop bits/char */102 103#define MONSYNC 0 /* 8 Bit Sync character */104#define BISYNC 0x10 /* 16 bit sync character */105#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */106#define EXTSYNC 0x30 /* External Sync Mode */107 108#define X1CLK 0x0 /* x1 clock mode */109#define X16CLK 0x40 /* x16 clock mode */110#define X32CLK 0x80 /* x32 clock mode */111#define X64CLK 0xC0 /* x64 clock mode */112#define XCLK_MASK 0xC0113 114/* Write Register 5 */115 116#define TxCRC_ENAB 0x1 /* Tx CRC Enable */117#define RTS 0x2 /* RTS */118#define SDLC_CRC 0x4 /* SDLC/CRC-16 */119#define TxENAB 0x8 /* Tx Enable */120#define SND_BRK 0x10 /* Send Break */121#define Tx5 0x0 /* Tx 5 bits (or less)/character */122#define Tx7 0x20 /* Tx 7 bits/character */123#define Tx6 0x40 /* Tx 6 bits/character */124#define Tx8 0x60 /* Tx 8 bits/character */125#define TxN_MASK 0x60126#define DTR 0x80 /* DTR */127 128/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */129 130/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */131 132/* Write Register 7' (ESCC Only) */133#define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */134#define AUTO_EOM_RST 2 /* Automatic EOM Reset */135#define AUTOnRTS 4 /* Automatic /RTS pin deactivation */136#define RxFIFO_LVL 8 /* Receive FIFO interrupt level */137#define nDTRnREQ 0x10 /* /DTR/REQ timing */138#define TxFIFO_LVL 0x20 /* Transmit FIFO interrupt level */139#define EXT_RD_EN 0x40 /* Extended read register enable */140 141/* Write Register 8 (transmit buffer) */142 143/* Write Register 9 (Master interrupt control) */144#define VIS 1 /* Vector Includes Status */145#define NV 2 /* No Vector */146#define DLC 4 /* Disable Lower Chain */147#define MIE 8 /* Master Interrupt Enable */148#define STATHI 0x10 /* Status high */149#define SWIACK 0x20 /* Software Interrupt Ack (not on NMOS) */150#define NORESET 0 /* No reset on write to R9 */151#define CHRB 0x40 /* Reset channel B */152#define CHRA 0x80 /* Reset channel A */153#define FHWRES 0xc0 /* Force hardware reset */154 155/* Write Register 10 (misc control bits) */156#define BIT6 1 /* 6 bit/8bit sync */157#define LOOPMODE 2 /* SDLC Loop mode */158#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */159#define MARKIDLE 8 /* Mark/flag on idle */160#define GAOP 0x10 /* Go active on poll */161#define NRZ 0 /* NRZ mode */162#define NRZI 0x20 /* NRZI mode */163#define FM1 0x40 /* FM1 (transition = 1) */164#define FM0 0x60 /* FM0 (transition = 0) */165#define CRCPS 0x80 /* CRC Preset I/O */166 167/* Write Register 11 (Clock Mode control) */168#define TRxCXT 0 /* TRxC = Xtal output */169#define TRxCTC 1 /* TRxC = Transmit clock */170#define TRxCBR 2 /* TRxC = BR Generator Output */171#define TRxCDP 3 /* TRxC = DPLL output */172#define TRxCOI 4 /* TRxC O/I */173#define TCRTxCP 0 /* Transmit clock = RTxC pin */174#define TCTRxCP 8 /* Transmit clock = TRxC pin */175#define TCBR 0x10 /* Transmit clock = BR Generator output */176#define TCDPLL 0x18 /* Transmit clock = DPLL output */177#define RCRTxCP 0 /* Receive clock = RTxC pin */178#define RCTRxCP 0x20 /* Receive clock = TRxC pin */179#define RCBR 0x40 /* Receive clock = BR Generator output */180#define RCDPLL 0x60 /* Receive clock = DPLL output */181#define RTxCX 0x80 /* RTxC Xtal/No Xtal */182 183/* Write Register 12 (lower byte of baud rate generator time constant) */184 185/* Write Register 13 (upper byte of baud rate generator time constant) */186 187/* Write Register 14 (Misc control bits) */188#define BRENAB 1 /* Baud rate generator enable */189#define BRSRC 2 /* Baud rate generator source */190#define DTRREQ 4 /* DTR/Request function */191#define AUTOECHO 8 /* Auto Echo */192#define LOOPBAK 0x10 /* Local loopback */193#define SEARCH 0x20 /* Enter search mode */194#define RMC 0x40 /* Reset missing clock */195#define DISDPLL 0x60 /* Disable DPLL */196#define SSBR 0x80 /* Set DPLL source = BR generator */197#define SSRTxC 0xa0 /* Set DPLL source = RTxC */198#define SFMM 0xc0 /* Set FM mode */199#define SNRZI 0xe0 /* Set NRZI mode */200 201/* Write Register 15 (external/status interrupt control) */202#define WR7pEN 1 /* WR7' Enable (ESCC only) */203#define ZCIE 2 /* Zero count IE */204#define FIFOEN 4 /* FIFO Enable (ESCC only) */205#define DCDIE 8 /* DCD IE */206#define SYNCIE 0x10 /* Sync/hunt IE */207#define CTSIE 0x20 /* CTS IE */208#define TxUIE 0x40 /* Tx Underrun/EOM IE */209#define BRKIE 0x80 /* Break/Abort IE */210 211 212/* Read Register 0 */213#define Rx_CH_AV 0x1 /* Rx Character Available */214#define ZCOUNT 0x2 /* Zero count */215#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */216#define DCD 0x8 /* DCD */217#define SYNC 0x10 /* Sync/hunt */218#define CTS 0x20 /* CTS */219#define TxEOM 0x40 /* Tx underrun */220#define BRK_ABRT 0x80 /* Break/Abort */221 222/* Read Register 1 */223#define ALL_SNT 0x1 /* All sent */224/* Residue Data for 8 Rx bits/char programmed */225#define RES3 0x8 /* 0/3 */226#define RES4 0x4 /* 0/4 */227#define RES5 0xc /* 0/5 */228#define RES6 0x2 /* 0/6 */229#define RES7 0xa /* 0/7 */230#define RES8 0x6 /* 0/8 */231#define RES18 0xe /* 1/8 */232#define RES28 0x0 /* 2/8 */233/* Special Rx Condition Interrupts */234#define PAR_ERR 0x10 /* Parity error */235#define Rx_OVR 0x20 /* Rx Overrun Error */236#define CRC_ERR 0x40 /* CRC/Framing Error */237#define END_FR 0x80 /* End of Frame (SDLC) */238 239/* Read Register 2 (channel b only) - Interrupt vector */240#define CHB_Tx_EMPTY 0x00241#define CHB_EXT_STAT 0x02242#define CHB_Rx_AVAIL 0x04243#define CHB_SPECIAL 0x06244#define CHA_Tx_EMPTY 0x08245#define CHA_EXT_STAT 0x0a246#define CHA_Rx_AVAIL 0x0c247#define CHA_SPECIAL 0x0e248#define STATUS_MASK 0x0e249 250/* Read Register 3 (interrupt pending register) ch a only */251#define CHBEXT 0x1 /* Channel B Ext/Stat IP */252#define CHBTxIP 0x2 /* Channel B Tx IP */253#define CHBRxIP 0x4 /* Channel B Rx IP */254#define CHAEXT 0x8 /* Channel A Ext/Stat IP */255#define CHATxIP 0x10 /* Channel A Tx IP */256#define CHARxIP 0x20 /* Channel A Rx IP */257 258/* Read Register 6 (LSB frame byte count [Not on NMOS]) */259 260/* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */261 262/* Read Register 8 (receive data register) */263 264/* Read Register 10 (misc status bits) */265#define ONLOOP 2 /* On loop */266#define LOOPSEND 0x10 /* Loop sending */267#define CLK2MIS 0x40 /* Two clocks missing */268#define CLK1MIS 0x80 /* One clock missing */269 270/* Read Register 12 (lower byte of baud rate generator constant) */271 272/* Read Register 13 (upper byte of baud rate generator constant) */273 274/* Read Register 15 (value of WR 15) */275 276/* Misc macros */277#define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \278 udelay(5); } while(0)279 280#define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \281 udelay(5); } while(0)282 283#define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \284 udelay(2); \285 sbus_readb(&channel->data); \286 udelay(2); \287 sbus_readb(&channel->data); \288 udelay(2); } while(0)289 290#endif /* _SUNZILOG_H */291