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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Cadence UART driver (found in Xilinx Zynq)4 *5 * Copyright (c) 2011 - 2014 Xilinx, Inc.6 *7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This8 * still shows in the naming of this file, the kconfig symbols and some symbols9 * in the code.10 */11 12#include <linux/platform_device.h>13#include <linux/serial.h>14#include <linux/console.h>15#include <linux/serial_core.h>16#include <linux/slab.h>17#include <linux/tty.h>18#include <linux/tty_flip.h>19#include <linux/clk.h>20#include <linux/irq.h>21#include <linux/io.h>22#include <linux/of.h>23#include <linux/module.h>24#include <linux/pm_runtime.h>25#include <linux/gpio.h>26#include <linux/gpio/consumer.h>27#include <linux/delay.h>28#include <linux/reset.h>29 30#define CDNS_UART_TTY_NAME "ttyPS"31#define CDNS_UART_NAME "xuartps"32#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */33#define CDNS_UART_MINOR 0 /* works best with devtmpfs */34#define CDNS_UART_NR_PORTS 1635#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */36#define CDNS_UART_REGISTER_SPACE 0x100037#define TX_TIMEOUT 50000038 39/* Rx Trigger level */40static int rx_trigger_level = 56;41module_param(rx_trigger_level, uint, 0444);42MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");43 44/* Rx Timeout */45static int rx_timeout = 10;46module_param(rx_timeout, uint, 0444);47MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");48 49/* Register offsets for the UART. */50#define CDNS_UART_CR 0x00 /* Control Register */51#define CDNS_UART_MR 0x04 /* Mode Register */52#define CDNS_UART_IER 0x08 /* Interrupt Enable */53#define CDNS_UART_IDR 0x0C /* Interrupt Disable */54#define CDNS_UART_IMR 0x10 /* Interrupt Mask */55#define CDNS_UART_ISR 0x14 /* Interrupt Status */56#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */57#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */58#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */59#define CDNS_UART_MODEMCR 0x24 /* Modem Control */60#define CDNS_UART_MODEMSR 0x28 /* Modem Status */61#define CDNS_UART_SR 0x2C /* Channel Status */62#define CDNS_UART_FIFO 0x30 /* FIFO */63#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */64#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */65#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */66#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */67#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */68#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */69 70/* Control Register Bit Definitions */71#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */72#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */73#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */74#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */75#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */76#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */77#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */78#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */79#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */80#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */81#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */82#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */83 84/*85 * Mode Register:86 * The mode register (MR) defines the mode of transfer as well as the data87 * format. If this register is modified during transmission or reception,88 * data validity cannot be guaranteed.89 */90#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */91#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */92#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */93#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */94 95#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */96#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */97 98#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */99#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */100#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */101#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */102#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */103 104#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */105#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */106#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */107 108/*109 * Interrupt Registers:110 * Interrupt control logic uses the interrupt enable register (IER) and the111 * interrupt disable register (IDR) to set the value of the bits in the112 * interrupt mask register (IMR). The IMR determines whether to pass an113 * interrupt to the interrupt status register (ISR).114 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an115 * interrupt. IMR and ISR are read only, and IER and IDR are write only.116 * Reading either IER or IDR returns 0x00.117 * All four registers have the same bit definitions.118 */119#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */120#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */121#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */122#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */123#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */124#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */125#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */126#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */127#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */128#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */129#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */130 131 /*132 * Do not enable parity error interrupt for the following133 * reason: When parity error interrupt is enabled, each Rx134 * parity error always results in 2 events. The first one135 * being parity error interrupt and the second one with a136 * proper Rx interrupt with the incoming data. Disabling137 * parity error interrupt ensures better handling of parity138 * error events. With this change, for a parity error case, we139 * get a Rx interrupt with parity error set in ISR register140 * and we still handle parity errors in the desired way.141 */142 143#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \144 CDNS_UART_IXR_OVERRUN | \145 CDNS_UART_IXR_RXTRIG | \146 CDNS_UART_IXR_TOUT)147 148/* Goes in read_status_mask for break detection as the HW doesn't do it*/149#define CDNS_UART_IXR_BRK 0x00002000150 151#define CDNS_UART_RXBS_SUPPORT BIT(1)152/*153 * Modem Control register:154 * The read/write Modem Control register controls the interface with the modem155 * or data set, or a peripheral device emulating a modem.156 */157#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */158#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */159#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */160 161/*162 * Modem Status register:163 * The read/write Modem Status register reports the interface with the modem164 * or data set, or a peripheral device emulating a modem.165 */166#define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */167#define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */168#define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */169#define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */170 171/*172 * Channel Status Register:173 * The channel status register (CSR) is provided to enable the control logic174 * to monitor the status of bits in the channel interrupt status register,175 * even if these are masked out by the interrupt mask register.176 */177#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */178#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */179#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */180#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */181#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */182 183/* baud dividers min/max values */184#define CDNS_UART_BDIV_MIN 4185#define CDNS_UART_BDIV_MAX 255186#define CDNS_UART_CD_MAX 65535187#define UART_AUTOSUSPEND_TIMEOUT 3000188 189/**190 * struct cdns_uart - device data191 * @port: Pointer to the UART port192 * @uartclk: Reference clock193 * @pclk: APB clock194 * @cdns_uart_driver: Pointer to UART driver195 * @baud: Current baud rate196 * @clk_rate_change_nb: Notifier block for clock changes197 * @quirks: Flags for RXBS support.198 * @cts_override: Modem control state override199 * @gpiod_rts: Pointer to the gpio descriptor200 * @rs485_tx_started: RS485 tx state201 * @tx_timer: Timer for tx202 * @rstc: Pointer to the reset control203 */204struct cdns_uart {205 struct uart_port *port;206 struct clk *uartclk;207 struct clk *pclk;208 struct uart_driver *cdns_uart_driver;209 unsigned int baud;210 struct notifier_block clk_rate_change_nb;211 u32 quirks;212 bool cts_override;213 struct gpio_desc *gpiod_rts;214 bool rs485_tx_started;215 struct hrtimer tx_timer;216 struct reset_control *rstc;217};218struct cdns_platform_data {219 u32 quirks;220};221 222static struct serial_rs485 cdns_rs485_supported = {223 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |224 SER_RS485_RTS_AFTER_SEND,225 .delay_rts_before_send = 1,226 .delay_rts_after_send = 1,227};228 229#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \230 clk_rate_change_nb)231 232/**233 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.234 * @dev_id: Id of the UART port235 * @isrstatus: The interrupt status register value as read236 * Return: None237 */238static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)239{240 struct uart_port *port = (struct uart_port *)dev_id;241 struct cdns_uart *cdns_uart = port->private_data;242 unsigned int data;243 unsigned int rxbs_status = 0;244 unsigned int status_mask;245 unsigned int framerrprocessed = 0;246 char status = TTY_NORMAL;247 bool is_rxbs_support;248 249 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;250 251 while ((readl(port->membase + CDNS_UART_SR) &252 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {253 if (is_rxbs_support)254 rxbs_status = readl(port->membase + CDNS_UART_RXBS);255 data = readl(port->membase + CDNS_UART_FIFO);256 port->icount.rx++;257 /*258 * There is no hardware break detection in Zynq, so we interpret259 * framing error with all-zeros data as a break sequence.260 * Most of the time, there's another non-zero byte at the261 * end of the sequence.262 */263 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {264 if (!data) {265 port->read_status_mask |= CDNS_UART_IXR_BRK;266 framerrprocessed = 1;267 continue;268 }269 }270 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {271 port->icount.brk++;272 status = TTY_BREAK;273 if (uart_handle_break(port))274 continue;275 }276 277 isrstatus &= port->read_status_mask;278 isrstatus &= ~port->ignore_status_mask;279 status_mask = port->read_status_mask;280 status_mask &= ~port->ignore_status_mask;281 282 if (data &&283 (port->read_status_mask & CDNS_UART_IXR_BRK)) {284 port->read_status_mask &= ~CDNS_UART_IXR_BRK;285 port->icount.brk++;286 if (uart_handle_break(port))287 continue;288 }289 290 if (uart_handle_sysrq_char(port, data))291 continue;292 293 if (is_rxbs_support) {294 if ((rxbs_status & CDNS_UART_RXBS_PARITY)295 && (status_mask & CDNS_UART_IXR_PARITY)) {296 port->icount.parity++;297 status = TTY_PARITY;298 }299 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)300 && (status_mask & CDNS_UART_IXR_PARITY)) {301 port->icount.frame++;302 status = TTY_FRAME;303 }304 } else {305 if (isrstatus & CDNS_UART_IXR_PARITY) {306 port->icount.parity++;307 status = TTY_PARITY;308 }309 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&310 !framerrprocessed) {311 port->icount.frame++;312 status = TTY_FRAME;313 }314 }315 if (isrstatus & CDNS_UART_IXR_OVERRUN) {316 port->icount.overrun++;317 tty_insert_flip_char(&port->state->port, 0,318 TTY_OVERRUN);319 }320 tty_insert_flip_char(&port->state->port, data, status);321 isrstatus = 0;322 }323 324 tty_flip_buffer_push(&port->state->port);325}326 327/**328 * cdns_rts_gpio_enable - Configure RTS/GPIO to high/low329 * @cdns_uart: Handle to the cdns_uart330 * @enable: Value to be set to RTS/GPIO331 */332static void cdns_rts_gpio_enable(struct cdns_uart *cdns_uart, bool enable)333{334 u32 val;335 336 if (cdns_uart->gpiod_rts) {337 gpiod_set_value(cdns_uart->gpiod_rts, enable);338 } else {339 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR);340 if (enable)341 val |= CDNS_UART_MODEMCR_RTS;342 else343 val &= ~CDNS_UART_MODEMCR_RTS;344 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);345 }346}347 348/**349 * cdns_rs485_tx_setup - Tx setup specific to rs485350 * @cdns_uart: Handle to the cdns_uart351 */352static void cdns_rs485_tx_setup(struct cdns_uart *cdns_uart)353{354 bool enable;355 356 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_ON_SEND;357 cdns_rts_gpio_enable(cdns_uart, enable);358 359 cdns_uart->rs485_tx_started = true;360}361 362/**363 * cdns_rs485_rx_setup - Rx setup specific to rs485364 * @cdns_uart: Handle to the cdns_uart365 */366static void cdns_rs485_rx_setup(struct cdns_uart *cdns_uart)367{368 bool enable;369 370 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_AFTER_SEND;371 cdns_rts_gpio_enable(cdns_uart, enable);372 373 cdns_uart->rs485_tx_started = false;374}375 376/**377 * cdns_uart_tx_empty - Check whether TX is empty378 * @port: Handle to the uart port structure379 *380 * Return: TIOCSER_TEMT on success, 0 otherwise381 */382static unsigned int cdns_uart_tx_empty(struct uart_port *port)383{384 unsigned int status;385 386 status = readl(port->membase + CDNS_UART_SR);387 status &= (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);388 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;389}390 391/**392 * cdns_rs485_rx_callback - Timer rx callback handler for rs485.393 * @t: Handle to the hrtimer structure394 */395static enum hrtimer_restart cdns_rs485_rx_callback(struct hrtimer *t)396{397 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);398 399 /*400 * Default Rx should be setup, because Rx signaling path401 * need to enable to receive data.402 */403 cdns_rs485_rx_setup(cdns_uart);404 405 return HRTIMER_NORESTART;406}407 408/**409 * cdns_calc_after_tx_delay - calculate delay required for after tx.410 * @cdns_uart: Handle to the cdns_uart411 */412static u64 cdns_calc_after_tx_delay(struct cdns_uart *cdns_uart)413{414 /*415 * Frame time + stop bit time + rs485.delay_rts_after_send416 */417 return cdns_uart->port->frame_time418 + DIV_ROUND_UP(cdns_uart->port->frame_time, 7)419 + (u64)cdns_uart->port->rs485.delay_rts_after_send * NSEC_PER_MSEC;420}421 422/**423 * cdns_uart_handle_tx - Handle the bytes to be transmitted.424 * @dev_id: Id of the UART port425 * Return: None426 */427static void cdns_uart_handle_tx(void *dev_id)428{429 struct uart_port *port = (struct uart_port *)dev_id;430 struct cdns_uart *cdns_uart = port->private_data;431 struct tty_port *tport = &port->state->port;432 unsigned int numbytes;433 unsigned char ch;434 435 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {436 /* Disable the TX Empty interrupt */437 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);438 return;439 }440 441 numbytes = port->fifosize;442 while (numbytes &&443 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) &&444 uart_fifo_get(port, &ch)) {445 writel(ch, port->membase + CDNS_UART_FIFO);446 numbytes--;447 }448 449 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)450 uart_write_wakeup(port);451 452 /* Enable the TX Empty interrupt */453 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER);454 455 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED &&456 (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port))) {457 cdns_uart->tx_timer.function = &cdns_rs485_rx_callback;458 hrtimer_start(&cdns_uart->tx_timer,459 ns_to_ktime(cdns_calc_after_tx_delay(cdns_uart)), HRTIMER_MODE_REL);460 }461}462 463/**464 * cdns_uart_isr - Interrupt handler465 * @irq: Irq number466 * @dev_id: Id of the port467 *468 * Return: IRQHANDLED469 */470static irqreturn_t cdns_uart_isr(int irq, void *dev_id)471{472 struct uart_port *port = (struct uart_port *)dev_id;473 unsigned int isrstatus;474 475 uart_port_lock(port);476 477 /* Read the interrupt status register to determine which478 * interrupt(s) is/are active and clear them.479 */480 isrstatus = readl(port->membase + CDNS_UART_ISR);481 writel(isrstatus, port->membase + CDNS_UART_ISR);482 483 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {484 cdns_uart_handle_tx(dev_id);485 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;486 }487 488 isrstatus &= port->read_status_mask;489 isrstatus &= ~port->ignore_status_mask;490 /*491 * Skip RX processing if RX is disabled as RXEMPTY will never be set492 * as read bytes will not be removed from the FIFO.493 */494 if (isrstatus & CDNS_UART_IXR_RXMASK &&495 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))496 cdns_uart_handle_rx(dev_id, isrstatus);497 498 uart_port_unlock(port);499 return IRQ_HANDLED;500}501 502/**503 * cdns_uart_calc_baud_divs - Calculate baud rate divisors504 * @clk: UART module input clock505 * @baud: Desired baud rate506 * @rbdiv: BDIV value (return value)507 * @rcd: CD value (return value)508 * @div8: Value for clk_sel bit in mod (return value)509 * Return: baud rate, requested baud when possible, or actual baud when there510 * was too much error, zero if no valid divisors are found.511 *512 * Formula to obtain baud rate is513 * baud_tx/rx rate = clk/CD * (BDIV + 1)514 * input_clk = (Uart User Defined Clock or Apb Clock)515 * depends on UCLKEN in MR Reg516 * clk = input_clk or input_clk/8;517 * depends on CLKS in MR reg518 * CD and BDIV depends on values in519 * baud rate generate register520 * baud rate clock divisor register521 */522static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,523 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)524{525 u32 cd, bdiv;526 unsigned int calc_baud;527 unsigned int bestbaud = 0;528 unsigned int bauderror;529 unsigned int besterror = ~0;530 531 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {532 *div8 = 1;533 clk /= 8;534 } else {535 *div8 = 0;536 }537 538 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {539 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));540 if (cd < 1 || cd > CDNS_UART_CD_MAX)541 continue;542 543 calc_baud = clk / (cd * (bdiv + 1));544 545 if (baud > calc_baud)546 bauderror = baud - calc_baud;547 else548 bauderror = calc_baud - baud;549 550 if (besterror > bauderror) {551 *rbdiv = bdiv;552 *rcd = cd;553 bestbaud = calc_baud;554 besterror = bauderror;555 }556 }557 /* use the values when percent error is acceptable */558 if (((besterror * 100) / baud) < 3)559 bestbaud = baud;560 561 return bestbaud;562}563 564/**565 * cdns_uart_set_baud_rate - Calculate and set the baud rate566 * @port: Handle to the uart port structure567 * @baud: Baud rate to set568 * Return: baud rate, requested baud when possible, or actual baud when there569 * was too much error, zero if no valid divisors are found.570 */571static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,572 unsigned int baud)573{574 unsigned int calc_baud;575 u32 cd = 0, bdiv = 0;576 u32 mreg;577 int div8;578 struct cdns_uart *cdns_uart = port->private_data;579 580 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,581 &div8);582 583 /* Write new divisors to hardware */584 mreg = readl(port->membase + CDNS_UART_MR);585 if (div8)586 mreg |= CDNS_UART_MR_CLKSEL;587 else588 mreg &= ~CDNS_UART_MR_CLKSEL;589 writel(mreg, port->membase + CDNS_UART_MR);590 writel(cd, port->membase + CDNS_UART_BAUDGEN);591 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);592 cdns_uart->baud = baud;593 594 return calc_baud;595}596 597#ifdef CONFIG_COMMON_CLK598/**599 * cdns_uart_clk_notifier_cb - Clock notifier callback600 * @nb: Notifier block601 * @event: Notify event602 * @data: Notifier data603 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.604 */605static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,606 unsigned long event, void *data)607{608 u32 ctrl_reg;609 struct uart_port *port;610 int locked = 0;611 struct clk_notifier_data *ndata = data;612 struct cdns_uart *cdns_uart = to_cdns_uart(nb);613 unsigned long flags;614 615 port = cdns_uart->port;616 if (port->suspended)617 return NOTIFY_OK;618 619 switch (event) {620 case PRE_RATE_CHANGE:621 {622 u32 bdiv, cd;623 int div8;624 625 /*626 * Find out if current baud-rate can be achieved with new clock627 * frequency.628 */629 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,630 &bdiv, &cd, &div8)) {631 dev_warn(port->dev, "clock rate change rejected\n");632 return NOTIFY_BAD;633 }634 635 uart_port_lock_irqsave(cdns_uart->port, &flags);636 637 /* Disable the TX and RX to set baud rate */638 ctrl_reg = readl(port->membase + CDNS_UART_CR);639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;640 writel(ctrl_reg, port->membase + CDNS_UART_CR);641 642 uart_port_unlock_irqrestore(cdns_uart->port, flags);643 644 return NOTIFY_OK;645 }646 case POST_RATE_CHANGE:647 /*648 * Set clk dividers to generate correct baud with new clock649 * frequency.650 */651 652 uart_port_lock_irqsave(cdns_uart->port, &flags);653 654 locked = 1;655 port->uartclk = ndata->new_rate;656 657 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,658 cdns_uart->baud);659 fallthrough;660 case ABORT_RATE_CHANGE:661 if (!locked)662 uart_port_lock_irqsave(cdns_uart->port, &flags);663 664 /* Set TX/RX Reset */665 ctrl_reg = readl(port->membase + CDNS_UART_CR);666 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;667 writel(ctrl_reg, port->membase + CDNS_UART_CR);668 669 while (readl(port->membase + CDNS_UART_CR) &670 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))671 cpu_relax();672 673 /*674 * Clear the RX disable and TX disable bits and then set the TX675 * enable bit and RX enable bit to enable the transmitter and676 * receiver.677 */678 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);679 ctrl_reg = readl(port->membase + CDNS_UART_CR);680 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);681 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;682 writel(ctrl_reg, port->membase + CDNS_UART_CR);683 684 uart_port_unlock_irqrestore(cdns_uart->port, flags);685 686 return NOTIFY_OK;687 default:688 return NOTIFY_DONE;689 }690}691#endif692 693/**694 * cdns_rs485_tx_callback - Timer tx callback handler for rs485.695 * @t: Handle to the hrtimer structure696 */697static enum hrtimer_restart cdns_rs485_tx_callback(struct hrtimer *t)698{699 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);700 701 uart_port_lock(cdns_uart->port);702 cdns_uart_handle_tx(cdns_uart->port);703 uart_port_unlock(cdns_uart->port);704 705 return HRTIMER_NORESTART;706}707 708/**709 * cdns_uart_start_tx - Start transmitting bytes710 * @port: Handle to the uart port structure711 */712static void cdns_uart_start_tx(struct uart_port *port)713{714 unsigned int status;715 struct cdns_uart *cdns_uart = port->private_data;716 717 if (uart_tx_stopped(port))718 return;719 720 /*721 * Set the TX enable bit and clear the TX disable bit to enable the722 * transmitter.723 */724 status = readl(port->membase + CDNS_UART_CR);725 status &= ~CDNS_UART_CR_TX_DIS;726 status |= CDNS_UART_CR_TX_EN;727 writel(status, port->membase + CDNS_UART_CR);728 729 if (kfifo_is_empty(&port->state->port.xmit_fifo))730 return;731 732 /* Clear the TX Empty interrupt */733 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);734 735 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED) {736 if (!cdns_uart->rs485_tx_started) {737 cdns_uart->tx_timer.function = &cdns_rs485_tx_callback;738 cdns_rs485_tx_setup(cdns_uart);739 return hrtimer_start(&cdns_uart->tx_timer,740 ms_to_ktime(port->rs485.delay_rts_before_send),741 HRTIMER_MODE_REL);742 }743 }744 cdns_uart_handle_tx(port);745}746 747/**748 * cdns_uart_stop_tx - Stop TX749 * @port: Handle to the uart port structure750 */751static void cdns_uart_stop_tx(struct uart_port *port)752{753 unsigned int regval;754 struct cdns_uart *cdns_uart = port->private_data;755 756 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)757 cdns_rs485_rx_setup(cdns_uart);758 759 regval = readl(port->membase + CDNS_UART_CR);760 regval |= CDNS_UART_CR_TX_DIS;761 /* Disable the transmitter */762 writel(regval, port->membase + CDNS_UART_CR);763}764 765/**766 * cdns_uart_stop_rx - Stop RX767 * @port: Handle to the uart port structure768 */769static void cdns_uart_stop_rx(struct uart_port *port)770{771 unsigned int regval;772 773 /* Disable RX IRQs */774 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);775 776 /* Disable the receiver */777 regval = readl(port->membase + CDNS_UART_CR);778 regval |= CDNS_UART_CR_RX_DIS;779 writel(regval, port->membase + CDNS_UART_CR);780}781 782/**783 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop784 * transmitting char breaks785 * @port: Handle to the uart port structure786 * @ctl: Value based on which start or stop decision is taken787 */788static void cdns_uart_break_ctl(struct uart_port *port, int ctl)789{790 unsigned int status;791 unsigned long flags;792 793 uart_port_lock_irqsave(port, &flags);794 795 status = readl(port->membase + CDNS_UART_CR);796 797 if (ctl == -1)798 writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status),799 port->membase + CDNS_UART_CR);800 else {801 if ((status & CDNS_UART_CR_STOPBRK) == 0)802 writel(CDNS_UART_CR_STOPBRK | status,803 port->membase + CDNS_UART_CR);804 }805 uart_port_unlock_irqrestore(port, flags);806}807 808/**809 * cdns_uart_set_termios - termios operations, handling data length, parity,810 * stop bits, flow control, baud rate811 * @port: Handle to the uart port structure812 * @termios: Handle to the input termios structure813 * @old: Values of the previously saved termios structure814 */815static void cdns_uart_set_termios(struct uart_port *port,816 struct ktermios *termios,817 const struct ktermios *old)818{819 u32 cval = 0;820 unsigned int baud, minbaud, maxbaud;821 unsigned long flags;822 unsigned int ctrl_reg, mode_reg;823 824 uart_port_lock_irqsave(port, &flags);825 826 /* Disable the TX and RX to set baud rate */827 ctrl_reg = readl(port->membase + CDNS_UART_CR);828 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;829 writel(ctrl_reg, port->membase + CDNS_UART_CR);830 831 /*832 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk833 * min and max baud should be calculated here based on port->uartclk.834 * this way we get a valid baud and can safely call set_baud()835 */836 minbaud = port->uartclk /837 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);838 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);839 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);840 baud = cdns_uart_set_baud_rate(port, baud);841 if (tty_termios_baud_rate(termios))842 tty_termios_encode_baud_rate(termios, baud, baud);843 844 /* Update the per-port timeout. */845 uart_update_timeout(port, termios->c_cflag, baud);846 847 /* Set TX/RX Reset */848 ctrl_reg = readl(port->membase + CDNS_UART_CR);849 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;850 writel(ctrl_reg, port->membase + CDNS_UART_CR);851 852 while (readl(port->membase + CDNS_UART_CR) &853 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))854 cpu_relax();855 856 /*857 * Clear the RX disable and TX disable bits and then set the TX enable858 * bit and RX enable bit to enable the transmitter and receiver.859 */860 ctrl_reg = readl(port->membase + CDNS_UART_CR);861 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);862 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;863 writel(ctrl_reg, port->membase + CDNS_UART_CR);864 865 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);866 867 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |868 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;869 port->ignore_status_mask = 0;870 871 if (termios->c_iflag & INPCK)872 port->read_status_mask |= CDNS_UART_IXR_PARITY |873 CDNS_UART_IXR_FRAMING;874 875 if (termios->c_iflag & IGNPAR)876 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |877 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;878 879 /* ignore all characters if CREAD is not set */880 if ((termios->c_cflag & CREAD) == 0)881 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |882 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |883 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;884 885 mode_reg = readl(port->membase + CDNS_UART_MR);886 887 /* Handling Data Size */888 switch (termios->c_cflag & CSIZE) {889 case CS6:890 cval |= CDNS_UART_MR_CHARLEN_6_BIT;891 break;892 case CS7:893 cval |= CDNS_UART_MR_CHARLEN_7_BIT;894 break;895 default:896 case CS8:897 cval |= CDNS_UART_MR_CHARLEN_8_BIT;898 termios->c_cflag &= ~CSIZE;899 termios->c_cflag |= CS8;900 break;901 }902 903 /* Handling Parity and Stop Bits length */904 if (termios->c_cflag & CSTOPB)905 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */906 else907 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */908 909 if (termios->c_cflag & PARENB) {910 /* Mark or Space parity */911 if (termios->c_cflag & CMSPAR) {912 if (termios->c_cflag & PARODD)913 cval |= CDNS_UART_MR_PARITY_MARK;914 else915 cval |= CDNS_UART_MR_PARITY_SPACE;916 } else {917 if (termios->c_cflag & PARODD)918 cval |= CDNS_UART_MR_PARITY_ODD;919 else920 cval |= CDNS_UART_MR_PARITY_EVEN;921 }922 } else {923 cval |= CDNS_UART_MR_PARITY_NONE;924 }925 cval |= mode_reg & 1;926 writel(cval, port->membase + CDNS_UART_MR);927 928 cval = readl(port->membase + CDNS_UART_MODEMCR);929 if (termios->c_cflag & CRTSCTS)930 cval |= CDNS_UART_MODEMCR_FCM;931 else932 cval &= ~CDNS_UART_MODEMCR_FCM;933 writel(cval, port->membase + CDNS_UART_MODEMCR);934 935 uart_port_unlock_irqrestore(port, flags);936}937 938/**939 * cdns_uart_startup - Called when an application opens a cdns_uart port940 * @port: Handle to the uart port structure941 *942 * Return: 0 on success, negative errno otherwise943 */944static int cdns_uart_startup(struct uart_port *port)945{946 struct cdns_uart *cdns_uart = port->private_data;947 bool is_brk_support;948 int ret;949 unsigned long flags;950 unsigned int status = 0;951 952 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;953 954 ret = reset_control_deassert(cdns_uart->rstc);955 if (ret)956 return ret;957 958 uart_port_lock_irqsave(port, &flags);959 960 /* Disable the TX and RX */961 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,962 port->membase + CDNS_UART_CR);963 964 /* Set the Control Register with TX/RX Enable, TX/RX Reset,965 * no break chars.966 */967 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,968 port->membase + CDNS_UART_CR);969 970 while (readl(port->membase + CDNS_UART_CR) &971 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))972 cpu_relax();973 974 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)975 cdns_rs485_rx_setup(cdns_uart);976 977 /*978 * Clear the RX disable bit and then set the RX enable bit to enable979 * the receiver.980 */981 status = readl(port->membase + CDNS_UART_CR);982 status &= ~CDNS_UART_CR_RX_DIS;983 status |= CDNS_UART_CR_RX_EN;984 writel(status, port->membase + CDNS_UART_CR);985 986 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,987 * no parity.988 */989 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT990 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,991 port->membase + CDNS_UART_MR);992 993 /*994 * Set the RX FIFO Trigger level to use most of the FIFO, but it995 * can be tuned with a module parameter996 */997 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);998 999 /*1000 * Receive Timeout register is enabled but it1001 * can be tuned with a module parameter1002 */1003 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);1004 1005 /* Clear out any pending interrupts before enabling them */1006 writel(readl(port->membase + CDNS_UART_ISR),1007 port->membase + CDNS_UART_ISR);1008 1009 uart_port_unlock_irqrestore(port, flags);1010 1011 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);1012 if (ret) {1013 dev_err(port->dev, "request_irq '%d' failed with %d\n",1014 port->irq, ret);1015 return ret;1016 }1017 1018 /* Set the Interrupt Registers with desired interrupts */1019 if (is_brk_support)1020 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,1021 port->membase + CDNS_UART_IER);1022 else1023 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);1024 1025 return 0;1026}1027 1028/**1029 * cdns_uart_shutdown - Called when an application closes a cdns_uart port1030 * @port: Handle to the uart port structure1031 */1032static void cdns_uart_shutdown(struct uart_port *port)1033{1034 int status;1035 unsigned long flags;1036 struct cdns_uart *cdns_uart = port->private_data;1037 1038 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)1039 hrtimer_cancel(&cdns_uart->tx_timer);1040 1041 uart_port_lock_irqsave(port, &flags);1042 1043 /* Disable interrupts */1044 status = readl(port->membase + CDNS_UART_IMR);1045 writel(status, port->membase + CDNS_UART_IDR);1046 writel(0xffffffff, port->membase + CDNS_UART_ISR);1047 1048 /* Disable the TX and RX */1049 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,1050 port->membase + CDNS_UART_CR);1051 1052 uart_port_unlock_irqrestore(port, flags);1053 1054 free_irq(port->irq, port);1055}1056 1057/**1058 * cdns_uart_type - Set UART type to cdns_uart port1059 * @port: Handle to the uart port structure1060 *1061 * Return: string on success, NULL otherwise1062 */1063static const char *cdns_uart_type(struct uart_port *port)1064{1065 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;1066}1067 1068/**1069 * cdns_uart_verify_port - Verify the port params1070 * @port: Handle to the uart port structure1071 * @ser: Handle to the structure whose members are compared1072 *1073 * Return: 0 on success, negative errno otherwise.1074 */1075static int cdns_uart_verify_port(struct uart_port *port,1076 struct serial_struct *ser)1077{1078 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)1079 return -EINVAL;1080 if (port->irq != ser->irq)1081 return -EINVAL;1082 if (ser->io_type != UPIO_MEM)1083 return -EINVAL;1084 if (port->iobase != ser->port)1085 return -EINVAL;1086 if (ser->hub6 != 0)1087 return -EINVAL;1088 return 0;1089}1090 1091/**1092 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,1093 * called when the driver adds a cdns_uart port via1094 * uart_add_one_port()1095 * @port: Handle to the uart port structure1096 *1097 * Return: 0 on success, negative errno otherwise.1098 */1099static int cdns_uart_request_port(struct uart_port *port)1100{1101 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,1102 CDNS_UART_NAME)) {1103 return -ENOMEM;1104 }1105 1106 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);1107 if (!port->membase) {1108 dev_err(port->dev, "Unable to map registers\n");1109 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);1110 return -ENOMEM;1111 }1112 return 0;1113}1114 1115/**1116 * cdns_uart_release_port - Release UART port1117 * @port: Handle to the uart port structure1118 *1119 * Release the memory region attached to a cdns_uart port. Called when the1120 * driver removes a cdns_uart port via uart_remove_one_port().1121 */1122static void cdns_uart_release_port(struct uart_port *port)1123{1124 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);1125 iounmap(port->membase);1126 port->membase = NULL;1127}1128 1129/**1130 * cdns_uart_config_port - Configure UART port1131 * @port: Handle to the uart port structure1132 * @flags: If any1133 */1134static void cdns_uart_config_port(struct uart_port *port, int flags)1135{1136 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)1137 port->type = PORT_XUARTPS;1138}1139 1140/**1141 * cdns_uart_get_mctrl - Get the modem control state1142 * @port: Handle to the uart port structure1143 *1144 * Return: the modem control state1145 */1146static unsigned int cdns_uart_get_mctrl(struct uart_port *port)1147{1148 u32 val;1149 unsigned int mctrl = 0;1150 struct cdns_uart *cdns_uart_data = port->private_data;1151 1152 if (cdns_uart_data->cts_override)1153 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;1154 1155 val = readl(port->membase + CDNS_UART_MODEMSR);1156 if (val & CDNS_UART_MODEMSR_CTS)1157 mctrl |= TIOCM_CTS;1158 if (val & CDNS_UART_MODEMSR_DSR)1159 mctrl |= TIOCM_DSR;1160 if (val & CDNS_UART_MODEMSR_RI)1161 mctrl |= TIOCM_RNG;1162 if (val & CDNS_UART_MODEMSR_DCD)1163 mctrl |= TIOCM_CAR;1164 1165 return mctrl;1166}1167 1168static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)1169{1170 u32 val;1171 u32 mode_reg;1172 struct cdns_uart *cdns_uart_data = port->private_data;1173 1174 if (cdns_uart_data->cts_override)1175 return;1176 1177 val = readl(port->membase + CDNS_UART_MODEMCR);1178 mode_reg = readl(port->membase + CDNS_UART_MR);1179 1180 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);1181 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;1182 1183 if (mctrl & TIOCM_RTS)1184 val |= CDNS_UART_MODEMCR_RTS;1185 if (cdns_uart_data->gpiod_rts)1186 gpiod_set_value(cdns_uart_data->gpiod_rts, !(mctrl & TIOCM_RTS));1187 if (mctrl & TIOCM_DTR)1188 val |= CDNS_UART_MODEMCR_DTR;1189 if (mctrl & TIOCM_LOOP)1190 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;1191 else1192 mode_reg |= CDNS_UART_MR_CHMODE_NORM;1193 1194 writel(val, port->membase + CDNS_UART_MODEMCR);1195 writel(mode_reg, port->membase + CDNS_UART_MR);1196}1197 1198#ifdef CONFIG_CONSOLE_POLL1199static int cdns_uart_poll_get_char(struct uart_port *port)1200{1201 int c;1202 unsigned long flags;1203 1204 uart_port_lock_irqsave(port, &flags);1205 1206 /* Check if FIFO is empty */1207 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)1208 c = NO_POLL_CHAR;1209 else /* Read a character */1210 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);1211 1212 uart_port_unlock_irqrestore(port, flags);1213 1214 return c;1215}1216 1217static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)1218{1219 unsigned long flags;1220 1221 uart_port_lock_irqsave(port, &flags);1222 1223 /* Wait until FIFO is empty */1224 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))1225 cpu_relax();1226 1227 /* Write a character */1228 writel(c, port->membase + CDNS_UART_FIFO);1229 1230 /* Wait until FIFO is empty */1231 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))1232 cpu_relax();1233 1234 uart_port_unlock_irqrestore(port, flags);1235}1236#endif1237 1238static void cdns_uart_pm(struct uart_port *port, unsigned int state,1239 unsigned int oldstate)1240{1241 switch (state) {1242 case UART_PM_STATE_OFF:1243 pm_runtime_mark_last_busy(port->dev);1244 pm_runtime_put_autosuspend(port->dev);1245 break;1246 default:1247 pm_runtime_get_sync(port->dev);1248 break;1249 }1250}1251 1252static const struct uart_ops cdns_uart_ops = {1253 .set_mctrl = cdns_uart_set_mctrl,1254 .get_mctrl = cdns_uart_get_mctrl,1255 .start_tx = cdns_uart_start_tx,1256 .stop_tx = cdns_uart_stop_tx,1257 .stop_rx = cdns_uart_stop_rx,1258 .tx_empty = cdns_uart_tx_empty,1259 .break_ctl = cdns_uart_break_ctl,1260 .set_termios = cdns_uart_set_termios,1261 .startup = cdns_uart_startup,1262 .shutdown = cdns_uart_shutdown,1263 .pm = cdns_uart_pm,1264 .type = cdns_uart_type,1265 .verify_port = cdns_uart_verify_port,1266 .request_port = cdns_uart_request_port,1267 .release_port = cdns_uart_release_port,1268 .config_port = cdns_uart_config_port,1269#ifdef CONFIG_CONSOLE_POLL1270 .poll_get_char = cdns_uart_poll_get_char,1271 .poll_put_char = cdns_uart_poll_put_char,1272#endif1273};1274 1275static struct uart_driver cdns_uart_uart_driver;1276 1277#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE1278/**1279 * cdns_uart_console_putchar - write the character to the FIFO buffer1280 * @port: Handle to the uart port structure1281 * @ch: Character to be written1282 */1283static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch)1284{1285 unsigned int ctrl_reg;1286 unsigned long timeout;1287 1288 timeout = jiffies + msecs_to_jiffies(1000);1289 while (1) {1290 ctrl_reg = readl(port->membase + CDNS_UART_CR);1291 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))1292 break;1293 if (time_after(jiffies, timeout)) {1294 dev_warn(port->dev,1295 "timeout waiting for Enable\n");1296 return;1297 }1298 cpu_relax();1299 }1300 1301 timeout = jiffies + msecs_to_jiffies(1000);1302 while (1) {1303 ctrl_reg = readl(port->membase + CDNS_UART_SR);1304 1305 if (!(ctrl_reg & CDNS_UART_SR_TXFULL))1306 break;1307 if (time_after(jiffies, timeout)) {1308 dev_warn(port->dev,1309 "timeout waiting for TX fifo\n");1310 return;1311 }1312 cpu_relax();1313 }1314 writel(ch, port->membase + CDNS_UART_FIFO);1315}1316 1317static void cdns_early_write(struct console *con, const char *s,1318 unsigned int n)1319{1320 struct earlycon_device *dev = con->data;1321 1322 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);1323}1324 1325static int __init cdns_early_console_setup(struct earlycon_device *device,1326 const char *opt)1327{1328 struct uart_port *port = &device->port;1329 1330 if (!port->membase)1331 return -ENODEV;1332 1333 /* initialise control register */1334 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,1335 port->membase + CDNS_UART_CR);1336 1337 /* only set baud if specified on command line - otherwise1338 * assume it has been initialized by a boot loader.1339 */1340 if (port->uartclk && device->baud) {1341 u32 cd = 0, bdiv = 0;1342 u32 mr;1343 int div8;1344 1345 cdns_uart_calc_baud_divs(port->uartclk, device->baud,1346 &bdiv, &cd, &div8);1347 mr = CDNS_UART_MR_PARITY_NONE;1348 if (div8)1349 mr |= CDNS_UART_MR_CLKSEL;1350 1351 writel(mr, port->membase + CDNS_UART_MR);1352 writel(cd, port->membase + CDNS_UART_BAUDGEN);1353 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);1354 }1355 1356 device->con->write = cdns_early_write;1357 1358 return 0;1359}1360OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);1361OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);1362OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);1363OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);1364 1365 1366/* Static pointer to console port */1367static struct uart_port *console_port;1368 1369/**1370 * cdns_uart_console_write - perform write operation1371 * @co: Console handle1372 * @s: Pointer to character array1373 * @count: No of characters1374 */1375static void cdns_uart_console_write(struct console *co, const char *s,1376 unsigned int count)1377{1378 struct uart_port *port = console_port;1379 unsigned long flags;1380 unsigned int imr, ctrl;1381 int locked = 1;1382 1383 if (port->sysrq)1384 locked = 0;1385 else if (oops_in_progress)1386 locked = uart_port_trylock_irqsave(port, &flags);1387 else1388 uart_port_lock_irqsave(port, &flags);1389 1390 /* save and disable interrupt */1391 imr = readl(port->membase + CDNS_UART_IMR);1392 writel(imr, port->membase + CDNS_UART_IDR);1393 1394 /*1395 * Make sure that the tx part is enabled. Set the TX enable bit and1396 * clear the TX disable bit to enable the transmitter.1397 */1398 ctrl = readl(port->membase + CDNS_UART_CR);1399 ctrl &= ~CDNS_UART_CR_TX_DIS;1400 ctrl |= CDNS_UART_CR_TX_EN;1401 writel(ctrl, port->membase + CDNS_UART_CR);1402 1403 uart_console_write(port, s, count, cdns_uart_console_putchar);1404 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)1405 cpu_relax();1406 1407 /* restore interrupt state */1408 writel(imr, port->membase + CDNS_UART_IER);1409 1410 if (locked)1411 uart_port_unlock_irqrestore(port, flags);1412}1413 1414/**1415 * cdns_uart_console_setup - Initialize the uart to default config1416 * @co: Console handle1417 * @options: Initial settings of uart1418 *1419 * Return: 0 on success, negative errno otherwise.1420 */1421static int cdns_uart_console_setup(struct console *co, char *options)1422{1423 struct uart_port *port = console_port;1424 1425 int baud = 9600;1426 int bits = 8;1427 int parity = 'n';1428 int flow = 'n';1429 unsigned long time_out;1430 1431 if (!port->membase) {1432 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",1433 co->index);1434 return -ENODEV;1435 }1436 1437 if (options)1438 uart_parse_options(options, &baud, &parity, &bits, &flow);1439 1440 /* Wait for tx_empty before setting up the console */1441 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);1442 1443 while (time_before(jiffies, time_out) &&1444 cdns_uart_tx_empty(port) != TIOCSER_TEMT)1445 cpu_relax();1446 1447 return uart_set_options(port, co, baud, parity, bits, flow);1448}1449 1450static struct console cdns_uart_console = {1451 .name = CDNS_UART_TTY_NAME,1452 .write = cdns_uart_console_write,1453 .device = uart_console_device,1454 .setup = cdns_uart_console_setup,1455 .flags = CON_PRINTBUFFER,1456 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */1457 .data = &cdns_uart_uart_driver,1458};1459#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */1460 1461#ifdef CONFIG_PM_SLEEP1462/**1463 * cdns_uart_suspend - suspend event1464 * @device: Pointer to the device structure1465 *1466 * Return: 01467 */1468static int cdns_uart_suspend(struct device *device)1469{1470 struct uart_port *port = dev_get_drvdata(device);1471 struct cdns_uart *cdns_uart = port->private_data;1472 int may_wake;1473 1474 may_wake = device_may_wakeup(device);1475 1476 if (console_suspend_enabled && uart_console(port) && may_wake) {1477 unsigned long flags;1478 1479 uart_port_lock_irqsave(port, &flags);1480 /* Empty the receive FIFO 1st before making changes */1481 while (!(readl(port->membase + CDNS_UART_SR) &1482 CDNS_UART_SR_RXEMPTY))1483 readl(port->membase + CDNS_UART_FIFO);1484 /* set RX trigger level to 1 */1485 writel(1, port->membase + CDNS_UART_RXWM);1486 /* disable RX timeout interrups */1487 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);1488 uart_port_unlock_irqrestore(port, flags);1489 }1490 1491 /*1492 * Call the API provided in serial_core.c file which handles1493 * the suspend.1494 */1495 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);1496}1497 1498/**1499 * cdns_uart_resume - Resume after a previous suspend1500 * @device: Pointer to the device structure1501 *1502 * Return: 01503 */1504static int cdns_uart_resume(struct device *device)1505{1506 struct uart_port *port = dev_get_drvdata(device);1507 struct cdns_uart *cdns_uart = port->private_data;1508 unsigned long flags;1509 u32 ctrl_reg;1510 int may_wake;1511 int ret;1512 1513 may_wake = device_may_wakeup(device);1514 1515 if (console_suspend_enabled && uart_console(port) && !may_wake) {1516 ret = clk_enable(cdns_uart->pclk);1517 if (ret)1518 return ret;1519 1520 ret = clk_enable(cdns_uart->uartclk);1521 if (ret) {1522 clk_disable(cdns_uart->pclk);1523 return ret;1524 }1525 1526 uart_port_lock_irqsave(port, &flags);1527 1528 /* Set TX/RX Reset */1529 ctrl_reg = readl(port->membase + CDNS_UART_CR);1530 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;1531 writel(ctrl_reg, port->membase + CDNS_UART_CR);1532 while (readl(port->membase + CDNS_UART_CR) &1533 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))1534 cpu_relax();1535 1536 /* restore rx timeout value */1537 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);1538 /* Enable Tx/Rx */1539 ctrl_reg = readl(port->membase + CDNS_UART_CR);1540 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);1541 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;1542 writel(ctrl_reg, port->membase + CDNS_UART_CR);1543 1544 clk_disable(cdns_uart->uartclk);1545 clk_disable(cdns_uart->pclk);1546 uart_port_unlock_irqrestore(port, flags);1547 } else {1548 uart_port_lock_irqsave(port, &flags);1549 /* restore original rx trigger level */1550 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);1551 /* enable RX timeout interrupt */1552 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);1553 uart_port_unlock_irqrestore(port, flags);1554 }1555 1556 return uart_resume_port(cdns_uart->cdns_uart_driver, port);1557}1558#endif /* ! CONFIG_PM_SLEEP */1559static int __maybe_unused cdns_runtime_suspend(struct device *dev)1560{1561 struct uart_port *port = dev_get_drvdata(dev);1562 struct cdns_uart *cdns_uart = port->private_data;1563 1564 clk_disable(cdns_uart->uartclk);1565 clk_disable(cdns_uart->pclk);1566 return 0;1567};1568 1569static int __maybe_unused cdns_runtime_resume(struct device *dev)1570{1571 struct uart_port *port = dev_get_drvdata(dev);1572 struct cdns_uart *cdns_uart = port->private_data;1573 int ret;1574 1575 ret = clk_enable(cdns_uart->pclk);1576 if (ret)1577 return ret;1578 1579 ret = clk_enable(cdns_uart->uartclk);1580 if (ret) {1581 clk_disable(cdns_uart->pclk);1582 return ret;1583 }1584 return 0;1585};1586 1587static const struct dev_pm_ops cdns_uart_dev_pm_ops = {1588 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)1589 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,1590 cdns_runtime_resume, NULL)1591};1592 1593static const struct cdns_platform_data zynqmp_uart_def = {1594 .quirks = CDNS_UART_RXBS_SUPPORT, };1595 1596/* Match table for of_platform binding */1597static const struct of_device_id cdns_uart_of_match[] = {1598 { .compatible = "xlnx,xuartps", },1599 { .compatible = "cdns,uart-r1p8", },1600 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },1601 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },1602 {}1603};1604MODULE_DEVICE_TABLE(of, cdns_uart_of_match);1605 1606/* Temporary variable for storing number of instances */1607static int instances;1608 1609/**1610 * cdns_rs485_config - Called when an application calls TIOCSRS485 ioctl.1611 * @port: Pointer to the uart_port structure1612 * @termios: Pointer to the ktermios structure1613 * @rs485: Pointer to the serial_rs485 structure1614 *1615 * Return: 01616 */1617static int cdns_rs485_config(struct uart_port *port, struct ktermios *termios,1618 struct serial_rs485 *rs485)1619{1620 u32 val;1621 struct cdns_uart *cdns_uart = port->private_data;1622 1623 if (rs485->flags & SER_RS485_ENABLED) {1624 dev_dbg(port->dev, "Setting UART to RS485\n");1625 /* Make sure auto RTS is disabled */1626 val = readl(port->membase + CDNS_UART_MODEMCR);1627 val &= ~CDNS_UART_MODEMCR_FCM;1628 writel(val, port->membase + CDNS_UART_MODEMCR);1629 1630 /* Timer setup */1631 hrtimer_init(&cdns_uart->tx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);1632 cdns_uart->tx_timer.function = &cdns_rs485_tx_callback;1633 1634 /* Disable transmitter and make Rx setup*/1635 cdns_uart_stop_tx(port);1636 } else {1637 hrtimer_cancel(&cdns_uart->tx_timer);1638 }1639 return 0;1640}1641 1642/**1643 * cdns_uart_probe - Platform driver probe1644 * @pdev: Pointer to the platform device structure1645 *1646 * Return: 0 on success, negative errno otherwise1647 */1648static int cdns_uart_probe(struct platform_device *pdev)1649{1650 int rc, id, irq;1651 struct uart_port *port;1652 struct resource *res;1653 struct cdns_uart *cdns_uart_data;1654 const struct of_device_id *match;1655 1656 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),1657 GFP_KERNEL);1658 if (!cdns_uart_data)1659 return -ENOMEM;1660 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);1661 if (!port)1662 return -ENOMEM;1663 1664 /* Look for a serialN alias */1665 id = of_alias_get_id(pdev->dev.of_node, "serial");1666 if (id < 0)1667 id = 0;1668 1669 if (id >= CDNS_UART_NR_PORTS) {1670 dev_err(&pdev->dev, "Cannot get uart_port structure\n");1671 return -ENODEV;1672 }1673 1674 if (!cdns_uart_uart_driver.state) {1675 cdns_uart_uart_driver.owner = THIS_MODULE;1676 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;1677 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;1678 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;1679 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;1680 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;1681#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE1682 cdns_uart_uart_driver.cons = &cdns_uart_console;1683#endif1684 1685 rc = uart_register_driver(&cdns_uart_uart_driver);1686 if (rc < 0) {1687 dev_err(&pdev->dev, "Failed to register driver\n");1688 return rc;1689 }1690 }1691 1692 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;1693 1694 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);1695 if (match && match->data) {1696 const struct cdns_platform_data *data = match->data;1697 1698 cdns_uart_data->quirks = data->quirks;1699 }1700 1701 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");1702 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {1703 rc = PTR_ERR(cdns_uart_data->pclk);1704 goto err_out_unregister_driver;1705 }1706 1707 if (IS_ERR(cdns_uart_data->pclk)) {1708 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");1709 if (IS_ERR(cdns_uart_data->pclk)) {1710 rc = PTR_ERR(cdns_uart_data->pclk);1711 goto err_out_unregister_driver;1712 }1713 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");1714 }1715 1716 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");1717 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {1718 rc = PTR_ERR(cdns_uart_data->uartclk);1719 goto err_out_unregister_driver;1720 }1721 1722 if (IS_ERR(cdns_uart_data->uartclk)) {1723 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");1724 if (IS_ERR(cdns_uart_data->uartclk)) {1725 rc = PTR_ERR(cdns_uart_data->uartclk);1726 goto err_out_unregister_driver;1727 }1728 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");1729 }1730 1731 cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);1732 if (IS_ERR(cdns_uart_data->rstc)) {1733 rc = PTR_ERR(cdns_uart_data->rstc);1734 dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");1735 goto err_out_unregister_driver;1736 }1737 1738 rc = clk_prepare_enable(cdns_uart_data->pclk);1739 if (rc) {1740 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");1741 goto err_out_unregister_driver;1742 }1743 rc = clk_prepare_enable(cdns_uart_data->uartclk);1744 if (rc) {1745 dev_err(&pdev->dev, "Unable to enable device clock.\n");1746 goto err_out_clk_dis_pclk;1747 }1748 1749 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);1750 if (!res) {1751 rc = -ENODEV;1752 goto err_out_clk_disable;1753 }1754 1755 irq = platform_get_irq(pdev, 0);1756 if (irq < 0) {1757 rc = irq;1758 goto err_out_clk_disable;1759 }1760 1761#ifdef CONFIG_COMMON_CLK1762 cdns_uart_data->clk_rate_change_nb.notifier_call =1763 cdns_uart_clk_notifier_cb;1764 if (clk_notifier_register(cdns_uart_data->uartclk,1765 &cdns_uart_data->clk_rate_change_nb))1766 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");1767#endif1768 1769 /* At this point, we've got an empty uart_port struct, initialize it */1770 spin_lock_init(&port->lock);1771 port->type = PORT_UNKNOWN;1772 port->iotype = UPIO_MEM32;1773 port->flags = UPF_BOOT_AUTOCONF;1774 port->ops = &cdns_uart_ops;1775 port->fifosize = CDNS_UART_FIFO_SIZE;1776 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);1777 port->line = id;1778 1779 /*1780 * Register the port.1781 * This function also registers this device with the tty layer1782 * and triggers invocation of the config_port() entry point.1783 */1784 port->mapbase = res->start;1785 port->irq = irq;1786 port->dev = &pdev->dev;1787 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);1788 port->private_data = cdns_uart_data;1789 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |1790 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;1791 port->rs485_config = cdns_rs485_config;1792 port->rs485_supported = cdns_rs485_supported;1793 cdns_uart_data->port = port;1794 platform_set_drvdata(pdev, port);1795 1796 rc = uart_get_rs485_mode(port);1797 if (rc)1798 goto err_out_clk_notifier;1799 1800 cdns_uart_data->gpiod_rts = devm_gpiod_get_optional(&pdev->dev, "rts",1801 GPIOD_OUT_LOW);1802 if (IS_ERR(cdns_uart_data->gpiod_rts)) {1803 rc = PTR_ERR(cdns_uart_data->gpiod_rts);1804 dev_err(port->dev, "xuartps: devm_gpiod_get_optional failed\n");1805 goto err_out_clk_notifier;1806 }1807 1808 pm_runtime_use_autosuspend(&pdev->dev);1809 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);1810 pm_runtime_set_active(&pdev->dev);1811 pm_runtime_enable(&pdev->dev);1812 device_init_wakeup(port->dev, true);1813 1814#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE1815 /*1816 * If console hasn't been found yet try to assign this port1817 * because it is required to be assigned for console setup function.1818 * If register_console() don't assign value, then console_port pointer1819 * is cleanup.1820 */1821 if (!console_port) {1822 cdns_uart_console.index = id;1823 console_port = port;1824 }1825#endif1826 if (cdns_uart_data->port->rs485.flags & SER_RS485_ENABLED)1827 cdns_rs485_rx_setup(cdns_uart_data);1828 1829 rc = uart_add_one_port(&cdns_uart_uart_driver, port);1830 if (rc) {1831 dev_err(&pdev->dev,1832 "uart_add_one_port() failed; err=%i\n", rc);1833 goto err_out_pm_disable;1834 }1835 1836#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE1837 /* This is not port which is used for console that's why clean it up */1838 if (console_port == port &&1839 !console_is_registered(cdns_uart_uart_driver.cons)) {1840 console_port = NULL;1841 cdns_uart_console.index = -1;1842 }1843#endif1844 1845 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,1846 "cts-override");1847 1848 instances++;1849 1850 return 0;1851 1852err_out_pm_disable:1853 pm_runtime_disable(&pdev->dev);1854 pm_runtime_set_suspended(&pdev->dev);1855 pm_runtime_dont_use_autosuspend(&pdev->dev);1856err_out_clk_notifier:1857#ifdef CONFIG_COMMON_CLK1858 clk_notifier_unregister(cdns_uart_data->uartclk,1859 &cdns_uart_data->clk_rate_change_nb);1860#endif1861err_out_clk_disable:1862 clk_disable_unprepare(cdns_uart_data->uartclk);1863err_out_clk_dis_pclk:1864 clk_disable_unprepare(cdns_uart_data->pclk);1865err_out_unregister_driver:1866 if (!instances)1867 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);1868 return rc;1869}1870 1871/**1872 * cdns_uart_remove - called when the platform driver is unregistered1873 * @pdev: Pointer to the platform device structure1874 */1875static void cdns_uart_remove(struct platform_device *pdev)1876{1877 struct uart_port *port = platform_get_drvdata(pdev);1878 struct cdns_uart *cdns_uart_data = port->private_data;1879 1880 /* Remove the cdns_uart port from the serial core */1881#ifdef CONFIG_COMMON_CLK1882 clk_notifier_unregister(cdns_uart_data->uartclk,1883 &cdns_uart_data->clk_rate_change_nb);1884#endif1885 uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);1886 port->mapbase = 0;1887 clk_disable_unprepare(cdns_uart_data->uartclk);1888 clk_disable_unprepare(cdns_uart_data->pclk);1889 pm_runtime_disable(&pdev->dev);1890 pm_runtime_set_suspended(&pdev->dev);1891 pm_runtime_dont_use_autosuspend(&pdev->dev);1892 device_init_wakeup(&pdev->dev, false);1893 1894#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE1895 if (console_port == port)1896 console_port = NULL;1897#endif1898 reset_control_assert(cdns_uart_data->rstc);1899 1900 if (!--instances)1901 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);1902}1903 1904static struct platform_driver cdns_uart_platform_driver = {1905 .probe = cdns_uart_probe,1906 .remove_new = cdns_uart_remove,1907 .driver = {1908 .name = CDNS_UART_NAME,1909 .of_match_table = cdns_uart_of_match,1910 .pm = &cdns_uart_dev_pm_ops,1911 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),1912 },1913};1914 1915static int __init cdns_uart_init(void)1916{1917 /* Register the platform driver */1918 return platform_driver_register(&cdns_uart_platform_driver);1919}1920 1921static void __exit cdns_uart_exit(void)1922{1923 /* Unregister the platform driver */1924 platform_driver_unregister(&cdns_uart_platform_driver);1925}1926 1927arch_initcall(cdns_uart_init);1928module_exit(cdns_uart_exit);1929 1930MODULE_DESCRIPTION("Driver for Cadence UART");1931MODULE_AUTHOR("Xilinx Inc.");1932MODULE_LICENSE("GPL");1933