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1// SPDX-License-Identifier: GPL-2.02/*3 * zs.c: Serial port driver for IOASIC DECstations.4 *5 * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.6 * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.7 *8 * DECstation changes9 * Copyright (C) 1998-2000 Harald Koerfgen10 * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki11 *12 * For the rest of the code the original Copyright applies:13 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)14 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)15 *16 *17 * Note: for IOASIC systems the wiring is as follows:18 *19 * mouse/keyboard:20 * DIN-7 MJ-4 signal SCC21 * 2 1 TxD <- A.TxD22 * 3 4 RxD -> A.RxD23 *24 * EIA-232/EIA-423:25 * DB-25 MMJ-6 signal SCC26 * 2 2 TxD <- B.TxD27 * 3 5 RxD -> B.RxD28 * 4 RTS <- ~A.RTS29 * 5 CTS -> ~B.CTS30 * 6 6 DSR -> ~A.SYNC31 * 8 CD -> ~B.DCD32 * 12 DSRS(DCE) -> ~A.CTS (*)33 * 15 TxC -> B.TxC34 * 17 RxC -> B.RxC35 * 20 1 DTR <- ~A.DTR36 * 22 RI -> ~A.DCD37 * 23 DSRS(DTE) <- ~B.RTS38 *39 * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)40 * is shared with DSRS(DTE) at pin 23.41 *42 * As you can immediately notice the wiring of the RTS, DTR and DSR signals43 * is a bit odd. This makes the handling of port B unnecessarily44 * complicated and prevents the use of some automatic modes of operation.45 */46 47#include <linux/bug.h>48#include <linux/console.h>49#include <linux/delay.h>50#include <linux/errno.h>51#include <linux/init.h>52#include <linux/interrupt.h>53#include <linux/io.h>54#include <linux/ioport.h>55#include <linux/irqflags.h>56#include <linux/kernel.h>57#include <linux/module.h>58#include <linux/major.h>59#include <linux/serial.h>60#include <linux/serial_core.h>61#include <linux/spinlock.h>62#include <linux/sysrq.h>63#include <linux/tty.h>64#include <linux/tty_flip.h>65#include <linux/types.h>66 67#include <linux/atomic.h>68 69#include <asm/dec/interrupts.h>70#include <asm/dec/ioasic_addrs.h>71#include <asm/dec/system.h>72 73#include "zs.h"74 75 76MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");77MODULE_DESCRIPTION("DECstation Z85C30 serial driver");78MODULE_LICENSE("GPL");79 80 81static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";82static char zs_version[] __initdata = "0.10";83 84/*85 * It would be nice to dynamically allocate everything that86 * depends on ZS_NUM_SCCS, so we could support any number of87 * Z85C30s, but for now...88 */89#define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */90#define ZS_NUM_CHAN 2 /* 2 channels per chip. */91#define ZS_CHAN_A 0 /* Index of the channel A. */92#define ZS_CHAN_B 1 /* Index of the channel B. */93#define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */94#define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */95#define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte96 of the 16-bit IOBUS. */97#define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */98 99#define to_zport(uport) container_of(uport, struct zs_port, port)100 101struct zs_parms {102 resource_size_t scc[ZS_NUM_SCCS];103 int irq[ZS_NUM_SCCS];104};105 106static struct zs_scc zs_sccs[ZS_NUM_SCCS];107 108static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {109 0, /* write 0 */110 PAR_SPEC, /* write 1 */111 0, /* write 2 */112 0, /* write 3 */113 X16CLK | SB1, /* write 4 */114 0, /* write 5 */115 0, 0, 0, /* write 6, 7, 8 */116 MIE | DLC | NV, /* write 9 */117 NRZ, /* write 10 */118 TCBR | RCBR, /* write 11 */119 0, 0, /* BRG time constant, write 12 + 13 */120 BRSRC | BRENABL, /* write 14 */121 0, /* write 15 */122};123 124/*125 * Debugging.126 */127#undef ZS_DEBUG_REGS128 129 130/*131 * Reading and writing Z85C30 registers.132 */133static void recovery_delay(void)134{135 udelay(2);136}137 138static u8 read_zsreg(struct zs_port *zport, int reg)139{140 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;141 u8 retval;142 143 if (reg != 0) {144 writeb(reg & 0xf, control);145 fast_iob();146 recovery_delay();147 }148 retval = readb(control);149 recovery_delay();150 return retval;151}152 153static void write_zsreg(struct zs_port *zport, int reg, u8 value)154{155 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;156 157 if (reg != 0) {158 writeb(reg & 0xf, control);159 fast_iob(); recovery_delay();160 }161 writeb(value, control);162 fast_iob();163 recovery_delay();164 return;165}166 167static u8 read_zsdata(struct zs_port *zport)168{169 void __iomem *data = zport->port.membase +170 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;171 u8 retval;172 173 retval = readb(data);174 recovery_delay();175 return retval;176}177 178static void write_zsdata(struct zs_port *zport, u8 value)179{180 void __iomem *data = zport->port.membase +181 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;182 183 writeb(value, data);184 fast_iob();185 recovery_delay();186 return;187}188 189#ifdef ZS_DEBUG_REGS190void zs_dump(void)191{192 struct zs_port *zport;193 int i, j;194 195 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {196 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];197 198 if (!zport->scc)199 continue;200 201 for (j = 0; j < 16; j++)202 printk("W%-2d = 0x%02x\t", j, zport->regs[j]);203 printk("\n");204 for (j = 0; j < 16; j++)205 printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));206 printk("\n\n");207 }208}209#endif210 211 212static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)213{214 if (irq)215 spin_lock_irq(lock);216 else217 spin_lock(lock);218}219 220static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)221{222 if (irq)223 spin_unlock_irq(lock);224 else225 spin_unlock(lock);226}227 228static int zs_receive_drain(struct zs_port *zport)229{230 int loops = 10000;231 232 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)233 read_zsdata(zport);234 return loops;235}236 237static int zs_transmit_drain(struct zs_port *zport, int irq)238{239 struct zs_scc *scc = zport->scc;240 int loops = 10000;241 242 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {243 zs_spin_unlock_cond_irq(&scc->zlock, irq);244 udelay(2);245 zs_spin_lock_cond_irq(&scc->zlock, irq);246 }247 return loops;248}249 250static int zs_line_drain(struct zs_port *zport, int irq)251{252 struct zs_scc *scc = zport->scc;253 int loops = 10000;254 255 while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {256 zs_spin_unlock_cond_irq(&scc->zlock, irq);257 udelay(2);258 zs_spin_lock_cond_irq(&scc->zlock, irq);259 }260 return loops;261}262 263 264static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)265{266 /* Let the current transmission finish. */267 zs_line_drain(zport, irq);268 /* Load 'em up. */269 write_zsreg(zport, R3, regs[3] & ~RxENABLE);270 write_zsreg(zport, R5, regs[5] & ~TxENAB);271 write_zsreg(zport, R4, regs[4]);272 write_zsreg(zport, R9, regs[9]);273 write_zsreg(zport, R1, regs[1]);274 write_zsreg(zport, R2, regs[2]);275 write_zsreg(zport, R10, regs[10]);276 write_zsreg(zport, R14, regs[14] & ~BRENABL);277 write_zsreg(zport, R11, regs[11]);278 write_zsreg(zport, R12, regs[12]);279 write_zsreg(zport, R13, regs[13]);280 write_zsreg(zport, R14, regs[14]);281 write_zsreg(zport, R15, regs[15]);282 if (regs[3] & RxENABLE)283 write_zsreg(zport, R3, regs[3]);284 if (regs[5] & TxENAB)285 write_zsreg(zport, R5, regs[5]);286 return;287}288 289 290/*291 * Status handling routines.292 */293 294/*295 * zs_tx_empty() -- get the transmitter empty status296 *297 * Purpose: Let user call ioctl() to get info when the UART physically298 * is emptied. On bus types like RS485, the transmitter must299 * release the bus after transmitting. This must be done when300 * the transmit shift register is empty, not be done when the301 * transmit holding register is empty. This functionality302 * allows an RS485 driver to be written in user space.303 */304static unsigned int zs_tx_empty(struct uart_port *uport)305{306 struct zs_port *zport = to_zport(uport);307 struct zs_scc *scc = zport->scc;308 unsigned long flags;309 u8 status;310 311 spin_lock_irqsave(&scc->zlock, flags);312 status = read_zsreg(zport, R1);313 spin_unlock_irqrestore(&scc->zlock, flags);314 315 return status & ALL_SNT ? TIOCSER_TEMT : 0;316}317 318static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,319 struct zs_port *zport_b)320{321 u8 status_a, status_b;322 unsigned int mctrl;323 324 status_a = read_zsreg(zport_a, R0);325 status_b = read_zsreg(zport_b, R0);326 327 mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |328 ((status_b & DCD) ? TIOCM_CAR : 0) |329 ((status_a & DCD) ? TIOCM_RNG : 0) |330 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);331 332 return mctrl;333}334 335static unsigned int zs_raw_get_mctrl(struct zs_port *zport)336{337 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];338 339 return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;340}341 342static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)343{344 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];345 unsigned int mmask, mctrl, delta;346 u8 mask_a, mask_b;347 348 if (zport == zport_a)349 return 0;350 351 mask_a = zport_a->regs[15];352 mask_b = zport->regs[15];353 354 mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |355 ((mask_b & DCDIE) ? TIOCM_CAR : 0) |356 ((mask_a & DCDIE) ? TIOCM_RNG : 0) |357 ((mask_a & SYNCIE) ? TIOCM_DSR : 0);358 359 mctrl = zport->mctrl;360 if (mmask) {361 mctrl &= ~mmask;362 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;363 }364 365 delta = mctrl ^ zport->mctrl;366 if (delta)367 zport->mctrl = mctrl;368 369 return delta;370}371 372static unsigned int zs_get_mctrl(struct uart_port *uport)373{374 struct zs_port *zport = to_zport(uport);375 struct zs_scc *scc = zport->scc;376 unsigned int mctrl;377 378 spin_lock(&scc->zlock);379 mctrl = zs_raw_get_mctrl(zport);380 spin_unlock(&scc->zlock);381 382 return mctrl;383}384 385static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)386{387 struct zs_port *zport = to_zport(uport);388 struct zs_scc *scc = zport->scc;389 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];390 u8 oldloop, newloop;391 392 spin_lock(&scc->zlock);393 if (zport != zport_a) {394 if (mctrl & TIOCM_DTR)395 zport_a->regs[5] |= DTR;396 else397 zport_a->regs[5] &= ~DTR;398 if (mctrl & TIOCM_RTS)399 zport_a->regs[5] |= RTS;400 else401 zport_a->regs[5] &= ~RTS;402 write_zsreg(zport_a, R5, zport_a->regs[5]);403 }404 405 /* Rarely modified, so don't poke at hardware unless necessary. */406 oldloop = zport->regs[14];407 newloop = oldloop;408 if (mctrl & TIOCM_LOOP)409 newloop |= LOOPBAK;410 else411 newloop &= ~LOOPBAK;412 if (newloop != oldloop) {413 zport->regs[14] = newloop;414 write_zsreg(zport, R14, zport->regs[14]);415 }416 spin_unlock(&scc->zlock);417}418 419static void zs_raw_stop_tx(struct zs_port *zport)420{421 write_zsreg(zport, R0, RES_Tx_P);422 zport->tx_stopped = 1;423}424 425static void zs_stop_tx(struct uart_port *uport)426{427 struct zs_port *zport = to_zport(uport);428 struct zs_scc *scc = zport->scc;429 430 spin_lock(&scc->zlock);431 zs_raw_stop_tx(zport);432 spin_unlock(&scc->zlock);433}434 435static void zs_raw_transmit_chars(struct zs_port *);436 437static void zs_start_tx(struct uart_port *uport)438{439 struct zs_port *zport = to_zport(uport);440 struct zs_scc *scc = zport->scc;441 442 spin_lock(&scc->zlock);443 if (zport->tx_stopped) {444 zs_transmit_drain(zport, 0);445 zport->tx_stopped = 0;446 zs_raw_transmit_chars(zport);447 }448 spin_unlock(&scc->zlock);449}450 451static void zs_stop_rx(struct uart_port *uport)452{453 struct zs_port *zport = to_zport(uport);454 struct zs_scc *scc = zport->scc;455 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];456 457 spin_lock(&scc->zlock);458 zport->regs[15] &= ~BRKIE;459 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);460 zport->regs[1] |= RxINT_DISAB;461 462 if (zport != zport_a) {463 /* A-side DCD tracks RI and SYNC tracks DSR. */464 zport_a->regs[15] &= ~(DCDIE | SYNCIE);465 write_zsreg(zport_a, R15, zport_a->regs[15]);466 if (!(zport_a->regs[15] & BRKIE)) {467 zport_a->regs[1] &= ~EXT_INT_ENAB;468 write_zsreg(zport_a, R1, zport_a->regs[1]);469 }470 471 /* This-side DCD tracks DCD and CTS tracks CTS. */472 zport->regs[15] &= ~(DCDIE | CTSIE);473 zport->regs[1] &= ~EXT_INT_ENAB;474 } else {475 /* DCD tracks RI and SYNC tracks DSR for the B side. */476 if (!(zport->regs[15] & (DCDIE | SYNCIE)))477 zport->regs[1] &= ~EXT_INT_ENAB;478 }479 480 write_zsreg(zport, R15, zport->regs[15]);481 write_zsreg(zport, R1, zport->regs[1]);482 spin_unlock(&scc->zlock);483}484 485static void zs_enable_ms(struct uart_port *uport)486{487 struct zs_port *zport = to_zport(uport);488 struct zs_scc *scc = zport->scc;489 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];490 491 if (zport == zport_a)492 return;493 494 spin_lock(&scc->zlock);495 496 /* Clear Ext interrupts if not being handled already. */497 if (!(zport_a->regs[1] & EXT_INT_ENAB))498 write_zsreg(zport_a, R0, RES_EXT_INT);499 500 /* A-side DCD tracks RI and SYNC tracks DSR. */501 zport_a->regs[1] |= EXT_INT_ENAB;502 zport_a->regs[15] |= DCDIE | SYNCIE;503 504 /* This-side DCD tracks DCD and CTS tracks CTS. */505 zport->regs[15] |= DCDIE | CTSIE;506 507 zs_raw_xor_mctrl(zport);508 509 write_zsreg(zport_a, R1, zport_a->regs[1]);510 write_zsreg(zport_a, R15, zport_a->regs[15]);511 write_zsreg(zport, R15, zport->regs[15]);512 spin_unlock(&scc->zlock);513}514 515static void zs_break_ctl(struct uart_port *uport, int break_state)516{517 struct zs_port *zport = to_zport(uport);518 struct zs_scc *scc = zport->scc;519 unsigned long flags;520 521 spin_lock_irqsave(&scc->zlock, flags);522 if (break_state == -1)523 zport->regs[5] |= SND_BRK;524 else525 zport->regs[5] &= ~SND_BRK;526 write_zsreg(zport, R5, zport->regs[5]);527 spin_unlock_irqrestore(&scc->zlock, flags);528}529 530 531/*532 * Interrupt handling routines.533 */534#define Rx_BRK 0x0100 /* BREAK event software flag. */535#define Rx_SYS 0x0200 /* SysRq event software flag. */536 537static void zs_receive_chars(struct zs_port *zport)538{539 struct uart_port *uport = &zport->port;540 struct zs_scc *scc = zport->scc;541 struct uart_icount *icount;542 unsigned int avail, status;543 int count;544 u8 ch, flag;545 546 for (count = 16; count; count--) {547 spin_lock(&scc->zlock);548 avail = read_zsreg(zport, R0) & Rx_CH_AV;549 spin_unlock(&scc->zlock);550 if (!avail)551 break;552 553 spin_lock(&scc->zlock);554 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);555 ch = read_zsdata(zport);556 spin_unlock(&scc->zlock);557 558 flag = TTY_NORMAL;559 560 icount = &uport->icount;561 icount->rx++;562 563 /* Handle the null char got when BREAK is removed. */564 if (!ch)565 status |= zport->tty_break;566 if (unlikely(status &567 (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {568 zport->tty_break = 0;569 570 /* Reset the error indication. */571 if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {572 spin_lock(&scc->zlock);573 write_zsreg(zport, R0, ERR_RES);574 spin_unlock(&scc->zlock);575 }576 577 if (status & (Rx_SYS | Rx_BRK)) {578 icount->brk++;579 /* SysRq discards the null char. */580 if (status & Rx_SYS)581 continue;582 } else if (status & FRM_ERR)583 icount->frame++;584 else if (status & PAR_ERR)585 icount->parity++;586 if (status & Rx_OVR)587 icount->overrun++;588 589 status &= uport->read_status_mask;590 if (status & Rx_BRK)591 flag = TTY_BREAK;592 else if (status & FRM_ERR)593 flag = TTY_FRAME;594 else if (status & PAR_ERR)595 flag = TTY_PARITY;596 }597 598 if (uart_handle_sysrq_char(uport, ch))599 continue;600 601 uart_insert_char(uport, status, Rx_OVR, ch, flag);602 }603 604 tty_flip_buffer_push(&uport->state->port);605}606 607static void zs_raw_transmit_chars(struct zs_port *zport)608{609 struct tty_port *tport = &zport->port.state->port;610 unsigned char ch;611 612 /* XON/XOFF chars. */613 if (zport->port.x_char) {614 write_zsdata(zport, zport->port.x_char);615 zport->port.icount.tx++;616 zport->port.x_char = 0;617 return;618 }619 620 /* If nothing to do or stopped or hardware stopped. */621 if (uart_tx_stopped(&zport->port) ||622 !uart_fifo_get(&zport->port, &ch)) {623 zs_raw_stop_tx(zport);624 return;625 }626 627 /* Send char. */628 write_zsdata(zport, ch);629 630 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)631 uart_write_wakeup(&zport->port);632 633 /* Are we are done? */634 if (kfifo_is_empty(&tport->xmit_fifo))635 zs_raw_stop_tx(zport);636}637 638static void zs_transmit_chars(struct zs_port *zport)639{640 struct zs_scc *scc = zport->scc;641 642 spin_lock(&scc->zlock);643 zs_raw_transmit_chars(zport);644 spin_unlock(&scc->zlock);645}646 647static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)648{649 struct uart_port *uport = &zport->port;650 struct zs_scc *scc = zport->scc;651 unsigned int delta;652 u8 status, brk;653 654 spin_lock(&scc->zlock);655 656 /* Get status from Read Register 0. */657 status = read_zsreg(zport, R0);658 659 if (zport->regs[15] & BRKIE) {660 brk = status & BRK_ABRT;661 if (brk && !zport->brk) {662 spin_unlock(&scc->zlock);663 if (uart_handle_break(uport))664 zport->tty_break = Rx_SYS;665 else666 zport->tty_break = Rx_BRK;667 spin_lock(&scc->zlock);668 }669 zport->brk = brk;670 }671 672 if (zport != zport_a) {673 delta = zs_raw_xor_mctrl(zport);674 spin_unlock(&scc->zlock);675 676 if (delta & TIOCM_CTS)677 uart_handle_cts_change(uport,678 zport->mctrl & TIOCM_CTS);679 if (delta & TIOCM_CAR)680 uart_handle_dcd_change(uport,681 zport->mctrl & TIOCM_CAR);682 if (delta & TIOCM_RNG)683 uport->icount.dsr++;684 if (delta & TIOCM_DSR)685 uport->icount.rng++;686 687 if (delta)688 wake_up_interruptible(&uport->state->port.delta_msr_wait);689 690 spin_lock(&scc->zlock);691 }692 693 /* Clear the status condition... */694 write_zsreg(zport, R0, RES_EXT_INT);695 696 spin_unlock(&scc->zlock);697}698 699/*700 * This is the Z85C30 driver's generic interrupt routine.701 */702static irqreturn_t zs_interrupt(int irq, void *dev_id)703{704 struct zs_scc *scc = dev_id;705 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];706 struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];707 irqreturn_t status = IRQ_NONE;708 u8 zs_intreg;709 int count;710 711 /*712 * NOTE: The read register 3, which holds the irq status,713 * does so for both channels on each chip. Although714 * the status value itself must be read from the A715 * channel and is only valid when read from channel A.716 * Yes... broken hardware...717 */718 for (count = 16; count; count--) {719 spin_lock(&scc->zlock);720 zs_intreg = read_zsreg(zport_a, R3);721 spin_unlock(&scc->zlock);722 if (!zs_intreg)723 break;724 725 /*726 * We do not like losing characters, so we prioritise727 * interrupt sources a little bit differently than728 * the SCC would, was it allowed to.729 */730 if (zs_intreg & CHBRxIP)731 zs_receive_chars(zport_b);732 if (zs_intreg & CHARxIP)733 zs_receive_chars(zport_a);734 if (zs_intreg & CHBEXT)735 zs_status_handle(zport_b, zport_a);736 if (zs_intreg & CHAEXT)737 zs_status_handle(zport_a, zport_a);738 if (zs_intreg & CHBTxIP)739 zs_transmit_chars(zport_b);740 if (zs_intreg & CHATxIP)741 zs_transmit_chars(zport_a);742 743 status = IRQ_HANDLED;744 }745 746 return status;747}748 749 750/*751 * Finally, routines used to initialize the serial port.752 */753static int zs_startup(struct uart_port *uport)754{755 struct zs_port *zport = to_zport(uport);756 struct zs_scc *scc = zport->scc;757 unsigned long flags;758 int irq_guard;759 int ret;760 761 irq_guard = atomic_add_return(1, &scc->irq_guard);762 if (irq_guard == 1) {763 ret = request_irq(zport->port.irq, zs_interrupt,764 IRQF_SHARED, "scc", scc);765 if (ret) {766 atomic_add(-1, &scc->irq_guard);767 printk(KERN_ERR "zs: can't get irq %d\n",768 zport->port.irq);769 return ret;770 }771 }772 773 spin_lock_irqsave(&scc->zlock, flags);774 775 /* Clear the receive FIFO. */776 zs_receive_drain(zport);777 778 /* Clear the interrupt registers. */779 write_zsreg(zport, R0, ERR_RES);780 write_zsreg(zport, R0, RES_Tx_P);781 /* But Ext only if not being handled already. */782 if (!(zport->regs[1] & EXT_INT_ENAB))783 write_zsreg(zport, R0, RES_EXT_INT);784 785 /* Finally, enable sequencing and interrupts. */786 zport->regs[1] &= ~RxINT_MASK;787 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;788 zport->regs[3] |= RxENABLE;789 zport->regs[15] |= BRKIE;790 write_zsreg(zport, R1, zport->regs[1]);791 write_zsreg(zport, R3, zport->regs[3]);792 write_zsreg(zport, R5, zport->regs[5]);793 write_zsreg(zport, R15, zport->regs[15]);794 795 /* Record the current state of RR0. */796 zport->mctrl = zs_raw_get_mctrl(zport);797 zport->brk = read_zsreg(zport, R0) & BRK_ABRT;798 799 zport->tx_stopped = 1;800 801 spin_unlock_irqrestore(&scc->zlock, flags);802 803 return 0;804}805 806static void zs_shutdown(struct uart_port *uport)807{808 struct zs_port *zport = to_zport(uport);809 struct zs_scc *scc = zport->scc;810 unsigned long flags;811 int irq_guard;812 813 spin_lock_irqsave(&scc->zlock, flags);814 815 zport->regs[3] &= ~RxENABLE;816 write_zsreg(zport, R5, zport->regs[5]);817 write_zsreg(zport, R3, zport->regs[3]);818 819 spin_unlock_irqrestore(&scc->zlock, flags);820 821 irq_guard = atomic_add_return(-1, &scc->irq_guard);822 if (!irq_guard)823 free_irq(zport->port.irq, scc);824}825 826 827static void zs_reset(struct zs_port *zport)828{829 struct zs_scc *scc = zport->scc;830 int irq;831 unsigned long flags;832 833 spin_lock_irqsave(&scc->zlock, flags);834 irq = !irqs_disabled_flags(flags);835 if (!scc->initialised) {836 /* Reset the pointer first, just in case... */837 read_zsreg(zport, R0);838 /* And let the current transmission finish. */839 zs_line_drain(zport, irq);840 write_zsreg(zport, R9, FHWRES);841 udelay(10);842 write_zsreg(zport, R9, 0);843 scc->initialised = 1;844 }845 load_zsregs(zport, zport->regs, irq);846 spin_unlock_irqrestore(&scc->zlock, flags);847}848 849static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,850 const struct ktermios *old_termios)851{852 struct zs_port *zport = to_zport(uport);853 struct zs_scc *scc = zport->scc;854 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];855 int irq;856 unsigned int baud, brg;857 unsigned long flags;858 859 spin_lock_irqsave(&scc->zlock, flags);860 irq = !irqs_disabled_flags(flags);861 862 /* Byte size. */863 zport->regs[3] &= ~RxNBITS_MASK;864 zport->regs[5] &= ~TxNBITS_MASK;865 switch (termios->c_cflag & CSIZE) {866 case CS5:867 zport->regs[3] |= Rx5;868 zport->regs[5] |= Tx5;869 break;870 case CS6:871 zport->regs[3] |= Rx6;872 zport->regs[5] |= Tx6;873 break;874 case CS7:875 zport->regs[3] |= Rx7;876 zport->regs[5] |= Tx7;877 break;878 case CS8:879 default:880 zport->regs[3] |= Rx8;881 zport->regs[5] |= Tx8;882 break;883 }884 885 /* Parity and stop bits. */886 zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);887 if (termios->c_cflag & CSTOPB)888 zport->regs[4] |= SB2;889 else890 zport->regs[4] |= SB1;891 if (termios->c_cflag & PARENB)892 zport->regs[4] |= PAR_ENA;893 if (!(termios->c_cflag & PARODD))894 zport->regs[4] |= PAR_EVEN;895 switch (zport->clk_mode) {896 case 64:897 zport->regs[4] |= X64CLK;898 break;899 case 32:900 zport->regs[4] |= X32CLK;901 break;902 case 16:903 zport->regs[4] |= X16CLK;904 break;905 case 1:906 zport->regs[4] |= X1CLK;907 break;908 default:909 BUG();910 }911 912 baud = uart_get_baud_rate(uport, termios, old_termios, 0,913 uport->uartclk / zport->clk_mode / 4);914 915 brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);916 zport->regs[12] = brg & 0xff;917 zport->regs[13] = (brg >> 8) & 0xff;918 919 uart_update_timeout(uport, termios->c_cflag, baud);920 921 uport->read_status_mask = Rx_OVR;922 if (termios->c_iflag & INPCK)923 uport->read_status_mask |= FRM_ERR | PAR_ERR;924 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))925 uport->read_status_mask |= Rx_BRK;926 927 uport->ignore_status_mask = 0;928 if (termios->c_iflag & IGNPAR)929 uport->ignore_status_mask |= FRM_ERR | PAR_ERR;930 if (termios->c_iflag & IGNBRK) {931 uport->ignore_status_mask |= Rx_BRK;932 if (termios->c_iflag & IGNPAR)933 uport->ignore_status_mask |= Rx_OVR;934 }935 936 if (termios->c_cflag & CREAD)937 zport->regs[3] |= RxENABLE;938 else939 zport->regs[3] &= ~RxENABLE;940 941 if (zport != zport_a) {942 if (!(termios->c_cflag & CLOCAL)) {943 zport->regs[15] |= DCDIE;944 } else945 zport->regs[15] &= ~DCDIE;946 if (termios->c_cflag & CRTSCTS) {947 zport->regs[15] |= CTSIE;948 } else949 zport->regs[15] &= ~CTSIE;950 zs_raw_xor_mctrl(zport);951 }952 953 /* Load up the new values. */954 load_zsregs(zport, zport->regs, irq);955 956 spin_unlock_irqrestore(&scc->zlock, flags);957}958 959/*960 * Hack alert!961 * Required solely so that the initial PROM-based console962 * works undisturbed in parallel with this one.963 */964static void zs_pm(struct uart_port *uport, unsigned int state,965 unsigned int oldstate)966{967 struct zs_port *zport = to_zport(uport);968 969 if (state < 3)970 zport->regs[5] |= TxENAB;971 else972 zport->regs[5] &= ~TxENAB;973 write_zsreg(zport, R5, zport->regs[5]);974}975 976 977static const char *zs_type(struct uart_port *uport)978{979 return "Z85C30 SCC";980}981 982static void zs_release_port(struct uart_port *uport)983{984 iounmap(uport->membase);985 uport->membase = NULL;986 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);987}988 989static int zs_map_port(struct uart_port *uport)990{991 if (!uport->membase)992 uport->membase = ioremap(uport->mapbase,993 ZS_CHAN_IO_SIZE);994 if (!uport->membase) {995 printk(KERN_ERR "zs: Cannot map MMIO\n");996 return -ENOMEM;997 }998 return 0;999}1000 1001static int zs_request_port(struct uart_port *uport)1002{1003 int ret;1004 1005 if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {1006 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");1007 return -EBUSY;1008 }1009 ret = zs_map_port(uport);1010 if (ret) {1011 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);1012 return ret;1013 }1014 return 0;1015}1016 1017static void zs_config_port(struct uart_port *uport, int flags)1018{1019 struct zs_port *zport = to_zport(uport);1020 1021 if (flags & UART_CONFIG_TYPE) {1022 if (zs_request_port(uport))1023 return;1024 1025 uport->type = PORT_ZS;1026 1027 zs_reset(zport);1028 }1029}1030 1031static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)1032{1033 struct zs_port *zport = to_zport(uport);1034 int ret = 0;1035 1036 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)1037 ret = -EINVAL;1038 if (ser->irq != uport->irq)1039 ret = -EINVAL;1040 if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)1041 ret = -EINVAL;1042 return ret;1043}1044 1045 1046static const struct uart_ops zs_ops = {1047 .tx_empty = zs_tx_empty,1048 .set_mctrl = zs_set_mctrl,1049 .get_mctrl = zs_get_mctrl,1050 .stop_tx = zs_stop_tx,1051 .start_tx = zs_start_tx,1052 .stop_rx = zs_stop_rx,1053 .enable_ms = zs_enable_ms,1054 .break_ctl = zs_break_ctl,1055 .startup = zs_startup,1056 .shutdown = zs_shutdown,1057 .set_termios = zs_set_termios,1058 .pm = zs_pm,1059 .type = zs_type,1060 .release_port = zs_release_port,1061 .request_port = zs_request_port,1062 .config_port = zs_config_port,1063 .verify_port = zs_verify_port,1064};1065 1066/*1067 * Initialize Z85C30 port structures.1068 */1069static int __init zs_probe_sccs(void)1070{1071 static int probed;1072 struct zs_parms zs_parms;1073 int chip, side, irq;1074 int n_chips = 0;1075 int i;1076 1077 if (probed)1078 return 0;1079 1080 irq = dec_interrupt[DEC_IRQ_SCC0];1081 if (irq >= 0) {1082 zs_parms.scc[n_chips] = IOASIC_SCC0;1083 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];1084 n_chips++;1085 }1086 irq = dec_interrupt[DEC_IRQ_SCC1];1087 if (irq >= 0) {1088 zs_parms.scc[n_chips] = IOASIC_SCC1;1089 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];1090 n_chips++;1091 }1092 if (!n_chips)1093 return -ENXIO;1094 1095 probed = 1;1096 1097 for (chip = 0; chip < n_chips; chip++) {1098 spin_lock_init(&zs_sccs[chip].zlock);1099 for (side = 0; side < ZS_NUM_CHAN; side++) {1100 struct zs_port *zport = &zs_sccs[chip].zport[side];1101 struct uart_port *uport = &zport->port;1102 1103 zport->scc = &zs_sccs[chip];1104 zport->clk_mode = 16;1105 1106 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);1107 uport->irq = zs_parms.irq[chip];1108 uport->uartclk = ZS_CLOCK;1109 uport->fifosize = 1;1110 uport->iotype = UPIO_MEM;1111 uport->flags = UPF_BOOT_AUTOCONF;1112 uport->ops = &zs_ops;1113 uport->line = chip * ZS_NUM_CHAN + side;1114 uport->mapbase = dec_kn_slot_base +1115 zs_parms.scc[chip] +1116 (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;1117 1118 for (i = 0; i < ZS_NUM_REGS; i++)1119 zport->regs[i] = zs_init_regs[i];1120 }1121 }1122 1123 return 0;1124}1125 1126 1127#ifdef CONFIG_SERIAL_ZS_CONSOLE1128static void zs_console_putchar(struct uart_port *uport, unsigned char ch)1129{1130 struct zs_port *zport = to_zport(uport);1131 struct zs_scc *scc = zport->scc;1132 int irq;1133 unsigned long flags;1134 1135 spin_lock_irqsave(&scc->zlock, flags);1136 irq = !irqs_disabled_flags(flags);1137 if (zs_transmit_drain(zport, irq))1138 write_zsdata(zport, ch);1139 spin_unlock_irqrestore(&scc->zlock, flags);1140}1141 1142/*1143 * Print a string to the serial port trying not to disturb1144 * any possible real use of the port...1145 */1146static void zs_console_write(struct console *co, const char *s,1147 unsigned int count)1148{1149 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;1150 struct zs_port *zport = &zs_sccs[chip].zport[side];1151 struct zs_scc *scc = zport->scc;1152 unsigned long flags;1153 u8 txint, txenb;1154 int irq;1155 1156 /* Disable transmit interrupts and enable the transmitter. */1157 spin_lock_irqsave(&scc->zlock, flags);1158 txint = zport->regs[1];1159 txenb = zport->regs[5];1160 if (txint & TxINT_ENAB) {1161 zport->regs[1] = txint & ~TxINT_ENAB;1162 write_zsreg(zport, R1, zport->regs[1]);1163 }1164 if (!(txenb & TxENAB)) {1165 zport->regs[5] = txenb | TxENAB;1166 write_zsreg(zport, R5, zport->regs[5]);1167 }1168 spin_unlock_irqrestore(&scc->zlock, flags);1169 1170 uart_console_write(&zport->port, s, count, zs_console_putchar);1171 1172 /* Restore transmit interrupts and the transmitter enable. */1173 spin_lock_irqsave(&scc->zlock, flags);1174 irq = !irqs_disabled_flags(flags);1175 zs_line_drain(zport, irq);1176 if (!(txenb & TxENAB)) {1177 zport->regs[5] &= ~TxENAB;1178 write_zsreg(zport, R5, zport->regs[5]);1179 }1180 if (txint & TxINT_ENAB) {1181 zport->regs[1] |= TxINT_ENAB;1182 write_zsreg(zport, R1, zport->regs[1]);1183 1184 /* Resume any transmission as the TxIP bit won't be set. */1185 if (!zport->tx_stopped)1186 zs_raw_transmit_chars(zport);1187 }1188 spin_unlock_irqrestore(&scc->zlock, flags);1189}1190 1191/*1192 * Setup serial console baud/bits/parity. We do two things here:1193 * - construct a cflag setting for the first uart_open()1194 * - initialise the serial port1195 * Return non-zero if we didn't find a serial port.1196 */1197static int __init zs_console_setup(struct console *co, char *options)1198{1199 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;1200 struct zs_port *zport = &zs_sccs[chip].zport[side];1201 struct uart_port *uport = &zport->port;1202 int baud = 9600;1203 int bits = 8;1204 int parity = 'n';1205 int flow = 'n';1206 int ret;1207 1208 ret = zs_map_port(uport);1209 if (ret)1210 return ret;1211 1212 zs_reset(zport);1213 zs_pm(uport, 0, -1);1214 1215 if (options)1216 uart_parse_options(options, &baud, &parity, &bits, &flow);1217 return uart_set_options(uport, co, baud, parity, bits, flow);1218}1219 1220static struct uart_driver zs_reg;1221static struct console zs_console = {1222 .name = "ttyS",1223 .write = zs_console_write,1224 .device = uart_console_device,1225 .setup = zs_console_setup,1226 .flags = CON_PRINTBUFFER,1227 .index = -1,1228 .data = &zs_reg,1229};1230 1231/*1232 * Register console.1233 */1234static int __init zs_serial_console_init(void)1235{1236 int ret;1237 1238 ret = zs_probe_sccs();1239 if (ret)1240 return ret;1241 register_console(&zs_console);1242 1243 return 0;1244}1245 1246console_initcall(zs_serial_console_init);1247 1248#define SERIAL_ZS_CONSOLE &zs_console1249#else1250#define SERIAL_ZS_CONSOLE NULL1251#endif /* CONFIG_SERIAL_ZS_CONSOLE */1252 1253static struct uart_driver zs_reg = {1254 .owner = THIS_MODULE,1255 .driver_name = "serial",1256 .dev_name = "ttyS",1257 .major = TTY_MAJOR,1258 .minor = 64,1259 .nr = ZS_NUM_SCCS * ZS_NUM_CHAN,1260 .cons = SERIAL_ZS_CONSOLE,1261};1262 1263/* zs_init inits the driver. */1264static int __init zs_init(void)1265{1266 int i, ret;1267 1268 pr_info("%s%s\n", zs_name, zs_version);1269 1270 /* Find out how many Z85C30 SCCs we have. */1271 ret = zs_probe_sccs();1272 if (ret)1273 return ret;1274 1275 ret = uart_register_driver(&zs_reg);1276 if (ret)1277 return ret;1278 1279 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {1280 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];1281 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];1282 struct uart_port *uport = &zport->port;1283 1284 if (zport->scc)1285 uart_add_one_port(&zs_reg, uport);1286 }1287 1288 return 0;1289}1290 1291static void __exit zs_exit(void)1292{1293 int i;1294 1295 for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {1296 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];1297 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];1298 struct uart_port *uport = &zport->port;1299 1300 if (zport->scc)1301 uart_remove_one_port(&zs_reg, uport);1302 }1303 1304 uart_unregister_driver(&zs_reg);1305}1306 1307module_init(zs_init);1308module_exit(zs_exit);1309