286 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * zs.h: Definitions for the DECstation Z85C30 serial driver.4 *5 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.6 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.7 *8 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)9 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)10 * Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki11 */12#ifndef _SERIAL_ZS_H13#define _SERIAL_ZS_H14 15#ifdef __KERNEL__16 17#define ZS_NUM_REGS 1618 19/*20 * This is our internal structure for each serial port's state.21 */22struct zs_port {23 struct zs_scc *scc; /* Containing SCC. */24 struct uart_port port; /* Underlying UART. */25 26 int clk_mode; /* May be 1, 16, 32, or 64. */27 28 unsigned int tty_break; /* Set on BREAK condition. */29 int tx_stopped; /* Output is suspended. */30 31 unsigned int mctrl; /* State of modem lines. */32 u8 brk; /* BREAK state from RR0. */33 34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */35};36 37/*38 * Per-SCC state for locking and the interrupt handler.39 */40struct zs_scc {41 struct zs_port zport[2];42 spinlock_t zlock;43 atomic_t irq_guard;44 int initialised;45};46 47#endif /* __KERNEL__ */48 49/*50 * Conversion routines to/from brg time constants from/to bits per second.51 */52#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))53#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)54 55/*56 * The Zilog register set.57 */58 59/* Write Register 0 (Command) */60#define R0 0 /* Register selects */61#define R1 162#define R2 263#define R3 364#define R4 465#define R5 566#define R6 667#define R7 768#define R8 869#define R9 970#define R10 1071#define R11 1172#define R12 1273#define R13 1374#define R14 1475#define R15 1576 77#define NULLCODE 0 /* Null Code */78#define POINT_HIGH 0x8 /* Select upper half of registers */79#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */80#define SEND_ABORT 0x18 /* HDLC Abort */81#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */82#define RES_Tx_P 0x28 /* Reset TxINT Pending */83#define ERR_RES 0x30 /* Error Reset */84#define RES_H_IUS 0x38 /* Reset highest IUS */85 86#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */87#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */88#define RES_EOM_L 0xC0 /* Reset EOM latch */89 90/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */91#define EXT_INT_ENAB 0x1 /* Ext Int Enable */92#define TxINT_ENAB 0x2 /* Tx Int Enable */93#define PAR_SPEC 0x4 /* Parity is special condition */94 95#define RxINT_DISAB 0 /* Rx Int Disable */96#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */97#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */98#define RxINT_ERR 0x18 /* Int on error only */99#define RxINT_MASK 0x18100 101#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */102#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */103#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */104 105/* Write Register 2 (Interrupt Vector) */106 107/* Write Register 3 (Receive Parameters and Control) */108#define RxENABLE 0x1 /* Rx Enable */109#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */110#define ADD_SM 0x4 /* Address Search Mode (SDLC) */111#define RxCRC_ENAB 0x8 /* Rx CRC Enable */112#define ENT_HM 0x10 /* Enter Hunt Mode */113#define AUTO_ENAB 0x20 /* Auto Enables */114#define Rx5 0x0 /* Rx 5 Bits/Character */115#define Rx7 0x40 /* Rx 7 Bits/Character */116#define Rx6 0x80 /* Rx 6 Bits/Character */117#define Rx8 0xc0 /* Rx 8 Bits/Character */118#define RxNBITS_MASK 0xc0119 120/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */121#define PAR_ENA 0x1 /* Parity Enable */122#define PAR_EVEN 0x2 /* Parity Even/Odd* */123 124#define SYNC_ENAB 0 /* Sync Modes Enable */125#define SB1 0x4 /* 1 stop bit/char */126#define SB15 0x8 /* 1.5 stop bits/char */127#define SB2 0xc /* 2 stop bits/char */128#define SB_MASK 0xc129 130#define MONSYNC 0 /* 8 Bit Sync character */131#define BISYNC 0x10 /* 16 bit sync character */132#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */133#define EXTSYNC 0x30 /* External Sync Mode */134 135#define X1CLK 0x0 /* x1 clock mode */136#define X16CLK 0x40 /* x16 clock mode */137#define X32CLK 0x80 /* x32 clock mode */138#define X64CLK 0xc0 /* x64 clock mode */139#define XCLK_MASK 0xc0140 141/* Write Register 5 (Transmit Parameters and Controls) */142#define TxCRC_ENAB 0x1 /* Tx CRC Enable */143#define RTS 0x2 /* RTS */144#define SDLC_CRC 0x4 /* SDLC/CRC-16 */145#define TxENAB 0x8 /* Tx Enable */146#define SND_BRK 0x10 /* Send Break */147#define Tx5 0x0 /* Tx 5 bits (or less)/character */148#define Tx7 0x20 /* Tx 7 bits/character */149#define Tx6 0x40 /* Tx 6 bits/character */150#define Tx8 0x60 /* Tx 8 bits/character */151#define TxNBITS_MASK 0x60152#define DTR 0x80 /* DTR */153 154/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */155 156/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */157 158/* Write Register 8 (Transmit Buffer) */159 160/* Write Register 9 (Master Interrupt Control) */161#define VIS 1 /* Vector Includes Status */162#define NV 2 /* No Vector */163#define DLC 4 /* Disable Lower Chain */164#define MIE 8 /* Master Interrupt Enable */165#define STATHI 0x10 /* Status high */166#define SOFTACK 0x20 /* Software Interrupt Acknowledge */167#define NORESET 0 /* No reset on write to R9 */168#define CHRB 0x40 /* Reset channel B */169#define CHRA 0x80 /* Reset channel A */170#define FHWRES 0xc0 /* Force hardware reset */171 172/* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */173#define BIT6 1 /* 6 bit/8bit sync */174#define LOOPMODE 2 /* SDLC Loop mode */175#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */176#define MARKIDLE 8 /* Mark/flag on idle */177#define GAOP 0x10 /* Go active on poll */178#define NRZ 0 /* NRZ mode */179#define NRZI 0x20 /* NRZI mode */180#define FM1 0x40 /* FM1 (transition = 1) */181#define FM0 0x60 /* FM0 (transition = 0) */182#define CRCPS 0x80 /* CRC Preset I/O */183 184/* Write Register 11 (Clock Mode Control) */185#define TRxCXT 0 /* TRxC = Xtal output */186#define TRxCTC 1 /* TRxC = Transmit clock */187#define TRxCBR 2 /* TRxC = BR Generator Output */188#define TRxCDP 3 /* TRxC = DPLL output */189#define TRxCOI 4 /* TRxC O/I */190#define TCRTxCP 0 /* Transmit clock = RTxC pin */191#define TCTRxCP 8 /* Transmit clock = TRxC pin */192#define TCBR 0x10 /* Transmit clock = BR Generator output */193#define TCDPLL 0x18 /* Transmit clock = DPLL output */194#define RCRTxCP 0 /* Receive clock = RTxC pin */195#define RCTRxCP 0x20 /* Receive clock = TRxC pin */196#define RCBR 0x40 /* Receive clock = BR Generator output */197#define RCDPLL 0x60 /* Receive clock = DPLL output */198#define RTxCX 0x80 /* RTxC Xtal/No Xtal */199 200/* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */201 202/* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */203 204/* Write Register 14 (Miscellaneous Control Bits) */205#define BRENABL 1 /* Baud rate generator enable */206#define BRSRC 2 /* Baud rate generator source */207#define DTRREQ 4 /* DTR/Request function */208#define AUTOECHO 8 /* Auto Echo */209#define LOOPBAK 0x10 /* Local loopback */210#define SEARCH 0x20 /* Enter search mode */211#define RMC 0x40 /* Reset missing clock */212#define DISDPLL 0x60 /* Disable DPLL */213#define SSBR 0x80 /* Set DPLL source = BR generator */214#define SSRTxC 0xa0 /* Set DPLL source = RTxC */215#define SFMM 0xc0 /* Set FM mode */216#define SNRZI 0xe0 /* Set NRZI mode */217 218/* Write Register 15 (External/Status Interrupt Control) */219#define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */220#define ZCIE 2 /* Zero count IE */221#define DCDIE 8 /* DCD IE */222#define SYNCIE 0x10 /* Sync/hunt IE */223#define CTSIE 0x20 /* CTS IE */224#define TxUIE 0x40 /* Tx Underrun/EOM IE */225#define BRKIE 0x80 /* Break/Abort IE */226 227 228/* Read Register 0 (Transmit/Receive Buffer Status and External Status) */229#define Rx_CH_AV 0x1 /* Rx Character Available */230#define ZCOUNT 0x2 /* Zero count */231#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */232#define DCD 0x8 /* DCD */233#define SYNC_HUNT 0x10 /* Sync/hunt */234#define CTS 0x20 /* CTS */235#define TxEOM 0x40 /* Tx underrun */236#define BRK_ABRT 0x80 /* Break/Abort */237 238/* Read Register 1 (Special Receive Condition Status) */239#define ALL_SNT 0x1 /* All sent */240/* Residue Data for 8 Rx bits/char programmed */241#define RES3 0x8 /* 0/3 */242#define RES4 0x4 /* 0/4 */243#define RES5 0xc /* 0/5 */244#define RES6 0x2 /* 0/6 */245#define RES7 0xa /* 0/7 */246#define RES8 0x6 /* 0/8 */247#define RES18 0xe /* 1/8 */248#define RES28 0x0 /* 2/8 */249/* Special Rx Condition Interrupts */250#define PAR_ERR 0x10 /* Parity Error */251#define Rx_OVR 0x20 /* Rx Overrun Error */252#define FRM_ERR 0x40 /* CRC/Framing Error */253#define END_FR 0x80 /* End of Frame (SDLC) */254 255/* Read Register 2 (Interrupt Vector (WR2) -- channel A). */256 257/* Read Register 2 (Modified Interrupt Vector -- channel B). */258 259/* Read Register 3 (Interrupt Pending Bits -- channel A only). */260#define CHBEXT 0x1 /* Channel B Ext/Stat IP */261#define CHBTxIP 0x2 /* Channel B Tx IP */262#define CHBRxIP 0x4 /* Channel B Rx IP */263#define CHAEXT 0x8 /* Channel A Ext/Stat IP */264#define CHATxIP 0x10 /* Channel A Tx IP */265#define CHARxIP 0x20 /* Channel A Rx IP */266 267/* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */268 269/* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */270 271/* Read Register 8 (Receive Data) */272 273/* Read Register 10 (Miscellaneous Status Bits) */274#define ONLOOP 2 /* On loop */275#define LOOPSEND 0x10 /* Loop sending */276#define CLK2MIS 0x40 /* Two clocks missing */277#define CLK1MIS 0x80 /* One clock missing */278 279/* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */280 281/* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */282 283/* Read Register 15 (External/Status Interrupt Control (WR15)) */284 285#endif /* _SERIAL_ZS_H */286