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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2021 HiSilicon Ltd. */3 4#ifndef HISI_ACC_VFIO_PCI_H5#define HISI_ACC_VFIO_PCI_H6 7#include <linux/hisi_acc_qm.h>8 9#define MB_POLL_PERIOD_US 1010#define MB_POLL_TIMEOUT_US 100011#define QM_CACHE_WB_START 0x20412#define QM_CACHE_WB_DONE 0x20813#define QM_MB_CMD_PAUSE_QM 0xe14#define QM_ABNORMAL_INT_STATUS 0x10000815#define QM_IFC_INT_STATUS 0x002816#define SEC_CORE_INT_STATUS 0x30100817#define HPRE_HAC_INT_STATUS 0x30180018#define HZIP_CORE_INT_STATUS 0x3010AC19 20#define QM_VFT_CFG_RDY 0x10006c21#define QM_VFT_CFG_OP_WR 0x10005822#define QM_VFT_CFG_TYPE 0x10005c23#define QM_VFT_CFG 0x10006024#define QM_VFT_CFG_OP_ENABLE 0x10005425#define QM_VFT_CFG_DATA_L 0x10006426#define QM_VFT_CFG_DATA_H 0x10006827 28#define ERROR_CHECK_TIMEOUT 10029#define CHECK_DELAY_TIME 10030 31#define QM_SQC_VFT_BASE_SHIFT_V2 2832#define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)33#define QM_SQC_VFT_NUM_SHIFT_V2 4534#define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)35 36/* RW regs */37#define QM_REGS_MAX_LEN 738#define QM_REG_ADDR_OFFSET 0x000439 40#define QM_XQC_ADDR_OFFSET 32U41#define QM_VF_AEQ_INT_MASK 0x000442#define QM_VF_EQ_INT_MASK 0x000c43#define QM_IFC_INT_SOURCE_V 0x002044#define QM_IFC_INT_MASK 0x002445#define QM_IFC_INT_SET_V 0x002c46#define QM_QUE_ISO_CFG_V 0x003047#define QM_PAGE_SIZE 0x003448 49#define QM_EQC_DW0 0X800050#define QM_AEQC_DW0 0X802051 52struct acc_vf_data {53#define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)54 /* QM match information */55#define ACC_DEV_MAGIC 0XCDCDCDCDFEEDAACC56 u64 acc_magic;57 u32 qp_num;58 u32 dev_id;59 u32 que_iso_cfg;60 u32 qp_base;61 u32 vf_qm_state;62 /* QM reserved match information */63 u32 qm_rsv_state[3];64 65 /* QM RW regs */66 u32 aeq_int_mask;67 u32 eq_int_mask;68 u32 ifc_int_source;69 u32 ifc_int_mask;70 u32 ifc_int_set;71 u32 page_size;72 73 /* QM_EQC_DW has 7 regs */74 u32 qm_eqc_dw[7];75 76 /* QM_AEQC_DW has 7 regs */77 u32 qm_aeqc_dw[7];78 79 /* QM reserved 5 regs */80 u32 qm_rsv_regs[5];81 u32 padding;82 /* QM memory init information */83 u64 eqe_dma;84 u64 aeqe_dma;85 u64 sqc_dma;86 u64 cqc_dma;87};88 89struct hisi_acc_vf_migration_file {90 struct file *filp;91 struct mutex lock;92 bool disabled;93 94 struct hisi_acc_vf_core_device *hisi_acc_vdev;95 struct acc_vf_data vf_data;96 size_t total_length;97};98 99struct hisi_acc_vf_core_device {100 struct vfio_pci_core_device core_device;101 u8 match_done;102 103 /* For migration state */104 struct mutex state_mutex;105 enum vfio_device_mig_state mig_state;106 struct pci_dev *pf_dev;107 struct pci_dev *vf_dev;108 struct hisi_qm *pf_qm;109 struct hisi_qm vf_qm;110 u32 vf_qm_state;111 int vf_id;112 struct hisi_acc_vf_migration_file *resuming_migf;113 struct hisi_acc_vf_migration_file *saving_migf;114};115#endif /* HISI_ACC_VFIO_PCI_H */116