66 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef CARMINE_CARMINE_H3#define CARMINE_CARMINE_H4 5#define CARMINE_MEMORY_BAR 26#define CARMINE_CONFIG_BAR 37 8#define MAX_DISPLAY 29#define CARMINE_DISPLAY_MEM (800 * 600 * 4)10#define CARMINE_TOTAL_DIPLAY_MEM (CARMINE_DISPLAY_MEM * MAX_DISPLAY)11 12#define CARMINE_USE_DISPLAY0 (1 << 0)13#define CARMINE_USE_DISPLAY1 (1 << 1)14 15/*16 * This values work on the eval card. Custom boards may use different timings,17 * here an example :)18 */19 20/* DRAM initialization values */21#ifdef CONFIG_FB_CARMINE_DRAM_EVAL22 23#define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff)24#define CARMINE_DFLT_IP_DCTL_ADD (0x05c3)25#define CARMINE_DFLT_IP_DCTL_MODE (0x0121)26#define CARMINE_DFLT_IP_DCTL_EMODE (0x8000)27#define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x4749)28#define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x2a22)29#define CARMINE_DFLT_IP_DCTL_REFRESH (0x0042)30#define CARMINE_DFLT_IP_DCTL_STATES (0x0003)31#define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020)32#define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f)33#define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000)34#define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x6646)35#define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x0055)36#define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0021)37#define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002)38#define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555)39#define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555)40#define CARMINE_DCTL_DLL_RESET (1)41#endif42 43#ifdef CONFIG_CARMINE_DRAM_CUSTOM44 45#define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff)46#define CARMINE_DFLT_IP_DCTL_ADD (0x03b2)47#define CARMINE_DFLT_IP_DCTL_MODE (0x0161)48#define CARMINE_DFLT_IP_DCTL_EMODE (0x8000)49#define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x2628)50#define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x1a09)51#define CARMINE_DFLT_IP_DCTL_REFRESH (0x00fe)52#define CARMINE_DFLT_IP_DCTL_STATES (0x0003)53#define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020)54#define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f)55#define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000)56#define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x0646)57#define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x55aa)58#define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0061)59#define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002)60#define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555)61#define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555)62#define CARMINE_DCTL_DLL_RESET (1)63#endif64 65#endif66