530 lines · c
1/*2 * drivers/video/chipsfb.c -- frame buffer device for3 * Chips & Technologies 65550 chip.4 *5 * Copyright (C) 1998-2002 Paul Mackerras6 *7 * This file is derived from the Powermac "chips" driver:8 * Copyright (C) 1997 Fabio Riccardi.9 * And from the frame buffer device for Open Firmware-initialized devices:10 * Copyright (C) 1997 Geert Uytterhoeven.11 *12 * This file is subject to the terms and conditions of the GNU General Public13 * License. See the file COPYING in the main directory of this archive for14 * more details.15 */16 17#include <linux/aperture.h>18#include <linux/backlight.h>19#include <linux/module.h>20#include <linux/kernel.h>21#include <linux/errno.h>22#include <linux/string.h>23#include <linux/mm.h>24#include <linux/vmalloc.h>25#include <linux/delay.h>26#include <linux/interrupt.h>27#include <linux/fb.h>28#include <linux/pm.h>29#include <linux/init.h>30#include <linux/pci.h>31#include <linux/console.h>32 33#ifdef CONFIG_PMAC_BACKLIGHT34#include <asm/backlight.h>35#endif36 37/*38 * Since we access the display with inb/outb to fixed port numbers,39 * we can only handle one 6555x chip. -- paulus40 */41#define write_ind(num, val, ap, dp) do { \42 outb((num), (ap)); outb((val), (dp)); \43} while (0)44#define read_ind(num, var, ap, dp) do { \45 outb((num), (ap)); var = inb((dp)); \46} while (0)47 48/* extension registers */49#define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)50#define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)51/* flat panel registers */52#define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)53#define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)54/* CRTC registers */55#define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)56#define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)57/* graphics registers */58#define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)59#define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)60/* sequencer registers */61#define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)62#define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)63/* attribute registers - slightly strange */64#define write_ar(num, val) do { \65 inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \66} while (0)67#define read_ar(num, var) do { \68 inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \69} while (0)70 71/*72 * Exported functions73 */74int chips_init(void);75 76static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);77static int chipsfb_check_var(struct fb_var_screeninfo *var,78 struct fb_info *info);79static int chipsfb_set_par(struct fb_info *info);80static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,81 u_int transp, struct fb_info *info);82static int chipsfb_blank(int blank, struct fb_info *info);83 84static const struct fb_ops chipsfb_ops = {85 .owner = THIS_MODULE,86 FB_DEFAULT_IOMEM_OPS,87 .fb_check_var = chipsfb_check_var,88 .fb_set_par = chipsfb_set_par,89 .fb_setcolreg = chipsfb_setcolreg,90 .fb_blank = chipsfb_blank,91};92 93static int chipsfb_check_var(struct fb_var_screeninfo *var,94 struct fb_info *info)95{96 if (var->xres > 800 || var->yres > 60097 || var->xres_virtual > 800 || var->yres_virtual > 60098 || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)99 || var->nonstd100 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)101 return -EINVAL;102 103 var->xres = var->xres_virtual = 800;104 var->yres = var->yres_virtual = 600;105 106 return 0;107}108 109static int chipsfb_set_par(struct fb_info *info)110{111 if (info->var.bits_per_pixel == 16) {112 write_cr(0x13, 200); // Set line length (doublewords)113 write_xr(0x81, 0x14); // 15 bit (555) color mode114 write_xr(0x82, 0x00); // Disable palettes115 write_xr(0x20, 0x10); // 16 bit blitter mode116 117 info->fix.line_length = 800*2;118 info->fix.visual = FB_VISUAL_TRUECOLOR;119 120 info->var.red.offset = 10;121 info->var.green.offset = 5;122 info->var.blue.offset = 0;123 info->var.red.length = info->var.green.length =124 info->var.blue.length = 5;125 126 } else {127 /* p->var.bits_per_pixel == 8 */128 write_cr(0x13, 100); // Set line length (doublewords)129 write_xr(0x81, 0x12); // 8 bit color mode130 write_xr(0x82, 0x08); // Graphics gamma enable131 write_xr(0x20, 0x00); // 8 bit blitter mode132 133 info->fix.line_length = 800;134 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;135 136 info->var.red.offset = info->var.green.offset =137 info->var.blue.offset = 0;138 info->var.red.length = info->var.green.length =139 info->var.blue.length = 8;140 141 }142 return 0;143}144 145static int chipsfb_blank(int blank, struct fb_info *info)146{147 return 1; /* get fb_blank to set the colormap to all black */148}149 150static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,151 u_int transp, struct fb_info *info)152{153 if (regno > 255)154 return 1;155 red >>= 8;156 green >>= 8;157 blue >>= 8;158 outb(regno, 0x3c8);159 udelay(1);160 outb(red, 0x3c9);161 outb(green, 0x3c9);162 outb(blue, 0x3c9);163 164 return 0;165}166 167struct chips_init_reg {168 unsigned char addr;169 unsigned char data;170};171 172static struct chips_init_reg chips_init_sr[] = {173 { 0x00, 0x03 },174 { 0x01, 0x01 },175 { 0x02, 0x0f },176 { 0x04, 0x0e }177};178 179static struct chips_init_reg chips_init_gr[] = {180 { 0x05, 0x00 },181 { 0x06, 0x0d },182 { 0x08, 0xff }183};184 185static struct chips_init_reg chips_init_ar[] = {186 { 0x10, 0x01 },187 { 0x12, 0x0f },188 { 0x13, 0x00 }189};190 191static struct chips_init_reg chips_init_cr[] = {192 { 0x00, 0x7f },193 { 0x01, 0x63 },194 { 0x02, 0x63 },195 { 0x03, 0x83 },196 { 0x04, 0x66 },197 { 0x05, 0x10 },198 { 0x06, 0x72 },199 { 0x07, 0x3e },200 { 0x08, 0x00 },201 { 0x09, 0x40 },202 { 0x0c, 0x00 },203 { 0x0d, 0x00 },204 { 0x10, 0x59 },205 { 0x11, 0x0d },206 { 0x12, 0x57 },207 { 0x13, 0x64 },208 { 0x14, 0x00 },209 { 0x15, 0x57 },210 { 0x16, 0x73 },211 { 0x17, 0xe3 },212 { 0x18, 0xff },213 { 0x30, 0x02 },214 { 0x31, 0x02 },215 { 0x32, 0x02 },216 { 0x33, 0x02 },217 { 0x40, 0x00 },218 { 0x41, 0x00 },219 { 0x40, 0x80 }220};221 222static struct chips_init_reg chips_init_fr[] = {223 { 0x01, 0x02 },224 { 0x03, 0x08 },225 { 0x04, 0x81 },226 { 0x05, 0x21 },227 { 0x08, 0x0c },228 { 0x0a, 0x74 },229 { 0x0b, 0x11 },230 { 0x10, 0x0c },231 { 0x11, 0xe0 },232 /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */233 { 0x20, 0x63 },234 { 0x21, 0x68 },235 { 0x22, 0x19 },236 { 0x23, 0x7f },237 { 0x24, 0x68 },238 { 0x26, 0x00 },239 { 0x27, 0x0f },240 { 0x30, 0x57 },241 { 0x31, 0x58 },242 { 0x32, 0x0d },243 { 0x33, 0x72 },244 { 0x34, 0x02 },245 { 0x35, 0x22 },246 { 0x36, 0x02 },247 { 0x37, 0x00 }248};249 250static struct chips_init_reg chips_init_xr[] = {251 { 0xce, 0x00 }, /* set default memory clock */252 { 0xcc, 0x43 }, /* memory clock ratio */253 { 0xcd, 0x18 },254 { 0xce, 0xa1 },255 { 0xc8, 0x84 },256 { 0xc9, 0x0a },257 { 0xca, 0x00 },258 { 0xcb, 0x20 },259 { 0xcf, 0x06 },260 { 0xd0, 0x0e },261 { 0x09, 0x01 },262 { 0x0a, 0x02 },263 { 0x0b, 0x01 },264 { 0x20, 0x00 },265 { 0x40, 0x03 },266 { 0x41, 0x01 },267 { 0x42, 0x00 },268 { 0x80, 0x82 },269 { 0x81, 0x12 },270 { 0x82, 0x08 },271 { 0xa0, 0x00 },272 { 0xa8, 0x00 }273};274 275static void chips_hw_init(void)276{277 int i;278 279 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)280 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);281 outb(0x29, 0x3c2); /* set misc output reg */282 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)283 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);284 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)285 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);286 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)287 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);288 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)289 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);290 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)291 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);292}293 294static const struct fb_fix_screeninfo chipsfb_fix = {295 .id = "C&T 65550",296 .type = FB_TYPE_PACKED_PIXELS,297 .visual = FB_VISUAL_PSEUDOCOLOR,298 .accel = FB_ACCEL_NONE,299 .line_length = 800,300 301// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.302// * "3500" PowerBook G3 (the original PB G3) has 2MB.303// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.304// Motherboard actually supports 2MB -- there are two blank locations305// for a second pair of DRAMs. (Thanks, Apple!)306// * 3400 has 1MB (I think). Don't know if it's expandable.307// -- Tim Seufert308 .smem_len = 0x100000, /* 1MB */309};310 311static const struct fb_var_screeninfo chipsfb_var = {312 .xres = 800,313 .yres = 600,314 .xres_virtual = 800,315 .yres_virtual = 600,316 .bits_per_pixel = 8,317 .red = { .length = 8 },318 .green = { .length = 8 },319 .blue = { .length = 8 },320 .height = -1,321 .width = -1,322 .vmode = FB_VMODE_NONINTERLACED,323 .pixclock = 10000,324 .left_margin = 16,325 .right_margin = 16,326 .upper_margin = 16,327 .lower_margin = 16,328 .hsync_len = 8,329 .vsync_len = 8,330};331 332static void init_chips(struct fb_info *p, unsigned long addr)333{334 fb_memset_io(p->screen_base, 0, 0x100000);335 336 p->fix = chipsfb_fix;337 p->fix.smem_start = addr;338 339 p->var = chipsfb_var;340 341 p->fbops = &chipsfb_ops;342 343 fb_alloc_cmap(&p->cmap, 256, 0);344 345 chips_hw_init();346}347 348static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)349{350 struct fb_info *p;351 unsigned long addr;352 unsigned short cmd;353 int rc;354 355 rc = aperture_remove_conflicting_pci_devices(dp, "chipsfb");356 if (rc)357 return rc;358 359 rc = pci_enable_device(dp);360 if (rc < 0) {361 dev_err(&dp->dev, "Cannot enable PCI device\n");362 goto err_out;363 }364 365 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) {366 rc = -ENODEV;367 goto err_disable;368 }369 addr = pci_resource_start(dp, 0);370 if (addr == 0) {371 rc = -ENODEV;372 goto err_disable;373 }374 375 p = framebuffer_alloc(0, &dp->dev);376 if (p == NULL) {377 rc = -ENOMEM;378 goto err_disable;379 }380 381 if (pci_request_region(dp, 0, "chipsfb") != 0) {382 dev_err(&dp->dev, "Cannot request framebuffer\n");383 rc = -EBUSY;384 goto err_release_fb;385 }386 387#ifdef __BIG_ENDIAN388 addr += 0x800000; // Use big-endian aperture389#endif390 391 /* we should use pci_enable_device here, but,392 the device doesn't declare its I/O ports in its BARs393 so pci_enable_device won't turn on I/O responses */394 pci_read_config_word(dp, PCI_COMMAND, &cmd);395 cmd |= 3; /* enable memory and IO space */396 pci_write_config_word(dp, PCI_COMMAND, cmd);397 398#ifdef CONFIG_PMAC_BACKLIGHT399 /* turn on the backlight */400 mutex_lock(&pmac_backlight_mutex);401 if (pmac_backlight) {402 pmac_backlight->props.power = FB_BLANK_UNBLANK;403 backlight_update_status(pmac_backlight);404 }405 mutex_unlock(&pmac_backlight_mutex);406#endif /* CONFIG_PMAC_BACKLIGHT */407 408#ifdef CONFIG_PPC409 p->screen_base = ioremap_wc(addr, 0x200000);410#else411 p->screen_base = ioremap(addr, 0x200000);412#endif413 if (p->screen_base == NULL) {414 dev_err(&dp->dev, "Cannot map framebuffer\n");415 rc = -ENOMEM;416 goto err_release_pci;417 }418 419 pci_set_drvdata(dp, p);420 421 init_chips(p, addr);422 423 rc = register_framebuffer(p);424 if (rc < 0) {425 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");426 goto err_unmap;427 }428 429 dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"430 " (%dK RAM detected)\n",431 p->node, p->fix.smem_len / 1024);432 433 return 0;434 435 err_unmap:436 iounmap(p->screen_base);437 err_release_pci:438 pci_release_region(dp, 0);439 err_release_fb:440 framebuffer_release(p);441 err_disable:442 pci_disable_device(dp);443 err_out:444 return rc;445}446 447static void chipsfb_remove(struct pci_dev *dp)448{449 struct fb_info *p = pci_get_drvdata(dp);450 451 if (p->screen_base == NULL)452 return;453 unregister_framebuffer(p);454 iounmap(p->screen_base);455 p->screen_base = NULL;456 pci_release_region(dp, 0);457}458 459#ifdef CONFIG_PM460static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)461{462 struct fb_info *p = pci_get_drvdata(pdev);463 464 if (state.event == pdev->dev.power.power_state.event)465 return 0;466 if (!(state.event & PM_EVENT_SLEEP))467 goto done;468 469 console_lock();470 chipsfb_blank(1, p);471 fb_set_suspend(p, 1);472 console_unlock();473 done:474 pdev->dev.power.power_state = state;475 return 0;476}477 478static int chipsfb_pci_resume(struct pci_dev *pdev)479{480 struct fb_info *p = pci_get_drvdata(pdev);481 482 console_lock();483 fb_set_suspend(p, 0);484 chipsfb_blank(0, p);485 console_unlock();486 487 pdev->dev.power.power_state = PMSG_ON;488 return 0;489}490#endif /* CONFIG_PM */491 492 493static struct pci_device_id chipsfb_pci_tbl[] = {494 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },495 { 0 }496};497 498MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);499 500static struct pci_driver chipsfb_driver = {501 .name = "chipsfb",502 .id_table = chipsfb_pci_tbl,503 .probe = chipsfb_pci_init,504 .remove = chipsfb_remove,505#ifdef CONFIG_PM506 .suspend = chipsfb_pci_suspend,507 .resume = chipsfb_pci_resume,508#endif509};510 511int __init chips_init(void)512{513 if (fb_modesetting_disabled("chipsfb"))514 return -ENODEV;515 516 if (fb_get_options("chipsfb", NULL))517 return -ENODEV;518 519 return pci_register_driver(&chipsfb_driver);520}521 522module_init(chips_init);523 524static void __exit chipsfb_exit(void)525{526 pci_unregister_driver(&chipsfb_driver);527}528 529MODULE_LICENSE("GPL");530