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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/drivers/video/cyber2000fb.h4 *5 * Copyright (C) 1998-2000 Russell King6 *7 * Integraphics Cyber2000 frame buffer device8 */9 10/*11 * Internal CyberPro sizes and offsets.12 */13#define MMIO_OFFSET 0x0080000014#define MMIO_SIZE 0x000c000015 16#define NR_PALETTE 25617 18#if defined(DEBUG) && defined(CONFIG_DEBUG_LL)19static void debug_printf(char *fmt, ...)20{21 extern void printascii(const char *);22 char buffer[128];23 va_list ap;24 25 va_start(ap, fmt);26 vsprintf(buffer, fmt, ap);27 va_end(ap);28 29 printascii(buffer);30}31#else32#define debug_printf(x...) do { } while (0)33#endif34 35#define RAMDAC_RAMPWRDN 0x0136#define RAMDAC_DAC8BIT 0x0237#define RAMDAC_VREFEN 0x0438#define RAMDAC_BYPASS 0x1039#define RAMDAC_DACPWRDN 0x4040 41#define EXT_CRT_VRTOFL 0x1142#define EXT_CRT_VRTOFL_LINECOMP10 0x1043#define EXT_CRT_VRTOFL_INTERLACE 0x2044 45#define EXT_CRT_IRQ 0x1246#define EXT_CRT_IRQ_ENABLE 0x0147#define EXT_CRT_IRQ_ACT_HIGH 0x0448 49#define EXT_CRT_TEST 0x1350 51#define EXT_SYNC_CTL 0x1652#define EXT_SYNC_CTL_HS_NORMAL 0x0053#define EXT_SYNC_CTL_HS_0 0x0154#define EXT_SYNC_CTL_HS_1 0x0255#define EXT_SYNC_CTL_HS_HSVS 0x0356#define EXT_SYNC_CTL_VS_NORMAL 0x0057#define EXT_SYNC_CTL_VS_0 0x0458#define EXT_SYNC_CTL_VS_1 0x0859#define EXT_SYNC_CTL_VS_COMP 0x0c60 61#define EXT_BUS_CTL 0x3062#define EXT_BUS_CTL_LIN_1MB 0x0063#define EXT_BUS_CTL_LIN_2MB 0x0164#define EXT_BUS_CTL_LIN_4MB 0x0265#define EXT_BUS_CTL_ZEROWAIT 0x0466#define EXT_BUS_CTL_PCIBURST_WRITE 0x2067#define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */68 69#define EXT_SEG_WRITE_PTR 0x3170#define EXT_SEG_READ_PTR 0x3271#define EXT_BIU_MISC 0x3372#define EXT_BIU_MISC_LIN_ENABLE 0x0173#define EXT_BIU_MISC_COP_ENABLE 0x0474#define EXT_BIU_MISC_COP_BFC 0x0875 76#define EXT_FUNC_CTL 0x3c77#define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */78 79#define PCI_BM_CTL 0x3e80#define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */81#define PCI_BM_CTL_BURST 0x02 /* enable burst */82#define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */83#define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */84 85#define X_V2_VID_MEM_START 0x4086#define X_V2_VID_SRC_WIDTH 0x4387#define X_V2_X_START 0x4588#define X_V2_X_END 0x4789#define X_V2_Y_START 0x4990#define X_V2_Y_END 0x4b91#define X_V2_VID_SRC_WIN_WIDTH 0x4d92 93#define Y_V2_DDA_X_INC 0x4394#define Y_V2_DDA_Y_INC 0x4795#define Y_V2_VID_FIFO_CTL 0x4996#define Y_V2_VID_FMT 0x4b97#define Y_V2_VID_DISP_CTL1 0x4c98#define Y_V2_VID_FIFO_CTL1 0x4d99 100#define J_X2_VID_MEM_START 0x40101#define J_X2_VID_SRC_WIDTH 0x43102#define J_X2_X_START 0x47103#define J_X2_X_END 0x49104#define J_X2_Y_START 0x4b105#define J_X2_Y_END 0x4d106#define J_X2_VID_SRC_WIN_WIDTH 0x4f107 108#define K_X2_DDA_X_INIT 0x40109#define K_X2_DDA_X_INC 0x42110#define K_X2_DDA_Y_INIT 0x44111#define K_X2_DDA_Y_INC 0x46112#define K_X2_VID_FMT 0x48113#define K_X2_VID_DISP_CTL1 0x49114 115#define K_CAP_X2_CTL1 0x49116 117#define CURS_H_START 0x50118#define CURS_H_PRESET 0x52119#define CURS_V_START 0x53120#define CURS_V_PRESET 0x55121#define CURS_CTL 0x56122 123#define EXT_ATTRIB_CTL 0x57124#define EXT_ATTRIB_CTL_EXT 0x01125 126#define EXT_OVERSCAN_RED 0x58127#define EXT_OVERSCAN_GREEN 0x59128#define EXT_OVERSCAN_BLUE 0x5a129 130#define CAP_X_START 0x60131#define CAP_X_END 0x62132#define CAP_Y_START 0x64133#define CAP_Y_END 0x66134#define CAP_DDA_X_INIT 0x68135#define CAP_DDA_X_INC 0x6a136#define CAP_DDA_Y_INIT 0x6c137#define CAP_DDA_Y_INC 0x6e138 139#define EXT_MEM_CTL0 0x70140#define EXT_MEM_CTL0_7CLK 0x01141#define EXT_MEM_CTL0_RAS_1 0x02142#define EXT_MEM_CTL0_RAS2CAS_1 0x04143#define EXT_MEM_CTL0_MULTCAS 0x08144#define EXT_MEM_CTL0_ASYM 0x10145#define EXT_MEM_CTL0_CAS1ON 0x20146#define EXT_MEM_CTL0_FIFOFLUSH 0x40147#define EXT_MEM_CTL0_SEQRESET 0x80148 149#define EXT_MEM_CTL1 0x71150#define EXT_MEM_CTL1_PAR 0x00151#define EXT_MEM_CTL1_SERPAR 0x01152#define EXT_MEM_CTL1_SER 0x03153#define EXT_MEM_CTL1_SYNC 0x04154#define EXT_MEM_CTL1_VRAM 0x08155#define EXT_MEM_CTL1_4K_REFRESH 0x10156#define EXT_MEM_CTL1_256Kx4 0x00157#define EXT_MEM_CTL1_512Kx8 0x40158#define EXT_MEM_CTL1_1Mx16 0x60159 160#define EXT_MEM_CTL2 0x72161#define MEM_CTL2_SIZE_1MB 0x00162#define MEM_CTL2_SIZE_2MB 0x01163#define MEM_CTL2_SIZE_4MB 0x02164#define MEM_CTL2_SIZE_MASK 0x03165#define MEM_CTL2_64BIT 0x04166 167#define EXT_HIDDEN_CTL1 0x73168 169#define EXT_FIFO_CTL 0x74170 171#define EXT_SEQ_MISC 0x77172#define EXT_SEQ_MISC_8 0x01173#define EXT_SEQ_MISC_16_RGB565 0x02174#define EXT_SEQ_MISC_32 0x03175#define EXT_SEQ_MISC_24_RGB888 0x04176#define EXT_SEQ_MISC_16_RGB555 0x06177#define EXT_SEQ_MISC_8_RGB332 0x09178#define EXT_SEQ_MISC_16_RGB444 0x0a179 180#define EXT_HIDDEN_CTL4 0x7a181 182#define CURS_MEM_START 0x7e /* bits 23..12 */183 184#define CAP_PIP_X_START 0x80185#define CAP_PIP_X_END 0x82186#define CAP_PIP_Y_START 0x84187#define CAP_PIP_Y_END 0x86188 189#define EXT_CAP_CTL1 0x88190 191#define EXT_CAP_CTL2 0x89192#define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01193#define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02194 195#define BM_CTRL0 0x9c196#define BM_CTRL1 0x9d197 198#define EXT_CAP_MODE1 0xa4199#define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */200#define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */201#define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */202#define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */203#define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */204#define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */205#define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */206 207#define EXT_CAP_MODE2 0xa5208#define EXT_CAP_MODE2_CCIRINVOE 0x01209#define EXT_CAP_MODE2_CCIRINVVGT 0x02210#define EXT_CAP_MODE2_CCIRINVHGT 0x04211#define EXT_CAP_MODE2_CCIRINVDG 0x08212#define EXT_CAP_MODE2_DATEND 0x10213#define EXT_CAP_MODE2_CCIRDGH 0x20214#define EXT_CAP_MODE2_FIXSONY 0x40215#define EXT_CAP_MODE2_SYNCFREEZE 0x80216 217#define EXT_TV_CTL 0xae218 219#define EXT_DCLK_MULT 0xb0220#define EXT_DCLK_DIV 0xb1221#define EXT_DCLK_DIV_VFSEL 0x20222#define EXT_MCLK_MULT 0xb2223#define EXT_MCLK_DIV 0xb3224 225#define EXT_LATCH1 0xb5226#define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */227 228#define EXT_FEATURE 0xb7229#define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */230#define EXT_FEATURE_BUS_PCI 0x00231#define EXT_FEATURE_BUS_VL_STD 0x04232#define EXT_FEATURE_BUS_VL_LINEAR 0x05233#define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */234 235#define EXT_LATCH2 0xb6236#define EXT_LATCH2_I2C_CLKEN 0x10237#define EXT_LATCH2_I2C_CLK 0x20238#define EXT_LATCH2_I2C_DATEN 0x40239#define EXT_LATCH2_I2C_DAT 0x80240 241#define EXT_XT_CTL 0xbe242#define EXT_XT_CAP16 0x04243#define EXT_XT_LINEARFB 0x08244#define EXT_XT_PAL 0x10245 246#define EXT_MEM_START 0xc0 /* ext start address 21 bits */247#define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */248#define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */249#define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */250#define EXT_X_START 0xc5 /* ext->screen, 16 bits */251#define EXT_X_END 0xc7 /* ext->screen, 16 bits */252#define EXT_Y_START 0xc9 /* ext->screen, 16 bits */253#define EXT_Y_END 0xcb /* ext->screen, 16 bits */254#define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */255#define EXT_COLOUR_COMPARE 0xce /* 24 bits */256#define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */257#define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */258#define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */259#define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */260 261#define EXT_VID_FIFO_CTL 0xd9262 263#define EXT_VID_FMT 0xdb264#define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */265#define EXT_VID_FMT_RGB555 0x01266#define EXT_VID_FMT_RGB565 0x02267#define EXT_VID_FMT_RGB888_24 0x03268#define EXT_VID_FMT_RGB888_32 0x04269#define EXT_VID_FMT_RGB8 0x05270#define EXT_VID_FMT_RGB4444 0x06271#define EXT_VID_FMT_RGB8T 0x07272#define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */273#define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */274#define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */275#define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */276 277#define EXT_VID_DISP_CTL1 0xdc278#define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */279#define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */280#define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */281#define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */282#define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */283#define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */284#define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */285#define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */286 287#define EXT_VID_FIFO_CTL1 0xdd288#define EXT_VID_FIFO_CTL1_OE_HIGH 0x02289#define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */290 291#define EXT_ROM_UCB4GH 0xe5292#define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */293#define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */294#define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */295#define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */296#define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */297 298#define VFAC_CTL1 0xe8299#define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/300#define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */301#define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */302#define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */303#define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */304#define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */305#define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */306 307#define VFAC_CTL2 0xe9308#define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */309#define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */310#define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */311#define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */312#define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */313#define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */314#define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */315#define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */316 317#define VFAC_CTL3 0xea318#define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */319#define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */320#define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */321#define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */322#define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */323#define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */324#define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */325#define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */326 327#define CAP_MEM_START 0xeb /* 18 bits */328#define CAP_MAP_WIDTH 0xed /* high 6 bits */329#define CAP_PITCH 0xee /* 8 bits */330 331#define CAP_CTL_MISC 0xef332#define CAP_CTL_MISC_HDIV 0x01333#define CAP_CTL_MISC_HDIV4 0x02334#define CAP_CTL_MISC_ODDEVEN 0x04335#define CAP_CTL_MISC_HSYNCDIV2 0x08336#define CAP_CTL_MISC_SYNCTZHIGH 0x10337#define CAP_CTL_MISC_SYNCTZOR 0x20338#define CAP_CTL_MISC_DISPUSED 0x80339 340#define REG_BANK 0xfa341#define REG_BANK_X 0x00342#define REG_BANK_Y 0x01343#define REG_BANK_W 0x02344#define REG_BANK_T 0x03345#define REG_BANK_J 0x04346#define REG_BANK_K 0x05347 348/*349 * Bus-master350 */351#define BM_VID_ADDR_LOW 0xbc040352#define BM_VID_ADDR_HIGH 0xbc044353#define BM_ADDRESS_LOW 0xbc080354#define BM_ADDRESS_HIGH 0xbc084355#define BM_LENGTH 0xbc088356#define BM_CONTROL 0xbc08c357#define BM_CONTROL_ENABLE 0x01 /* enable transfer */358#define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */359#define BM_CONTROL_INIT 0x04 /* initialise status & count */360#define BM_COUNT 0xbc090 /* read-only */361 362/*363 * TV registers364 */365#define TV_VBLANK_EVEN_START 0xbe43c366#define TV_VBLANK_EVEN_END 0xbe440367#define TV_VBLANK_ODD_START 0xbe444368#define TV_VBLANK_ODD_END 0xbe448369#define TV_SYNC_YGAIN 0xbe44c370#define TV_UV_GAIN 0xbe450371#define TV_PED_UVDET 0xbe454372#define TV_UV_BURST_AMP 0xbe458373#define TV_HSYNC_START 0xbe45c374#define TV_HSYNC_END 0xbe460375#define TV_Y_DELAY1 0xbe464376#define TV_Y_DELAY2 0xbe468377#define TV_UV_DELAY1 0xbe46c378#define TV_BURST_START 0xbe470379#define TV_BURST_END 0xbe474380#define TV_HBLANK_START 0xbe478381#define TV_HBLANK_END 0xbe47c382#define TV_PED_EVEN_START 0xbe480383#define TV_PED_EVEN_END 0xbe484384#define TV_PED_ODD_START 0xbe488385#define TV_PED_ODD_END 0xbe48c386#define TV_VSYNC_EVEN_START 0xbe490387#define TV_VSYNC_EVEN_END 0xbe494388#define TV_VSYNC_ODD_START 0xbe498389#define TV_VSYNC_ODD_END 0xbe49c390#define TV_SCFL 0xbe4a0391#define TV_SCFH 0xbe4a4392#define TV_SCP 0xbe4a8393#define TV_DELAYBYPASS 0xbe4b4394#define TV_EQL_END 0xbe4bc395#define TV_SERR_START 0xbe4c0396#define TV_SERR_END 0xbe4c4397#define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/398#define TV_VSYNC_VGA_HS 0xbe4e8399#define TV_FLICK_XMIN 0xbe514400#define TV_FLICK_XMAX 0xbe518401#define TV_FLICK_YMIN 0xbe51c402#define TV_FLICK_YMAX 0xbe520403 404/*405 * Graphics Co-processor406 */407#define CO_REG_CONTROL 0xbf011408#define CO_CTRL_BUSY 0x80409#define CO_CTRL_CMDFULL 0x04410#define CO_CTRL_FIFOEMPTY 0x02411#define CO_CTRL_READY 0x01412 413#define CO_REG_SRC_WIDTH 0xbf018414#define CO_REG_PIXFMT 0xbf01c415#define CO_PIXFMT_32BPP 0x03416#define CO_PIXFMT_24BPP 0x02417#define CO_PIXFMT_16BPP 0x01418#define CO_PIXFMT_8BPP 0x00419 420#define CO_REG_FGMIX 0xbf048421#define CO_FG_MIX_ZERO 0x00422#define CO_FG_MIX_SRC_AND_DST 0x01423#define CO_FG_MIX_SRC_AND_NDST 0x02424#define CO_FG_MIX_SRC 0x03425#define CO_FG_MIX_NSRC_AND_DST 0x04426#define CO_FG_MIX_DST 0x05427#define CO_FG_MIX_SRC_XOR_DST 0x06428#define CO_FG_MIX_SRC_OR_DST 0x07429#define CO_FG_MIX_NSRC_AND_NDST 0x08430#define CO_FG_MIX_SRC_XOR_NDST 0x09431#define CO_FG_MIX_NDST 0x0a432#define CO_FG_MIX_SRC_OR_NDST 0x0b433#define CO_FG_MIX_NSRC 0x0c434#define CO_FG_MIX_NSRC_OR_DST 0x0d435#define CO_FG_MIX_NSRC_OR_NDST 0x0e436#define CO_FG_MIX_ONES 0x0f437 438#define CO_REG_FGCOLOUR 0xbf058439#define CO_REG_BGCOLOUR 0xbf05c440#define CO_REG_PIXWIDTH 0xbf060441#define CO_REG_PIXHEIGHT 0xbf062442#define CO_REG_X_PHASE 0xbf078443#define CO_REG_CMD_L 0xbf07c444#define CO_CMD_L_PATTERN_FGCOL 0x8000445#define CO_CMD_L_INC_LEFT 0x0004446#define CO_CMD_L_INC_UP 0x0002447 448#define CO_REG_CMD_H 0xbf07e449#define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */450#define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */451#define CO_CMD_H_BLITTER 0x0800452 453#define CO_REG_SRC1_PTR 0xbf170454#define CO_REG_SRC2_PTR 0xbf174455#define CO_REG_DEST_PTR 0xbf178456#define CO_REG_DEST_WIDTH 0xbf218457 458/*459 * Private structure460 */461struct cfb_info;462 463struct cyberpro_info {464 struct device *dev;465 struct i2c_adapter *i2c;466 unsigned char __iomem *regs;467 char __iomem *fb;468 char dev_name[32];469 unsigned int fb_size;470 unsigned int chip_id;471 unsigned int irq;472 473 /*474 * The following is a pointer to be passed into the475 * functions below. The modules outside the main476 * cyber2000fb.c driver have no knowledge as to what477 * is within this structure.478 */479 struct cfb_info *info;480};481 482#define ID_IGA_1682 0483#define ID_CYBERPRO_2000 1484#define ID_CYBERPRO_2010 2485#define ID_CYBERPRO_5000 3486 487/*488 * Note! Writing to the Cyber20x0 registers from an interrupt489 * routine is definitely a bad idea atm.490 */491int cyber2000fb_attach(struct cyberpro_info *info, int idx);492void cyber2000fb_detach(int idx);493void cyber2000fb_enable_extregs(struct cfb_info *cfb);494void cyber2000fb_disable_extregs(struct cfb_info *cfb);495