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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * drivers/video/geode/display_gx1.h4 *   -- Geode GX1 display controller5 *6 * Copyright (C) 2005 Arcom Control Systems Ltd.7 *8 * Based on AMD's original 2.4 driver:9 *   Copyright (C) 2004 Advanced Micro Devices, Inc.10 */11#ifndef __DISPLAY_GX1_H__12#define __DISPLAY_GX1_H__13 14unsigned gx1_gx_base(void);15int gx1_frame_buffer_size(void);16 17extern const struct geode_dc_ops gx1_dc_ops;18 19/* GX1 configuration I/O registers */20 21#define CONFIG_CCR3 0xc322#  define CONFIG_CCR3_MAPEN 0x1023#define CONFIG_GCR  0xb824 25/* Memory controller registers */26 27#define MC_BANK_CFG		0x0828#  define MC_BCFG_DIMM0_SZ_MASK		0x0000070029#  define MC_BCFG_DIMM0_PG_SZ_MASK	0x0000007030#  define MC_BCFG_DIMM0_PG_SZ_NO_DIMM	0x0000007031 32#define MC_GBASE_ADD		0x1433#  define MC_GADD_GBADD_MASK		0x000003ff34 35/* Display controller registers */36 37#define DC_PAL_ADDRESS		0x7038#define DC_PAL_DATA		0x7439 40#define DC_UNLOCK		0x0041#  define DC_UNLOCK_CODE		0x0000475842 43#define DC_GENERAL_CFG		0x0444#  define DC_GCFG_DFLE			0x0000000145#  define DC_GCFG_CURE			0x0000000246#  define DC_GCFG_VCLK_DIV		0x0000000447#  define DC_GCFG_PLNO			0x0000000448#  define DC_GCFG_PPC			0x0000000849#  define DC_GCFG_CMPE			0x0000001050#  define DC_GCFG_DECE			0x0000002051#  define DC_GCFG_DCLK_MASK		0x000000C052#  define DC_GCFG_DCLK_DIV_1		0x0000008053#  define DC_GCFG_DFHPSL_MASK		0x00000F0054#  define DC_GCFG_DFHPSL_POS			 855#  define DC_GCFG_DFHPEL_MASK		0x0000F00056#  define DC_GCFG_DFHPEL_POS			1257#  define DC_GCFG_CIM_MASK		0x0003000058#  define DC_GCFG_CIM_POS			1659#  define DC_GCFG_FDTY			0x0004000060#  define DC_GCFG_RTPM			0x0008000061#  define DC_GCFG_DAC_RS_MASK		0x0070000062#  define DC_GCFG_DAC_RS_POS			2063#  define DC_GCFG_CKWR			0x0080000064#  define DC_GCFG_LDBL			0x0100000065#  define DC_GCFG_DIAG			0x0200000066#  define DC_GCFG_CH4S			0x0400000067#  define DC_GCFG_SSLC			0x0800000068#  define DC_GCFG_VIDE			0x1000000069#  define DC_GCFG_VRDY			0x2000000070#  define DC_GCFG_DPCK			0x4000000071#  define DC_GCFG_DDCK			0x8000000072 73#define DC_TIMING_CFG		0x0874#  define DC_TCFG_FPPE			0x0000000175#  define DC_TCFG_HSYE			0x0000000276#  define DC_TCFG_VSYE			0x0000000477#  define DC_TCFG_BLKE			0x0000000878#  define DC_TCFG_DDCK			0x0000001079#  define DC_TCFG_TGEN			0x0000002080#  define DC_TCFG_VIEN			0x0000004081#  define DC_TCFG_BLNK			0x0000008082#  define DC_TCFG_CHSP			0x0000010083#  define DC_TCFG_CVSP			0x0000020084#  define DC_TCFG_FHSP			0x0000040085#  define DC_TCFG_FVSP			0x0000080086#  define DC_TCFG_FCEN			0x0000100087#  define DC_TCFG_CDCE			0x0000200088#  define DC_TCFG_PLNR			0x0000200089#  define DC_TCFG_INTL			0x0000400090#  define DC_TCFG_PXDB			0x0000800091#  define DC_TCFG_BKRT			0x0001000092#  define DC_TCFG_PSD_MASK		0x000E000093#  define DC_TCFG_PSD_POS			1794#  define DC_TCFG_DDCI			0x0800000095#  define DC_TCFG_SENS			0x1000000096#  define DC_TCFG_DNA			0x2000000097#  define DC_TCFG_VNA			0x4000000098#  define DC_TCFG_VINT			0x8000000099 100#define DC_OUTPUT_CFG		0x0C101#  define DC_OCFG_8BPP			0x00000001102#  define DC_OCFG_555			0x00000002103#  define DC_OCFG_PCKE			0x00000004104#  define DC_OCFG_FRME			0x00000008105#  define DC_OCFG_DITE			0x00000010106#  define DC_OCFG_2PXE			0x00000020107#  define DC_OCFG_2XCK			0x00000040108#  define DC_OCFG_2IND			0x00000080109#  define DC_OCFG_34ADD			0x00000100110#  define DC_OCFG_FRMS			0x00000200111#  define DC_OCFG_CKSL			0x00000400112#  define DC_OCFG_PRMP			0x00000800113#  define DC_OCFG_PDEL			0x00001000114#  define DC_OCFG_PDEH			0x00002000115#  define DC_OCFG_CFRW			0x00004000116#  define DC_OCFG_DIAG			0x00008000117 118#define DC_FB_ST_OFFSET		0x10119#define DC_CB_ST_OFFSET		0x14120#define DC_CURS_ST_OFFSET	0x18121#define DC_ICON_ST_OFFSET	0x1C122#define DC_VID_ST_OFFSET	0x20123#define DC_LINE_DELTA		0x24124#define DC_BUF_SIZE		0x28125 126#define DC_H_TIMING_1		0x30127#define DC_H_TIMING_2		0x34128#define DC_H_TIMING_3		0x38129#define DC_FP_H_TIMING		0x3C130 131#define DC_V_TIMING_1		0x40132#define DC_V_TIMING_2		0x44133#define DC_V_TIMING_3		0x48134#define DC_FP_V_TIMING		0x4C135 136#define DC_CURSOR_X		0x50137#define DC_ICON_X		0x54138#define DC_V_LINE_CNT		0x54139#define DC_CURSOR_Y		0x58140#define DC_ICON_Y		0x5C141#define DC_SS_LINE_CMP		0x5C142#define DC_CURSOR_COLOR		0x60143#define DC_ICON_COLOR		0x64144#define DC_BORDER_COLOR		0x68145#define DC_PAL_ADDRESS		0x70146#define DC_PAL_DATA		0x74147#define DC_DFIFO_DIAG		0x78148#define DC_CFIFO_DIAG		0x7C149 150#endif /* !__DISPLAY_GX1_H__ */151