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1/**************************************************************************2 3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.4All Rights Reserved.5 6Permission is hereby granted, free of charge, to any person obtaining a7copy of this software and associated documentation files (the8"Software"), to deal in the Software without restriction, including9without limitation the rights to use, copy, modify, merge, publish,10distribute, sub license, and/or sell copies of the Software, and to11permit persons to whom the Software is furnished to do so, subject to12the following conditions:13 14The above copyright notice and this permission notice (including the15next paragraph) shall be included in all copies or substantial portions16of the Software.17 18THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS19OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF20MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.21IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR22ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,23TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE24SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.25 26**************************************************************************/27 28/*29 * Authors:30 * Kevin E. Martin <kevin@precisioninsight.com>31 */32 33/* I/O register offsets */34#define SRX VGA_SEQ_I35#define GRX VGA_GFX_I36#define ARX VGA_ATT_IW37#define XRX 0x3D638#define MRX 0x3D239 40/* VGA Color Palette Registers */41#define DACMASK 0x3C642#define DACSTATE 0x3C743#define DACRX 0x3C744#define DACWX 0x3C845#define DACDATA 0x3C946 47/* CRT Controller Registers (CRX) */48#define START_ADDR_HI 0x0C49#define START_ADDR_LO 0x0D50#define VERT_SYNC_END 0x1151#define EXT_VERT_TOTAL 0x3052#define EXT_VERT_DISPLAY 0x3153#define EXT_VERT_SYNC_START 0x3254#define EXT_VERT_BLANK_START 0x3355#define EXT_HORIZ_TOTAL 0x3556#define EXT_HORIZ_BLANK 0x3957#define EXT_START_ADDR 0x4058#define EXT_START_ADDR_ENABLE 0x8059#define EXT_OFFSET 0x4160#define EXT_START_ADDR_HI 0x4261#define INTERLACE_CNTL 0x7062#define INTERLACE_ENABLE 0x8063#define INTERLACE_DISABLE 0x0064 65/* Miscellaneous Output Register */66#define MSR_R 0x3CC67#define MSR_W 0x3C268#define IO_ADDR_SELECT 0x0169 70#define MDA_BASE 0x3B071#define CGA_BASE 0x3D072 73/* System Configuration Extension Registers (XRX) */74#define IO_CTNL 0x0975#define EXTENDED_ATTR_CNTL 0x0276#define EXTENDED_CRTC_CNTL 0x0177 78#define ADDRESS_MAPPING 0x0A79#define PACKED_MODE_ENABLE 0x0480#define LINEAR_MODE_ENABLE 0x0281#define PAGE_MAPPING_ENABLE 0x0182 83#define BITBLT_CNTL 0x2084#define COLEXP_MODE 0x3085#define COLEXP_8BPP 0x0086#define COLEXP_16BPP 0x1087#define COLEXP_24BPP 0x2088#define COLEXP_RESERVED 0x3089#define CHIP_RESET 0x0290#define BITBLT_STATUS 0x0191 92#define DISPLAY_CNTL 0x4093#define VGA_WRAP_MODE 0x0294#define VGA_WRAP_AT_256KB 0x0095#define VGA_NO_WRAP 0x0296#define GUI_MODE 0x0197#define STANDARD_VGA_MODE 0x0098#define HIRES_MODE 0x0199 100#define DRAM_ROW_TYPE 0x50101#define DRAM_ROW_0 0x07102#define DRAM_ROW_0_SDRAM 0x00103#define DRAM_ROW_0_EMPTY 0x07104#define DRAM_ROW_1 0x38105#define DRAM_ROW_1_SDRAM 0x00106#define DRAM_ROW_1_EMPTY 0x38107#define DRAM_ROW_CNTL_LO 0x51108#define DRAM_CAS_LATENCY 0x10109#define DRAM_RAS_TIMING 0x08110#define DRAM_RAS_PRECHARGE 0x04111#define DRAM_ROW_CNTL_HI 0x52112#define DRAM_EXT_CNTL 0x53113#define DRAM_REFRESH_RATE 0x03114#define DRAM_REFRESH_DISABLE 0x00115#define DRAM_REFRESH_60HZ 0x01116#define DRAM_REFRESH_FAST_TEST 0x02117#define DRAM_REFRESH_RESERVED 0x03118#define DRAM_TIMING 0x54119#define DRAM_ROW_BNDRY_0 0x55120#define DRAM_ROW_BNDRY_1 0x56121 122#define DPMS_SYNC_SELECT 0x61123#define VSYNC_CNTL 0x08124#define VSYNC_ON 0x00125#define VSYNC_OFF 0x08126#define HSYNC_CNTL 0x02127#define HSYNC_ON 0x00128#define HSYNC_OFF 0x02129 130#define PIXPIPE_CONFIG_0 0x80131#define DAC_8_BIT 0x80132#define DAC_6_BIT 0x00133#define HW_CURSOR_ENABLE 0x10134#define EXTENDED_PALETTE 0x01135 136#define PIXPIPE_CONFIG_1 0x81137#define DISPLAY_COLOR_MODE 0x0F138#define DISPLAY_VGA_MODE 0x00139#define DISPLAY_8BPP_MODE 0x02140#define DISPLAY_15BPP_MODE 0x04141#define DISPLAY_16BPP_MODE 0x05142#define DISPLAY_24BPP_MODE 0x06143#define DISPLAY_32BPP_MODE 0x07144 145#define PIXPIPE_CONFIG_2 0x82146#define DISPLAY_GAMMA_ENABLE 0x08147#define DISPLAY_GAMMA_DISABLE 0x00148#define OVERLAY_GAMMA_ENABLE 0x04149#define OVERLAY_GAMMA_DISABLE 0x00150 151#define CURSOR_CONTROL 0xA0152#define CURSOR_ORIGIN_SCREEN 0x00153#define CURSOR_ORIGIN_DISPLAY 0x10154#define CURSOR_MODE 0x07155#define CURSOR_MODE_DISABLE 0x00156#define CURSOR_MODE_32_4C_AX 0x01157#define CURSOR_MODE_128_2C 0x02158#define CURSOR_MODE_128_1C 0x03159#define CURSOR_MODE_64_3C 0x04160#define CURSOR_MODE_64_4C_AX 0x05161#define CURSOR_MODE_64_4C 0x06162#define CURSOR_MODE_RESERVED 0x07163#define CURSOR_BASEADDR_LO 0xA2164#define CURSOR_BASEADDR_HI 0xA3165#define CURSOR_X_LO 0xA4166#define CURSOR_X_HI 0xA5167#define CURSOR_X_POS 0x00168#define CURSOR_X_NEG 0x80169#define CURSOR_Y_LO 0xA6170#define CURSOR_Y_HI 0xA7171#define CURSOR_Y_POS 0x00172#define CURSOR_Y_NEG 0x80173 174#define VCLK2_VCO_M 0xC8175#define VCLK2_VCO_N 0xC9176#define VCLK2_VCO_MN_MSBS 0xCA177#define VCO_N_MSBS 0x30178#define VCO_M_MSBS 0x03179#define VCLK2_VCO_DIV_SEL 0xCB180#define POST_DIV_SELECT 0x70181#define POST_DIV_1 0x00182#define POST_DIV_2 0x10183#define POST_DIV_4 0x20184#define POST_DIV_8 0x30185#define POST_DIV_16 0x40186#define POST_DIV_32 0x50187#define VCO_LOOP_DIV_BY_4M 0x00188#define VCO_LOOP_DIV_BY_16M 0x04189#define REF_CLK_DIV_BY_5 0x02190#define REF_DIV_4 0x00191#define REF_DIV_1 0x01192 193#define PLL_CNTL 0xCE194#define PLL_MEMCLK_SEL 0x03195#define PLL_MEMCLK__66667KHZ 0x00196#define PLL_MEMCLK__75000KHZ 0x01197#define PLL_MEMCLK__88889KHZ 0x02198#define PLL_MEMCLK_100000KHZ 0x03199 200/* Multimedia Extension Registers (MRX) */201#define ACQ_CNTL_1 0x02202#define ACQ_CNTL_2 0x03203#define FRAME_CAP_MODE 0x01204#define CONT_CAP_MODE 0x00205#define SINGLE_CAP_MODE 0x01206#define ACQ_CNTL_3 0x04207#define COL_KEY_CNTL_1 0x3C208#define BLANK_DISP_OVERLAY 0x20209 210/* FIFOs */211#define LP_FIFO 0x1000212#define HP_FIFO 0x2000213#define INSTPNT 0x3040214#define LP_FIFO_COUNT 0x3040215#define HP_FIFO_COUNT 0x3041216 217/* FIFO Commands */218#define CLIENT 0xE0000000219#define CLIENT_2D 0x60000000220 221/* Command Parser Mode Register */222#define COMPARS 0x3038223#define TWO_D_INST_DISABLE 0x08224#define THREE_D_INST_DISABLE 0x04225#define STATE_VAR_UPDATE_DISABLE 0x02226#define PAL_STIP_DISABLE 0x01227 228/* Interrupt Control Registers */229#define IER 0x3030230#define IIR 0x3032231#define IMR 0x3034232#define ISR 0x3036233#define VMIINTB_EVENT 0x2000234#define GPIO4_INT 0x1000235#define DISP_FLIP_EVENT 0x0800236#define DVD_PORT_DMA 0x0400237#define DISP_VBLANK 0x0200238#define FIFO_EMPTY_DMA_DONE 0x0100239#define INST_PARSER_ERROR 0x0080240#define USER_DEFINED 0x0040241#define BREAKPOINT 0x0020242#define DISP_HORIZ_COUNT 0x0010243#define DISP_VSYNC 0x0008244#define CAPTURE_HORIZ_COUNT 0x0004245#define CAPTURE_VSYNC 0x0002246#define THREE_D_PIPE_FLUSHED 0x0001247 248/* FIFO Watermark and Burst Length Control Register */249#define FWATER_BLC 0x00006000250#define LMI_BURST_LENGTH 0x7F000000251#define LMI_FIFO_WATERMARK 0x003F0000252#define AGP_BURST_LENGTH 0x00007F00253#define AGP_FIFO_WATERMARK 0x0000003F254 255/* BitBLT Registers */256#define SRC_DST_PITCH 0x00040000257#define DST_PITCH 0x1FFF0000258#define SRC_PITCH 0x00001FFF259#define COLEXP_BG_COLOR 0x00040004260#define COLEXP_FG_COLOR 0x00040008261#define MONO_SRC_CNTL 0x0004000C262#define MONO_USE_COLEXP 0x00000000263#define MONO_USE_SRCEXP 0x08000000264#define MONO_DATA_ALIGN 0x07000000265#define MONO_BIT_ALIGN 0x01000000266#define MONO_BYTE_ALIGN 0x02000000267#define MONO_WORD_ALIGN 0x03000000268#define MONO_DWORD_ALIGN 0x04000000269#define MONO_QWORD_ALIGN 0x05000000270#define MONO_SRC_INIT_DSCRD 0x003F0000271#define MONO_SRC_RIGHT_CLIP 0x00003F00272#define MONO_SRC_LEFT_CLIP 0x0000003F273#define BITBLT_CONTROL 0x00040010274#define BLTR_STATUS 0x80000000275#define DYN_DEPTH 0x03000000276#define DYN_DEPTH_8BPP 0x00000000277#define DYN_DEPTH_16BPP 0x01000000278#define DYN_DEPTH_24BPP 0x02000000279#define DYN_DEPTH_32BPP 0x03000000 /* Unimplemented on the i740 */280#define DYN_DEPTH_ENABLE 0x00800000281#define PAT_VERT_ALIGN 0x00700000282#define SOLID_PAT_SELECT 0x00080000283#define PAT_IS_IN_COLOR 0x00000000284#define PAT_IS_MONO 0x00040000285#define MONO_PAT_TRANSP 0x00020000286#define COLOR_TRANSP_ROP 0x00000000287#define COLOR_TRANSP_DST 0x00008000288#define COLOR_TRANSP_EQ 0x00000000289#define COLOR_TRANSP_NOT_EQ 0x00010000290#define COLOR_TRANSP_ENABLE 0x00004000291#define MONO_SRC_TRANSP 0x00002000292#define SRC_IS_IN_COLOR 0x00000000293#define SRC_IS_MONO 0x00001000294#define SRC_USE_SRC_ADDR 0x00000000295#define SRC_USE_BLTDATA 0x00000400296#define BLT_TOP_TO_BOT 0x00000000297#define BLT_BOT_TO_TOP 0x00000200298#define BLT_LEFT_TO_RIGHT 0x00000000299#define BLT_RIGHT_TO_LEFT 0x00000100300#define BLT_ROP 0x000000FF301#define BLT_PAT_ADDR 0x00040014302#define BLT_SRC_ADDR 0x00040018303#define BLT_DST_ADDR 0x0004001C304#define BLT_DST_H_W 0x00040020305#define BLT_DST_HEIGHT 0x1FFF0000306#define BLT_DST_WIDTH 0x00001FFF307#define SRCEXP_BG_COLOR 0x00040024308#define SRCEXP_FG_COLOR 0x00040028309#define BLTDATA 0x00050000310