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1/*-*- linux-c -*-2 * linux/drivers/video/i810_regs.h -- Intel 810/815 Register List3 *4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>5 * All Rights Reserved 6 *7 *8 * This file is subject to the terms and conditions of the GNU General Public9 * License. See the file COPYING in the main directory of this archive for10 * more details.11 */12 13 14/*15 * Intel 810 Chipset Family PRM 15 3.1 16 * GC Register Memory Address Map 17 *18 * Based on:19 * Intel (R) 810 Chipset Family 20 * Programmer s Reference Manual 21 * November 1999 22 * Revision 1.0 23 * Order Number: 298026-001 R24 *25 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers 26 * are I/O mapped. 27 */28 29#ifndef __I810_REGS_H__30#define __I810_REGS_H__31 32/* Instruction and Interrupt Control Registers (01000h 02FFFh) */33#define FENCE 0x02000 34#define PGTBL_CTL 0x02020 35#define PGTBL_ER 0x02024 36#define LRING 0x0203037#define IRING 0x0204038#define HWS_PGA 0x02080 39#define IPEIR 0x0208840#define IPEHR 0x0208C 41#define INSTDONE 0x02090 42#define NOPID 0x0209443#define HWSTAM 0x02098 44#define IER 0x020A045#define IIR 0x020A446#define IMR 0x020A8 47#define ISR 0x020AC 48#define EIR 0x020B0 49#define EMR 0x020B4 50#define ESR 0x020B8 51#define INSTPM 0x020C052#define INSTPS 0x020C4 53#define BBP_PTR 0x020C8 54#define ABB_SRT 0x020CC55#define ABB_END 0x020D056#define DMA_FADD 0x020D4 57#define FW_BLC 0x020D858#define MEM_MODE 0x020DC 59 60/* Memory Control Registers (03000h 03FFFh) */61#define DRT 0x0300062#define DRAMCL 0x0300163#define DRAMCH 0x0300264 65 66/* Span Cursor Registers (04000h 04FFFh) */67#define UI_SC_CTL 0x04008 68 69/* I/O Control Registers (05000h 05FFFh) */70#define HVSYNC 0x05000 71#define GPIOA 0x0501072#define GPIOB 0x05014 73#define GPIOC 0x0501C74 75/* Clock Control and Power Management Registers (06000h 06FFFh) */76#define DCLK_0D 0x0600077#define DCLK_1D 0x0600478#define DCLK_2D 0x0600879#define LCD_CLKD 0x0600C80#define DCLK_0DS 0x0601081#define PWR_CLKC 0x0601482 83/* Graphics Translation Table Range Definition (10000h 1FFFFh) */84#define GTT 0x10000 85 86/* Overlay Registers (30000h 03FFFFh) */87#define OVOADDR 0x3000088#define DOVOSTA 0x3000889#define GAMMA 0x3001090#define OBUF_0Y 0x3010091#define OBUF_1Y 0x3010492#define OBUF_0U 0x3010893#define OBUF_0V 0x3010C94#define OBUF_1U 0x3011095#define OBUF_1V 0x30114 96#define OVOSTRIDE 0x3011897#define YRGB_VPH 0x3011C98#define UV_VPH 0x3012099#define HORZ_PH 0x30124100#define INIT_PH 0x30128101#define DWINPOS 0x3012C 102#define DWINSZ 0x30130103#define SWID 0x30134104#define SWIDQW 0x30138105#define SHEIGHT 0x3013F106#define YRGBSCALE 0x30140 107#define UVSCALE 0x30144108#define OVOCLRCO 0x30148109#define OVOCLRC1 0x3014C110#define DCLRKV 0x30150111#define DLCRKM 0x30154112#define SCLRKVH 0x30158113#define SCLRKVL 0x3015C114#define SCLRKM 0x30160115#define OVOCONF 0x30164116#define OVOCMD 0x30168117#define AWINPOS 0x30170118#define AWINZ 0x30174119 120/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */121#define BR00 0x40000122#define BRO1 0x40004123#define BR02 0x40008124#define BR03 0x4000C125#define BR04 0x40010126#define BR05 0x40014127#define BR06 0x40018128#define BR07 0x4001C129#define BR08 0x40020130#define BR09 0x40024131#define BR10 0x40028132#define BR11 0x4002C133#define BR12 0x40030134#define BR13 0x40034135#define BR14 0x40038136#define BR15 0x4003C137#define BR16 0x40040138#define BR17 0x40044139#define BR18 0x40048140#define BR19 0x4004C141#define SSLADD 0x40074142#define DSLH 0x40078143#define DSLRADD 0x4007C144 145 146/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */147/* LCD/TV-Out */148#define HTOTAL 0x60000149#define HBLANK 0x60004150#define HSYNC 0x60008151#define VTOTAL 0x6000C152#define VBLANK 0x60010153#define VSYNC 0x60014154#define LCDTV_C 0x60018155#define OVRACT 0x6001C156#define BCLRPAT 0x60020157 158/* Display and Cursor Control Registers (70000h 7FFFFh) */159#define DISP_SL 0x70000160#define DISP_SLC 0x70004161#define PIXCONF 0x70008162#define PIXCONF1 0x70009163#define BLTCNTL 0x7000C164#define SWF 0x70014165#define DPLYBASE 0x70020166#define DPLYSTAS 0x70024167#define CURCNTR 0x70080168#define CURBASE 0x70084169#define CURPOS 0x70088170 171 172/* VGA Registers */173 174/* SMRAM Registers */175#define SMRAM 0x10176 177/* Graphics Control Registers */178#define GR_INDEX 0x3CE179#define GR_DATA 0x3CF180 181#define GR10 0x10182#define GR11 0x11183 184/* CRT Controller Registers */185#define CR_INDEX_MDA 0x3B4186#define CR_INDEX_CGA 0x3D4187#define CR_DATA_MDA 0x3B5188#define CR_DATA_CGA 0x3D5189 190#define CR30 0x30191#define CR31 0x31192#define CR32 0x32193#define CR33 0x33194#define CR35 0x35195#define CR39 0x39196#define CR40 0x40197#define CR41 0x41198#define CR42 0x42199#define CR70 0x70200#define CR80 0x80 201#define CR81 0x82202 203/* Extended VGA Registers */204 205/* General Control and Status Registers */206#define ST00 0x3C2207#define ST01_MDA 0x3BA208#define ST01_CGA 0x3DA209#define FRC_READ 0x3CA210#define FRC_WRITE_MDA 0x3BA211#define FRC_WRITE_CGA 0x3DA212#define MSR_READ 0x3CC213#define MSR_WRITE 0x3C2214 215/* Sequencer Registers */216#define SR_INDEX 0x3C4217#define SR_DATA 0x3C5218 219#define SR01 0x01220#define SR02 0x02221#define SR03 0x03222#define SR04 0x04223#define SR07 0x07224 225/* Graphics Controller Registers */226#define GR00 0x00 227#define GR01 0x01228#define GR02 0x02229#define GR03 0x03230#define GR04 0x04231#define GR05 0x05232#define GR06 0x06233#define GR07 0x07234#define GR08 0x08 235 236/* Attribute Controller Registers */237#define ATTR_WRITE 0x3C0238#define ATTR_READ 0x3C1239 240/* VGA Color Palette Registers */241 242/* CLUT */243#define CLUT_DATA 0x3C9 /* DACDATA */244#define CLUT_INDEX_READ 0x3C7 /* DACRX */245#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */246#define DACMASK 0x3C6247 248/* CRT Controller Registers */249#define CR00 0x00250#define CR01 0x01251#define CR02 0x02252#define CR03 0x03253#define CR04 0x04254#define CR05 0x05255#define CR06 0x06256#define CR07 0x07257#define CR08 0x08258#define CR09 0x09259#define CR0A 0x0A260#define CR0B 0x0B261#define CR0C 0x0C262#define CR0D 0x0D263#define CR0E 0x0E264#define CR0F 0x0F265#define CR10 0x10266#define CR11 0x11267#define CR12 0x12268#define CR13 0x13269#define CR14 0x14270#define CR15 0x15271#define CR16 0x16272#define CR17 0x17273#define CR18 0x18274 275#endif /* __I810_REGS_H__ */276