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1/*2 *  linux/drivers/video/kyro/STG4000Ramdac.c3 *4 *  Copyright (C) 2002 STMicroelectronics5 *6 * This file is subject to the terms and conditions of the GNU General Public7 * License.  See the file COPYING in the main directory of this archive8 * for more details.9 */10 11#include <linux/kernel.h>12#include <linux/errno.h>13#include <linux/types.h>14#include <video/kyro.h>15 16#include "STG4000Reg.h"17#include "STG4000Interface.h"18 19static u32 STG_PIXEL_BUS_WIDTH = 128;	/* 128 bit bus width      */20static u32 REF_CLOCK = 14318;21 22int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,23		     u32 displayDepth,24		     u32 displayWidth,25		     u32 displayHeight,26		     s32 HSyncPolarity,27		     s32 VSyncPolarity, u32 * pixelClock)28{29	u32 tmp = 0;30	u32 F = 0, R = 0, P = 0;31	u32 stride = 0;32	u32 ulPdiv = 0;33	u32 physicalPixelDepth = 0;34	/* Make sure DAC is in Reset */35	tmp = STG_READ_REG(SoftwareReset);36 37	if (tmp & 0x1) {38		CLEAR_BIT(1);39		STG_WRITE_REG(SoftwareReset, tmp);40	}41 42	/* Set Pixel Format */43	tmp = STG_READ_REG(DACPixelFormat);44	CLEAR_BITS_FRM_TO(0, 2);45 46	/* Set LUT not used from 16bpp to 32 bpp ??? */47	CLEAR_BITS_FRM_TO(8, 9);48 49	switch (displayDepth) {50	case 16:51		{52			physicalPixelDepth = 16;53			tmp |= _16BPP;54			break;55		}56	case 32:57		{58			/* Set for 32 bits per pixel */59			physicalPixelDepth = 32;60			tmp |= _32BPP;61			break;62		}63	default:64		return -EINVAL;65	}66 67	STG_WRITE_REG(DACPixelFormat, tmp);68 69	/* Workout Bus transfer bandwidth according to pixel format */70	ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;71 72	/* Get Screen Stride in pixels */73	stride = displayWidth;74 75	/* Set Primary size info */76	tmp = STG_READ_REG(DACPrimSize);77	CLEAR_BITS_FRM_TO(0, 10);78	CLEAR_BITS_FRM_TO(12, 31);79	tmp |=80	    ((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -81					      1) << 23))82	     | (stride / ulPdiv));83	STG_WRITE_REG(DACPrimSize, tmp);84 85 86	/* Set Pixel Clock */87	*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);88 89	/* Set DAC PLL Mode */90	tmp = STG_READ_REG(DACPLLMode);91	CLEAR_BITS_FRM_TO(0, 15);92	/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */93	tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));94	STG_WRITE_REG(DACPLLMode, tmp);95 96	/* Set Prim Address */97	tmp = STG_READ_REG(DACPrimAddress);98	CLEAR_BITS_FRM_TO(0, 20);99	CLEAR_BITS_FRM_TO(20, 31);100	STG_WRITE_REG(DACPrimAddress, tmp);101 102	/* Set Cursor details with HW Cursor disabled */103	tmp = STG_READ_REG(DACCursorCtrl);104	tmp &= ~SET_BIT(31);105	STG_WRITE_REG(DACCursorCtrl, tmp);106 107	tmp = STG_READ_REG(DACCursorAddr);108	CLEAR_BITS_FRM_TO(0, 20);109	STG_WRITE_REG(DACCursorAddr, tmp);110 111	/* Set Video Window */112	tmp = STG_READ_REG(DACVidWinStart);113	CLEAR_BITS_FRM_TO(0, 10);114	CLEAR_BITS_FRM_TO(16, 26);115	STG_WRITE_REG(DACVidWinStart, tmp);116 117	tmp = STG_READ_REG(DACVidWinEnd);118	CLEAR_BITS_FRM_TO(0, 10);119	CLEAR_BITS_FRM_TO(16, 26);120	STG_WRITE_REG(DACVidWinEnd, tmp);121 122	/* Set DAC Border Color to default */123	tmp = STG_READ_REG(DACBorderColor);124	CLEAR_BITS_FRM_TO(0, 23);125	STG_WRITE_REG(DACBorderColor, tmp);126 127	/* Set Graphics and Overlay Burst Control */128	STG_WRITE_REG(DACBurstCtrl, 0x0404);129 130	/* Set CRC Trigger to default */131	tmp = STG_READ_REG(DACCrcTrigger);132	CLEAR_BIT(0);133	STG_WRITE_REG(DACCrcTrigger, tmp);134 135	/* Set Video Port Control to default */136	tmp = STG_READ_REG(DigVidPortCtrl);137	CLEAR_BIT(8);138	CLEAR_BITS_FRM_TO(16, 27);139	CLEAR_BITS_FRM_TO(1, 3);140	CLEAR_BITS_FRM_TO(10, 11);141	STG_WRITE_REG(DigVidPortCtrl, tmp);142 143	return 0;144}145 146/* Ramdac control, turning output to the screen on and off */147void DisableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)148{149	u32 tmp;150 151	/* Disable DAC for Graphics Stream Control */152	tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);153	STG_WRITE_REG(DACStreamCtrl, tmp);154}155 156void EnableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)157{158	u32 tmp;159 160	/* Enable DAC for Graphics Stream Control */161	tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);162	STG_WRITE_REG(DACStreamCtrl, tmp);163}164