190 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Fujitsu MB862xx Graphics Controller Registers/Bits4 */5 6#ifndef _MB862XX_REG_H7#define _MB862XX_REG_H8 9#define MB862XX_MMIO_BASE 0x01fc000010#define MB862XX_MMIO_HIGH_BASE 0x03fc000011#define MB862XX_I2C_BASE 0x0000c00012#define MB862XX_DISP_BASE 0x0001000013#define MB862XX_CAP_BASE 0x0001800014#define MB862XX_DRAW_BASE 0x0003000015#define MB862XX_GEO_BASE 0x0003800016#define MB862XX_PIO_BASE 0x0003800017#define MB862XX_MMIO_SIZE 0x4000018 19/* Host interface/pio registers */20#define GC_IST 0x0000002021#define GC_IMASK 0x0000002422#define GC_SRST 0x0000002c23#define GC_CCF 0x0000003824#define GC_RSW 0x0000005c25#define GC_CID 0x000000f026#define GC_REVISION 0x0000008427 28#define GC_CCF_CGE_100 0x0000000029#define GC_CCF_CGE_133 0x0004000030#define GC_CCF_CGE_166 0x0008000031#define GC_CCF_COT_100 0x0000000032#define GC_CCF_COT_133 0x0001000033#define GC_CID_CNAME_MSK 0x0000ff0034#define GC_CID_VERSION_MSK 0x000000ff35 36/* define enabled interrupts hereby */37#define GC_INT_EN 0x0000000038 39/* Memory interface mode register */40#define GC_MMR 0x0000fffc41 42/* Display Controller registers */43#define GC_DCM0 0x0000000044#define GC_HTP 0x0000000445#define GC_HDB_HDP 0x0000000846#define GC_VSW_HSW_HSP 0x0000000c47#define GC_VTR 0x0000001048#define GC_VDP_VSP 0x0000001449#define GC_WY_WX 0x0000001850#define GC_WH_WW 0x0000001c51#define GC_L0M 0x0000002052#define GC_L0OA0 0x0000002453#define GC_L0DA0 0x0000002854#define GC_L0DY_L0DX 0x0000002c55#define GC_L1M 0x0000003056#define GC_L1DA 0x0000003457#define GC_DCM1 0x0000010058#define GC_L0EM 0x0000011059#define GC_L0WY_L0WX 0x0000011460#define GC_L0WH_L0WW 0x0000011861#define GC_L1EM 0x0000012062#define GC_L1WY_L1WX 0x0000012463#define GC_L1WH_L1WW 0x0000012864#define GC_DLS 0x0000018065#define GC_DCM2 0x0000010466#define GC_DCM3 0x0000010867#define GC_CPM_CUTC 0x000000a068#define GC_CUOA0 0x000000a469#define GC_CUY0_CUX0 0x000000a870#define GC_CUOA1 0x000000ac71#define GC_CUY1_CUX1 0x000000b072#define GC_L0PAL0 0x0000040073 74#define GC_CPM_CEN0 0x0010000075#define GC_CPM_CEN1 0x0020000076#define GC_DCM1_DEN 0x8000000077#define GC_DCM1_L1E 0x0002000078#define GC_L1M_16 0x8000000079#define GC_L1M_YC 0x4000000080#define GC_L1M_CS 0x2000000081 82#define GC_DCM01_ESY 0x0000000483#define GC_DCM01_SC 0x00003f0084#define GC_DCM01_RESV 0x0000400085#define GC_DCM01_CKS 0x0000800086#define GC_DCM01_L0E 0x0001000087#define GC_DCM01_DEN 0x8000000088#define GC_L0M_L0C_8 0x0000000089#define GC_L0M_L0C_16 0x8000000090#define GC_L0EM_L0EC_24 0x4000000091#define GC_L0M_L0W_UNIT 6492#define GC_L1EM_DM 0x0200000093 94#define GC_DISP_REFCLK_400 40095 96/* I2C */97#define GC_I2C_BSR 0x00000000 /* BSR */98#define GC_I2C_BCR 0x00000004 /* BCR */99#define GC_I2C_CCR 0x00000008 /* CCR */100#define GC_I2C_ADR 0x0000000C /* ADR */101#define GC_I2C_DAR 0x00000010 /* DAR */102 103#define I2C_DISABLE 0x00000000104#define I2C_STOP 0x00000000105#define I2C_START 0x00000010106#define I2C_REPEATED_START 0x00000030107#define I2C_CLOCK_AND_ENABLE 0x0000003f108#define I2C_READY 0x01109#define I2C_INT 0x01110#define I2C_INTE 0x02111#define I2C_ACK 0x08112#define I2C_BER 0x80113#define I2C_BEIE 0x40114#define I2C_TRX 0x80115#define I2C_LRB 0x10116 117/* Capture registers and bits */118#define GC_CAP_VCM 0x00000000119#define GC_CAP_CSC 0x00000004120#define GC_CAP_VCS 0x00000008121#define GC_CAP_CBM 0x00000010122#define GC_CAP_CBOA 0x00000014123#define GC_CAP_CBLA 0x00000018124#define GC_CAP_IMG_START 0x0000001C125#define GC_CAP_IMG_END 0x00000020126#define GC_CAP_CMSS 0x00000048127#define GC_CAP_CMDS 0x0000004C128 129#define GC_VCM_VIE 0x80000000130#define GC_VCM_CM 0x03000000131#define GC_VCM_VS_PAL 0x00000002132#define GC_CBM_OO 0x80000000133#define GC_CBM_HRV 0x00000010134#define GC_CBM_CBST 0x00000001135 136/* Carmine specific */137#define MB86297_DRAW_BASE 0x00020000138#define MB86297_DISP0_BASE 0x00100000139#define MB86297_DISP1_BASE 0x00140000140#define MB86297_WRBACK_BASE 0x00180000141#define MB86297_CAP0_BASE 0x00200000142#define MB86297_CAP1_BASE 0x00280000143#define MB86297_DRAMCTRL_BASE 0x00300000144#define MB86297_CTRL_BASE 0x00400000145#define MB86297_I2C_BASE 0x00500000146 147#define GC_CTRL_STATUS 0x00000000148#define GC_CTRL_INT_MASK 0x00000004149#define GC_CTRL_CLK_ENABLE 0x0000000c150#define GC_CTRL_SOFT_RST 0x00000010151 152#define GC_CTRL_CLK_EN_DRAM 0x00000001153#define GC_CTRL_CLK_EN_2D3D 0x00000002154#define GC_CTRL_CLK_EN_DISP0 0x00000020155#define GC_CTRL_CLK_EN_DISP1 0x00000040156 157#define GC_2D3D_REV 0x000004b4158#define GC_RE_REVISION 0x24240200159 160/* define enabled interrupts hereby */161#define GC_CARMINE_INT_EN 0x00000004162 163/* DRAM controller */164#define GC_DCTL_MODE_ADD 0x00000000165#define GC_DCTL_SETTIME1_EMODE 0x00000004166#define GC_DCTL_REFRESH_SETTIME2 0x00000008167#define GC_DCTL_RSV0_STATES 0x0000000C168#define GC_DCTL_RSV2_RSV1 0x00000010169#define GC_DCTL_DDRIF2_DDRIF1 0x00000014170#define GC_DCTL_IOCONT1_IOCONT0 0x00000024171 172#define GC_DCTL_STATES_MSK 0x0000000f173#define GC_DCTL_INIT_WAIT_CNT 3000174#define GC_DCTL_INIT_WAIT_INTERVAL 1175 176/* DRAM ctrl values for Carmine PCI Eval. board */177#define GC_EVB_DCTL_MODE_ADD 0x012105c3178#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3179#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000180#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22181#define GC_EVB_DCTL_RSV0_STATES 0x00200003182#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002183#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f184#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646185#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555186 187#define GC_DISP_REFCLK_533 533188 189#endif190