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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * HDMI driver definition for TI OMAP4 Processor.4 *5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/6 */7 8#ifndef _HDMI_H9#define _HDMI_H10 11#include <linux/delay.h>12#include <linux/io.h>13#include <linux/platform_device.h>14#include <linux/hdmi.h>15#include <video/omapfb_dss.h>16#include <sound/omap-hdmi-audio.h>17 18#include "dss.h"19 20/* HDMI Wrapper */21 22#define HDMI_WP_REVISION 0x023#define HDMI_WP_SYSCONFIG 0x1024#define HDMI_WP_IRQSTATUS_RAW 0x2425#define HDMI_WP_IRQSTATUS 0x2826#define HDMI_WP_IRQENABLE_SET 0x2C27#define HDMI_WP_IRQENABLE_CLR 0x3028#define HDMI_WP_IRQWAKEEN 0x3429#define HDMI_WP_PWR_CTRL 0x4030#define HDMI_WP_DEBOUNCE 0x4431#define HDMI_WP_VIDEO_CFG 0x5032#define HDMI_WP_VIDEO_SIZE 0x6033#define HDMI_WP_VIDEO_TIMING_H 0x6834#define HDMI_WP_VIDEO_TIMING_V 0x6C35#define HDMI_WP_CLK 0x7036#define HDMI_WP_AUDIO_CFG 0x8037#define HDMI_WP_AUDIO_CFG2 0x8438#define HDMI_WP_AUDIO_CTRL 0x8839#define HDMI_WP_AUDIO_DATA 0x8C40 41/* HDMI WP IRQ flags */42#define HDMI_IRQ_CORE (1 << 0)43#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)44#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)45#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)46#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)47#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)48#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)49#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)50#define HDMI_IRQ_LINK_CONNECT (1 << 25)51#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)52#define HDMI_IRQ_PLL_LOCK (1 << 29)53#define HDMI_IRQ_PLL_UNLOCK (1 << 30)54#define HDMI_IRQ_PLL_RECAL (1 << 31)55 56/* HDMI PLL */57 58#define PLLCTRL_PLL_CONTROL 0x059#define PLLCTRL_PLL_STATUS 0x460#define PLLCTRL_PLL_GO 0x861#define PLLCTRL_CFG1 0xC62#define PLLCTRL_CFG2 0x1063#define PLLCTRL_CFG3 0x1464#define PLLCTRL_SSC_CFG1 0x1865#define PLLCTRL_SSC_CFG2 0x1C66#define PLLCTRL_CFG4 0x2067 68/* HDMI PHY */69 70#define HDMI_TXPHY_TX_CTRL 0x071#define HDMI_TXPHY_DIGITAL_CTRL 0x472#define HDMI_TXPHY_POWER_CTRL 0x873#define HDMI_TXPHY_PAD_CFG_CTRL 0xC74#define HDMI_TXPHY_BIST_CONTROL 0x1C75 76enum hdmi_pll_pwr {77 HDMI_PLLPWRCMD_ALLOFF = 0,78 HDMI_PLLPWRCMD_PLLONLY = 1,79 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,80 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 381};82 83enum hdmi_phy_pwr {84 HDMI_PHYPWRCMD_OFF = 0,85 HDMI_PHYPWRCMD_LDOON = 1,86 HDMI_PHYPWRCMD_TXON = 287};88 89enum hdmi_core_hdmi_dvi {90 HDMI_DVI = 0,91 HDMI_HDMI = 192};93 94enum hdmi_packing_mode {95 HDMI_PACK_10b_RGB_YUV444 = 0,96 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,97 HDMI_PACK_20b_YUV422 = 2,98 HDMI_PACK_ALREADYPACKED = 799};100 101enum hdmi_stereo_channels {102 HDMI_AUDIO_STEREO_NOCHANNELS = 0,103 HDMI_AUDIO_STEREO_ONECHANNEL = 1,104 HDMI_AUDIO_STEREO_TWOCHANNELS = 2,105 HDMI_AUDIO_STEREO_THREECHANNELS = 3,106 HDMI_AUDIO_STEREO_FOURCHANNELS = 4107};108 109enum hdmi_audio_type {110 HDMI_AUDIO_TYPE_LPCM = 0,111 HDMI_AUDIO_TYPE_IEC = 1112};113 114enum hdmi_audio_justify {115 HDMI_AUDIO_JUSTIFY_LEFT = 0,116 HDMI_AUDIO_JUSTIFY_RIGHT = 1117};118 119enum hdmi_audio_sample_order {120 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,121 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1122};123 124enum hdmi_audio_samples_perword {125 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,126 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1127};128 129enum hdmi_audio_sample_size_omap {130 HDMI_AUDIO_SAMPLE_16BITS = 0,131 HDMI_AUDIO_SAMPLE_24BITS = 1132};133 134enum hdmi_audio_transf_mode {135 HDMI_AUDIO_TRANSF_DMA = 0,136 HDMI_AUDIO_TRANSF_IRQ = 1137};138 139enum hdmi_audio_blk_strt_end_sig {140 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,141 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1142};143 144enum hdmi_core_audio_layout {145 HDMI_AUDIO_LAYOUT_2CH = 0,146 HDMI_AUDIO_LAYOUT_8CH = 1,147 HDMI_AUDIO_LAYOUT_6CH = 2148};149 150enum hdmi_core_cts_mode {151 HDMI_AUDIO_CTS_MODE_HW = 0,152 HDMI_AUDIO_CTS_MODE_SW = 1153};154 155enum hdmi_audio_mclk_mode {156 HDMI_AUDIO_MCLK_128FS = 0,157 HDMI_AUDIO_MCLK_256FS = 1,158 HDMI_AUDIO_MCLK_384FS = 2,159 HDMI_AUDIO_MCLK_512FS = 3,160 HDMI_AUDIO_MCLK_768FS = 4,161 HDMI_AUDIO_MCLK_1024FS = 5,162 HDMI_AUDIO_MCLK_1152FS = 6,163 HDMI_AUDIO_MCLK_192FS = 7164};165 166struct hdmi_video_format {167 enum hdmi_packing_mode packing_mode;168 u32 y_res; /* Line per panel */169 u32 x_res; /* pixel per line */170};171 172struct hdmi_config {173 struct omap_video_timings timings;174 struct hdmi_avi_infoframe infoframe;175 enum hdmi_core_hdmi_dvi hdmi_dvi_mode;176};177 178struct hdmi_audio_format {179 enum hdmi_stereo_channels stereo_channels;180 u8 active_chnnls_msk;181 enum hdmi_audio_type type;182 enum hdmi_audio_justify justification;183 enum hdmi_audio_sample_order sample_order;184 enum hdmi_audio_samples_perword samples_per_word;185 enum hdmi_audio_sample_size_omap sample_size;186 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;187};188 189struct hdmi_audio_dma {190 u8 transfer_size;191 u8 block_size;192 enum hdmi_audio_transf_mode mode;193 u16 fifo_threshold;194};195 196struct hdmi_core_audio_i2s_config {197 u8 in_length_bits;198 u8 justification;199 u8 sck_edge_mode;200 u8 vbit;201 u8 direction;202 u8 shift;203 u8 active_sds;204};205 206struct hdmi_core_audio_config {207 struct hdmi_core_audio_i2s_config i2s_cfg;208 struct snd_aes_iec958 *iec60958_cfg;209 bool fs_override;210 u32 n;211 u32 cts;212 u32 aud_par_busclk;213 enum hdmi_core_audio_layout layout;214 enum hdmi_core_cts_mode cts_mode;215 bool use_mclk;216 enum hdmi_audio_mclk_mode mclk_mode;217 bool en_acr_pkt;218 bool en_dsd_audio;219 bool en_parallel_aud_input;220 bool en_spdif;221};222 223struct hdmi_wp_data {224 void __iomem *base;225 phys_addr_t phys_base;226};227 228struct hdmi_pll_data {229 struct dss_pll pll;230 231 void __iomem *base;232 233 struct hdmi_wp_data *wp;234};235 236struct hdmi_phy_data {237 void __iomem *base;238 239 u8 lane_function[4];240 u8 lane_polarity[4];241};242 243struct hdmi_core_data {244 void __iomem *base;245};246 247static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,248 u32 val)249{250 __raw_writel(val, base_addr + idx);251}252 253static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)254{255 return __raw_readl(base_addr + idx);256}257 258#define REG_FLD_MOD(base, idx, val, start, end) \259 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\260 val, start, end))261#define REG_GET(base, idx, start, end) \262 FLD_GET(hdmi_read_reg(base, idx), start, end)263 264static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,265 const u32 idx, int b2, int b1, u32 val)266{267 u32 t = 0, v;268 while (val != (v = REG_GET(base_addr, idx, b2, b1))) {269 if (t++ > 10000)270 return v;271 udelay(1);272 }273 return v;274}275 276/* HDMI wrapper funcs */277int hdmi_wp_video_start(struct hdmi_wp_data *wp);278void hdmi_wp_video_stop(struct hdmi_wp_data *wp);279void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);280u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);281void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);282void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);283void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);284int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);285int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);286void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,287 struct hdmi_video_format *video_fmt);288void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,289 struct omap_video_timings *timings);290void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,291 struct omap_video_timings *timings);292void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,293 struct omap_video_timings *timings, struct hdmi_config *param);294int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);295phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);296 297/* HDMI PLL funcs */298void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);299void hdmi_pll_compute(struct hdmi_pll_data *pll,300 unsigned long target_tmds, struct dss_pll_clock_info *pi);301int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,302 struct hdmi_wp_data *wp);303void hdmi_pll_uninit(struct hdmi_pll_data *hpll);304 305/* HDMI PHY funcs */306int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,307 unsigned long lfbitclk);308void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);309int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);310int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);311 312/* HDMI common funcs */313int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,314 struct hdmi_phy_data *phy);315 316/* Audio funcs */317int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);318int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);319int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);320void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,321 struct hdmi_audio_format *aud_fmt);322void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,323 struct hdmi_audio_dma *aud_dma);324static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)325{326 return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;327}328 329/* HDMI DRV data */330struct omap_hdmi {331 struct mutex lock;332 struct platform_device *pdev;333 334 struct hdmi_wp_data wp;335 struct hdmi_pll_data pll;336 struct hdmi_phy_data phy;337 struct hdmi_core_data core;338 339 struct hdmi_config cfg;340 341 struct regulator *vdda_reg;342 343 bool core_enabled;344 345 struct omap_dss_device output;346 347 struct platform_device *audio_pdev;348 void (*audio_abort_cb)(struct device *dev);349 int wp_idlemode;350 351 bool audio_configured;352 struct omap_dss_audio audio_config;353 354 /* This lock should be taken when booleans below are touched. */355 spinlock_t audio_playing_lock;356 bool audio_playing;357 bool display_enabled;358};359 360#endif361