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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __PXA168FB_H__3#define __PXA168FB_H__4 5/* ------------< LCD register >------------ */6/* Video Frame 0&1 start address registers */7#define LCD_SPU_DMA_START_ADDR_Y0 0x00C08#define LCD_SPU_DMA_START_ADDR_U0 0x00C49#define LCD_SPU_DMA_START_ADDR_V0 0x00C810#define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */11#define LCD_SPU_DMA_START_ADDR_Y1 0x00D012#define LCD_SPU_DMA_START_ADDR_U1 0x00D413#define LCD_SPU_DMA_START_ADDR_V1 0x00D814#define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */15 16/* YC & UV Pitch */17#define LCD_SPU_DMA_PITCH_YC 0x00E018#define SPU_DMA_PITCH_C(c) ((c) << 16)19#define SPU_DMA_PITCH_Y(y) (y)20#define LCD_SPU_DMA_PITCH_UV 0x00E421#define SPU_DMA_PITCH_V(v) ((v) << 16)22#define SPU_DMA_PITCH_U(u) (u)23 24/* Video Starting Point on Screen Register */25#define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E826#define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */27#define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */28 29/* Video Size Register */30#define LCD_SPU_DMA_HPXL_VLN 0x00EC31#define CFG_DMA_VLN(y) ((y) << 16)32#define CFG_DMA_HPXL(x) (x)33 34/* Video Size After zooming Register */35#define LCD_SPU_DZM_HPXL_VLN 0x00F036#define CFG_DZM_VLN(y) ((y) << 16)37#define CFG_DZM_HPXL(x) (x)38 39/* Graphic Frame 0&1 Starting Address Register */40#define LCD_CFG_GRA_START_ADDR0 0x00F441#define LCD_CFG_GRA_START_ADDR1 0x00F842 43/* Graphic Frame Pitch */44#define LCD_CFG_GRA_PITCH 0x00FC45 46/* Graphic Starting Point on Screen Register */47#define LCD_SPU_GRA_OVSA_HPXL_VLN 0x010048#define CFG_GRA_OVSA_VLN(y) ((y) << 16)49#define CFG_GRA_OVSA_HPXL(x) (x)50 51/* Graphic Size Register */52#define LCD_SPU_GRA_HPXL_VLN 0x010453#define CFG_GRA_VLN(y) ((y) << 16)54#define CFG_GRA_HPXL(x) (x)55 56/* Graphic Size after Zooming Register */57#define LCD_SPU_GZM_HPXL_VLN 0x010858#define CFG_GZM_VLN(y) ((y) << 16)59#define CFG_GZM_HPXL(x) (x)60 61/* HW Cursor Starting Point on Screen Register */62#define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C63#define CFG_HWC_OVSA_VLN(y) ((y) << 16)64#define CFG_HWC_OVSA_HPXL(x) (x)65 66/* HW Cursor Size */67#define LCD_SPU_HWC_HPXL_VLN 0x011068#define CFG_HWC_VLN(y) ((y) << 16)69#define CFG_HWC_HPXL(x) (x)70 71/* Total Screen Size Register */72#define LCD_SPUT_V_H_TOTAL 0x011473#define CFG_V_TOTAL(y) ((y) << 16)74#define CFG_H_TOTAL(x) (x)75 76/* Total Screen Active Size Register */77#define LCD_SPU_V_H_ACTIVE 0x011878#define CFG_V_ACTIVE(y) ((y) << 16)79#define CFG_H_ACTIVE(x) (x)80 81/* Screen H&V Porch Register */82#define LCD_SPU_H_PORCH 0x011C83#define CFG_H_BACK_PORCH(b) ((b) << 16)84#define CFG_H_FRONT_PORCH(f) (f)85#define LCD_SPU_V_PORCH 0x012086#define CFG_V_BACK_PORCH(b) ((b) << 16)87#define CFG_V_FRONT_PORCH(f) (f)88 89/* Screen Blank Color Register */90#define LCD_SPU_BLANKCOLOR 0x012491#define CFG_BLANKCOLOR_MASK 0x00FFFFFF92#define CFG_BLANKCOLOR_R_MASK 0x000000FF93#define CFG_BLANKCOLOR_G_MASK 0x0000FF0094#define CFG_BLANKCOLOR_B_MASK 0x00FF000095 96/* HW Cursor Color 1&2 Register */97#define LCD_SPU_ALPHA_COLOR1 0x012898#define CFG_HWC_COLOR1 0x00FFFFFF99#define CFG_HWC_COLOR1_R(red) ((red) << 16)100#define CFG_HWC_COLOR1_G(green) ((green) << 8)101#define CFG_HWC_COLOR1_B(blue) (blue)102#define CFG_HWC_COLOR1_R_MASK 0x000000FF103#define CFG_HWC_COLOR1_G_MASK 0x0000FF00104#define CFG_HWC_COLOR1_B_MASK 0x00FF0000105#define LCD_SPU_ALPHA_COLOR2 0x012C106#define CFG_HWC_COLOR2 0x00FFFFFF107#define CFG_HWC_COLOR2_R_MASK 0x000000FF108#define CFG_HWC_COLOR2_G_MASK 0x0000FF00109#define CFG_HWC_COLOR2_B_MASK 0x00FF0000110 111/* Video YUV Color Key Control */112#define LCD_SPU_COLORKEY_Y 0x0130113#define CFG_CKEY_Y2(y2) ((y2) << 24)114#define CFG_CKEY_Y2_MASK 0xFF000000115#define CFG_CKEY_Y1(y1) ((y1) << 16)116#define CFG_CKEY_Y1_MASK 0x00FF0000117#define CFG_CKEY_Y(y) ((y) << 8)118#define CFG_CKEY_Y_MASK 0x0000FF00119#define CFG_ALPHA_Y(y) (y)120#define CFG_ALPHA_Y_MASK 0x000000FF121#define LCD_SPU_COLORKEY_U 0x0134122#define CFG_CKEY_U2(u2) ((u2) << 24)123#define CFG_CKEY_U2_MASK 0xFF000000124#define CFG_CKEY_U1(u1) ((u1) << 16)125#define CFG_CKEY_U1_MASK 0x00FF0000126#define CFG_CKEY_U(u) ((u) << 8)127#define CFG_CKEY_U_MASK 0x0000FF00128#define CFG_ALPHA_U(u) (u)129#define CFG_ALPHA_U_MASK 0x000000FF130#define LCD_SPU_COLORKEY_V 0x0138131#define CFG_CKEY_V2(v2) ((v2) << 24)132#define CFG_CKEY_V2_MASK 0xFF000000133#define CFG_CKEY_V1(v1) ((v1) << 16)134#define CFG_CKEY_V1_MASK 0x00FF0000135#define CFG_CKEY_V(v) ((v) << 8)136#define CFG_CKEY_V_MASK 0x0000FF00137#define CFG_ALPHA_V(v) (v)138#define CFG_ALPHA_V_MASK 0x000000FF139 140/* SPI Read Data Register */141#define LCD_SPU_SPI_RXDATA 0x0140142 143/* Smart Panel Read Data Register */144#define LCD_SPU_ISA_RSDATA 0x0144145#define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF146#define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00147#define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000148#define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000149#define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF150 151/* HWC SRAM Read Data Register */152#define LCD_SPU_HWC_RDDAT 0x0158153 154/* Gamma Table SRAM Read Data Register */155#define LCD_SPU_GAMMA_RDDAT 0x015c156#define CFG_GAMMA_RDDAT_MASK 0x000000FF157 158/* Palette Table SRAM Read Data Register */159#define LCD_SPU_PALETTE_RDDAT 0x0160160#define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF161 162/* I/O Pads Input Read Only Register */163#define LCD_SPU_IOPAD_IN 0x0178164#define CFG_IOPAD_IN_MASK 0x0FFFFFFF165 166/* Reserved Read Only Registers */167#define LCD_CFG_RDREG5F 0x017C168#define IRE_FRAME_CNT_MASK 0x000000C0169#define IPE_FRAME_CNT_MASK 0x00000030170#define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */171#define DMA_FRAME_CNT_MASK 0x00000003 /* Video */172 173/* SPI Control Register. */174#define LCD_SPU_SPI_CTRL 0x0180175#define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */176#define CFG_SCLKCNT_MASK 0xFF000000177#define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */178#define CFG_RXBITS_MASK 0x00FF0000179#define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */180#define CFG_TXBITS_MASK 0x0000FF00181#define CFG_CLKINV(clk) ((clk) << 7)182#define CFG_CLKINV_MASK 0x00000080183#define CFG_KEEPXFER(transfer) ((transfer) << 6)184#define CFG_KEEPXFER_MASK 0x00000040185#define CFG_RXBITSTO0(rx) ((rx) << 5)186#define CFG_RXBITSTO0_MASK 0x00000020187#define CFG_TXBITSTO0(tx) ((tx) << 4)188#define CFG_TXBITSTO0_MASK 0x00000010189#define CFG_SPI_ENA(spi) ((spi) << 3)190#define CFG_SPI_ENA_MASK 0x00000008191#define CFG_SPI_SEL(spi) ((spi) << 2)192#define CFG_SPI_SEL_MASK 0x00000004193#define CFG_SPI_3W4WB(wire) ((wire) << 1)194#define CFG_SPI_3W4WB_MASK 0x00000002195#define CFG_SPI_START(start) (start)196#define CFG_SPI_START_MASK 0x00000001197 198/* SPI Tx Data Register */199#define LCD_SPU_SPI_TXDATA 0x0184200 201/*202 1. Smart Pannel 8-bit Bus Control Register.203 2. AHB Slave Path Data Port Register204*/205#define LCD_SPU_SMPN_CTRL 0x0188206 207/* DMA Control 0 Register */208#define LCD_SPU_DMA_CTRL0 0x0190209#define CFG_NOBLENDING(nb) ((nb) << 31)210#define CFG_NOBLENDING_MASK 0x80000000211#define CFG_GAMMA_ENA(gn) ((gn) << 30)212#define CFG_GAMMA_ENA_MASK 0x40000000213#define CFG_CBSH_ENA(cn) ((cn) << 29)214#define CFG_CBSH_ENA_MASK 0x20000000215#define CFG_PALETTE_ENA(pn) ((pn) << 28)216#define CFG_PALETTE_ENA_MASK 0x10000000217#define CFG_ARBFAST_ENA(an) ((an) << 27)218#define CFG_ARBFAST_ENA_MASK 0x08000000219#define CFG_HWC_1BITMOD(mode) ((mode) << 26)220#define CFG_HWC_1BITMOD_MASK 0x04000000221#define CFG_HWC_1BITENA(mn) ((mn) << 25)222#define CFG_HWC_1BITENA_MASK 0x02000000223#define CFG_HWC_ENA(cn) ((cn) << 24)224#define CFG_HWC_ENA_MASK 0x01000000225#define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20)226#define CFG_DMAFORMAT_MASK 0x00F00000227#define CFG_GRAFORMAT(graformat) ((graformat) << 16)228#define CFG_GRAFORMAT_MASK 0x000F0000229/* for graphic part */230#define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15)231#define CFG_GRA_FTOGGLE_MASK 0x00008000232#define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14)233#define CFG_GRA_HSMOOTH_MASK 0x00004000234#define CFG_GRA_TSTMODE(test) ((test) << 13)235#define CFG_GRA_TSTMODE_MASK 0x00002000236#define CFG_GRA_SWAPRB(swap) ((swap) << 12)237#define CFG_GRA_SWAPRB_MASK 0x00001000238#define CFG_GRA_SWAPUV(swap) ((swap) << 11)239#define CFG_GRA_SWAPUV_MASK 0x00000800240#define CFG_GRA_SWAPYU(swap) ((swap) << 10)241#define CFG_GRA_SWAPYU_MASK 0x00000400242#define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9)243#define CFG_YUV2RGB_GRA_MASK 0x00000200244#define CFG_GRA_ENA(gra) ((gra) << 8)245#define CFG_GRA_ENA_MASK 0x00000100246/* for video part */247#define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7)248#define CFG_DMA_FTOGGLE_MASK 0x00000080249#define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6)250#define CFG_DMA_HSMOOTH_MASK 0x00000040251#define CFG_DMA_TSTMODE(test) ((test) << 5)252#define CFG_DMA_TSTMODE_MASK 0x00000020253#define CFG_DMA_SWAPRB(swap) ((swap) << 4)254#define CFG_DMA_SWAPRB_MASK 0x00000010255#define CFG_DMA_SWAPUV(swap) ((swap) << 3)256#define CFG_DMA_SWAPUV_MASK 0x00000008257#define CFG_DMA_SWAPYU(swap) ((swap) << 2)258#define CFG_DMA_SWAPYU_MASK 0x00000004259#define CFG_DMA_SWAP_MASK 0x0000001C260#define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1)261#define CFG_YUV2RGB_DMA_MASK 0x00000002262#define CFG_DMA_ENA(video) (video)263#define CFG_DMA_ENA_MASK 0x00000001264 265/* DMA Control 1 Register */266#define LCD_SPU_DMA_CTRL1 0x0194267#define CFG_FRAME_TRIG(trig) ((trig) << 31)268#define CFG_FRAME_TRIG_MASK 0x80000000269#define CFG_VSYNC_TRIG(trig) ((trig) << 28)270#define CFG_VSYNC_TRIG_MASK 0x70000000271#define CFG_VSYNC_INV(inv) ((inv) << 27)272#define CFG_VSYNC_INV_MASK 0x08000000273#define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24)274#define CFG_COLOR_KEY_MASK 0x07000000275#define CFG_CARRY(carry) ((carry) << 23)276#define CFG_CARRY_MASK 0x00800000277#define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22)278#define CFG_LNBUF_ENA_MASK 0x00400000279#define CFG_GATED_ENA(gated) ((gated) << 21)280#define CFG_GATED_ENA_MASK 0x00200000281#define CFG_PWRDN_ENA(power) ((power) << 20)282#define CFG_PWRDN_ENA_MASK 0x00100000283#define CFG_DSCALE(dscale) ((dscale) << 18)284#define CFG_DSCALE_MASK 0x000C0000285#define CFG_ALPHA_MODE(amode) ((amode) << 16)286#define CFG_ALPHA_MODE_MASK 0x00030000287#define CFG_ALPHA(alpha) ((alpha) << 8)288#define CFG_ALPHA_MASK 0x0000FF00289#define CFG_PXLCMD(pxlcmd) (pxlcmd)290#define CFG_PXLCMD_MASK 0x000000FF291 292/* SRAM Control Register */293#define LCD_SPU_SRAM_CTRL 0x0198294#define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14)295#define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000296#define CFG_SRAM_ADDR_LCDID(id) ((id) << 8)297#define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00298#define CFG_SRAM_ADDR(addr) (addr)299#define CFG_SRAM_ADDR_MASK 0x000000FF300 301/* SRAM Write Data Register */302#define LCD_SPU_SRAM_WRDAT 0x019C303 304/* SRAM RTC/WTC Control Register */305#define LCD_SPU_SRAM_PARA0 0x01A0306 307/* SRAM Power Down Control Register */308#define LCD_SPU_SRAM_PARA1 0x01A4309#define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */310#define CFG_CSB_256x32_MASK 0x00008000311#define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */312#define CFG_CSB_256x24_MASK 0x00004000313#define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */314#define CFG_CSB_256x8_MASK 0x00002000315#define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */316#define CFG_PDWN256x32_MASK 0x00000080317#define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */318#define CFG_PDWN256x24_MASK 0x00000040319#define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */320#define CFG_PDWN256x8_MASK 0x00000020321#define CFG_PDWN32x32(pdwn) ((pdwn) << 3)322#define CFG_PDWN32x32_MASK 0x00000008323#define CFG_PDWN16x66(pdwn) ((pdwn) << 2)324#define CFG_PDWN16x66_MASK 0x00000004325#define CFG_PDWN32x66(pdwn) ((pdwn) << 1)326#define CFG_PDWN32x66_MASK 0x00000002327#define CFG_PDWN64x66(pdwn) (pdwn)328#define CFG_PDWN64x66_MASK 0x00000001329 330/* Smart or Dumb Panel Clock Divider */331#define LCD_CFG_SCLK_DIV 0x01A8332#define SCLK_SOURCE_SELECT(src) ((src) << 31)333#define SCLK_SOURCE_SELECT_MASK 0x80000000334#define CLK_FRACDIV(frac) ((frac) << 16)335#define CLK_FRACDIV_MASK 0x0FFF0000336#define CLK_INT_DIV(div) (div)337#define CLK_INT_DIV_MASK 0x0000FFFF338 339/* Video Contrast Register */340#define LCD_SPU_CONTRAST 0x01AC341#define CFG_BRIGHTNESS(bright) ((bright) << 16)342#define CFG_BRIGHTNESS_MASK 0xFFFF0000343#define CFG_CONTRAST(contrast) (contrast)344#define CFG_CONTRAST_MASK 0x0000FFFF345 346/* Video Saturation Register */347#define LCD_SPU_SATURATION 0x01B0348#define CFG_C_MULTS(mult) ((mult) << 16)349#define CFG_C_MULTS_MASK 0xFFFF0000350#define CFG_SATURATION(sat) (sat)351#define CFG_SATURATION_MASK 0x0000FFFF352 353/* Video Hue Adjust Register */354#define LCD_SPU_CBSH_HUE 0x01B4355#define CFG_SIN0(sin0) ((sin0) << 16)356#define CFG_SIN0_MASK 0xFFFF0000357#define CFG_COS0(con0) (con0)358#define CFG_COS0_MASK 0x0000FFFF359 360/* Dump LCD Panel Control Register */361#define LCD_SPU_DUMB_CTRL 0x01B8362#define CFG_DUMBMODE(mode) ((mode) << 28)363#define CFG_DUMBMODE_MASK 0xF0000000364#define CFG_LCDGPIO_O(data) ((data) << 20)365#define CFG_LCDGPIO_O_MASK 0x0FF00000366#define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12)367#define CFG_LCDGPIO_ENA_MASK 0x000FF000368#define CFG_BIAS_OUT(bias) ((bias) << 8)369#define CFG_BIAS_OUT_MASK 0x00000100370#define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7)371#define CFG_REVERSE_RGB_MASK 0x00000080372#define CFG_INV_COMPBLANK(blank) ((blank) << 6)373#define CFG_INV_COMPBLANK_MASK 0x00000040374#define CFG_INV_COMPSYNC(sync) ((sync) << 5)375#define CFG_INV_COMPSYNC_MASK 0x00000020376#define CFG_INV_HENA(hena) ((hena) << 4)377#define CFG_INV_HENA_MASK 0x00000010378#define CFG_INV_VSYNC(vsync) ((vsync) << 3)379#define CFG_INV_VSYNC_MASK 0x00000008380#define CFG_INV_HSYNC(hsync) ((hsync) << 2)381#define CFG_INV_HSYNC_MASK 0x00000004382#define CFG_INV_PCLK(pclk) ((pclk) << 1)383#define CFG_INV_PCLK_MASK 0x00000002384#define CFG_DUMB_ENA(dumb) (dumb)385#define CFG_DUMB_ENA_MASK 0x00000001386 387/* LCD I/O Pads Control Register */388#define SPU_IOPAD_CONTROL 0x01BC389#define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */390#define CFG_GRA_VM_ENA_MASK 0x00008000391#define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */392#define CFG_DMA_VM_ENA_MASK 0x00002000393#define CFG_CMD_VM_ENA(vm) ((vm) << 13)394#define CFG_CMD_VM_ENA_MASK 0x00000800395#define CFG_CSC(csc) ((csc) << 8) /* csc */396#define CFG_CSC_MASK 0x00000300397#define CFG_AXICTRL(axi) ((axi) << 4)398#define CFG_AXICTRL_MASK 0x000000F0399#define CFG_IOPADMODE(iopad) (iopad)400#define CFG_IOPADMODE_MASK 0x0000000F401 402/* LCD Interrupt Control Register */403#define SPU_IRQ_ENA 0x01C0404#define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31)405#define DMA_FRAME_IRQ0_ENA_MASK 0x80000000406#define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30)407#define DMA_FRAME_IRQ1_ENA_MASK 0x40000000408#define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29)409#define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000410#define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27)411#define GRA_FRAME_IRQ0_ENA_MASK 0x08000000412#define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26)413#define GRA_FRAME_IRQ1_ENA_MASK 0x04000000414#define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25)415#define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000416#define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23)417#define VSYNC_IRQ_ENA_MASK 0x00800000418#define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22)419#define DUMB_FRAMEDONE_ENA_MASK 0x00400000420#define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21)421#define TWC_FRAMEDONE_ENA_MASK 0x00200000422#define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20)423#define HWC_FRAMEDONE_ENA_MASK 0x00100000424#define SLV_IRQ_ENA(irq) ((irq) << 19)425#define SLV_IRQ_ENA_MASK 0x00080000426#define SPI_IRQ_ENA(irq) ((irq) << 18)427#define SPI_IRQ_ENA_MASK 0x00040000428#define PWRDN_IRQ_ENA(irq) ((irq) << 17)429#define PWRDN_IRQ_ENA_MASK 0x00020000430#define ERR_IRQ_ENA(irq) ((irq) << 16)431#define ERR_IRQ_ENA_MASK 0x00010000432#define CLEAN_SPU_IRQ_ISR(irq) (irq)433#define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF434 435/* LCD Interrupt Status Register */436#define SPU_IRQ_ISR 0x01C4437#define DMA_FRAME_IRQ0(irq) ((irq) << 31)438#define DMA_FRAME_IRQ0_MASK 0x80000000439#define DMA_FRAME_IRQ1(irq) ((irq) << 30)440#define DMA_FRAME_IRQ1_MASK 0x40000000441#define DMA_FF_UNDERFLOW(ff) ((ff) << 29)442#define DMA_FF_UNDERFLOW_MASK 0x20000000443#define GRA_FRAME_IRQ0(irq) ((irq) << 27)444#define GRA_FRAME_IRQ0_MASK 0x08000000445#define GRA_FRAME_IRQ1(irq) ((irq) << 26)446#define GRA_FRAME_IRQ1_MASK 0x04000000447#define GRA_FF_UNDERFLOW(ff) ((ff) << 25)448#define GRA_FF_UNDERFLOW_MASK 0x02000000449#define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23)450#define VSYNC_IRQ_MASK 0x00800000451#define DUMB_FRAMEDONE(fdone) ((fdone) << 22)452#define DUMB_FRAMEDONE_MASK 0x00400000453#define TWC_FRAMEDONE(fdone) ((fdone) << 21)454#define TWC_FRAMEDONE_MASK 0x00200000455#define HWC_FRAMEDONE(fdone) ((fdone) << 20)456#define HWC_FRAMEDONE_MASK 0x00100000457#define SLV_IRQ(irq) ((irq) << 19)458#define SLV_IRQ_MASK 0x00080000459#define SPI_IRQ(irq) ((irq) << 18)460#define SPI_IRQ_MASK 0x00040000461#define PWRDN_IRQ(irq) ((irq) << 17)462#define PWRDN_IRQ_MASK 0x00020000463#define ERR_IRQ(irq) ((irq) << 16)464#define ERR_IRQ_MASK 0x00010000465/* read-only */466#define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000467#define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000468#define DMA_FRAME_CNT_ISR_MASK 0x00003000469#define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800470#define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400471#define GRA_FRAME_CNT_ISR_MASK 0x00000300472#define VSYNC_IRQ_LEVEL_MASK 0x00000080473#define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040474#define TWC_FRAMEDONE_LEVEL_MASK 0x00000020475#define HWC_FRAMEDONE_LEVEL_MASK 0x00000010476#define SLV_FF_EMPTY_MASK 0x00000008477#define DMA_FF_ALLEMPTY_MASK 0x00000004478#define GRA_FF_ALLEMPTY_MASK 0x00000002479#define PWRDN_IRQ_LEVEL_MASK 0x00000001480 481 482/*483 * defined Video Memory Color format for DMA control 0 register484 * DMA0 bit[23:20]485 */486#define VMODE_RGB565 0x0487#define VMODE_RGB1555 0x1488#define VMODE_RGB888PACKED 0x2489#define VMODE_RGB888UNPACKED 0x3490#define VMODE_RGBA888 0x4491#define VMODE_YUV422PACKED 0x5492#define VMODE_YUV422PLANAR 0x6493#define VMODE_YUV420PLANAR 0x7494#define VMODE_SMPNCMD 0x8495#define VMODE_PALETTE4BIT 0x9496#define VMODE_PALETTE8BIT 0xa497#define VMODE_RESERVED 0xb498 499/*500 * defined Graphic Memory Color format for DMA control 0 register501 * DMA0 bit[19:16]502 */503#define GMODE_RGB565 0x0504#define GMODE_RGB1555 0x1505#define GMODE_RGB888PACKED 0x2506#define GMODE_RGB888UNPACKED 0x3507#define GMODE_RGBA888 0x4508#define GMODE_YUV422PACKED 0x5509#define GMODE_YUV422PLANAR 0x6510#define GMODE_YUV420PLANAR 0x7511#define GMODE_SMPNCMD 0x8512#define GMODE_PALETTE4BIT 0x9513#define GMODE_PALETTE8BIT 0xa514#define GMODE_RESERVED 0xb515 516/*517 * define for DMA control 1 register518 */519#define DMA1_FRAME_TRIG 31 /* bit location */520#define DMA1_VSYNC_MODE 28521#define DMA1_VSYNC_INV 27522#define DMA1_CKEY 24523#define DMA1_CARRY 23524#define DMA1_LNBUF_ENA 22525#define DMA1_GATED_ENA 21526#define DMA1_PWRDN_ENA 20527#define DMA1_DSCALE 18528#define DMA1_ALPHA_MODE 16529#define DMA1_ALPHA 08530#define DMA1_PXLCMD 00531 532/*533 * defined for Configure Dumb Mode534 * DUMB LCD Panel bit[31:28]535 */536#define DUMB16_RGB565_0 0x0537#define DUMB16_RGB565_1 0x1538#define DUMB18_RGB666_0 0x2539#define DUMB18_RGB666_1 0x3540#define DUMB12_RGB444_0 0x4541#define DUMB12_RGB444_1 0x5542#define DUMB24_RGB888_0 0x6543#define DUMB_BLANK 0x7544 545/*546 * defined for Configure I/O Pin Allocation Mode547 * LCD LCD I/O Pads control register bit[3:0]548 */549#define IOPAD_DUMB24 0x0550#define IOPAD_DUMB18SPI 0x1551#define IOPAD_DUMB18GPIO 0x2552#define IOPAD_DUMB16SPI 0x3553#define IOPAD_DUMB16GPIO 0x4554#define IOPAD_DUMB12 0x5555#define IOPAD_SMART18SPI 0x6556#define IOPAD_SMART16SPI 0x7557#define IOPAD_SMART8BOTH 0x8558 559#endif /* __PXA168FB_H__ */560