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1 /***************************************************************************\2|* *|3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|4|* *|5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|6|* international laws. Users and possessors of this source code are *|7|* hereby granted a nonexclusive, royalty-free copyright license to *|8|* use this code in individual and commercial software. *|9|* *|10|* Any use of this source code must include, in the user documenta- *|11|* tion and internal comments to the code, notices to the end user *|12|* as follows: *|13|* *|14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|15|* *|16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|27|* *|28|* U.S. Government End Users. This source code is a "commercial *|29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|30|* consisting of "commercial computer software" and "commercial *|31|* computer software documentation," as such terms are used in *|32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|35|* all U.S. Government End Users acquire the source code with only *|36|* those rights set forth herein. *|37|* *|38 \***************************************************************************/39 40/*41 * GPL licensing note -- nVidia is allowing a liberal interpretation of42 * the documentation restriction above, to merely say that this nVidia's43 * copyright and disclaimer should be included with all code derived44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 45 */46 47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */48 49#include <linux/kernel.h>50#include <linux/pci.h>51#include <linux/pci_ids.h>52#include "riva_hw.h"53#include "riva_tbl.h"54#include "nv_type.h"55 56/*57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT58 * operate identically (except TNT has more memory and better 3D quality.59 */60static int nv3Busy61(62 RIVA_HW_INST *chip63)64{65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);67}68static int nv4Busy69(70 RIVA_HW_INST *chip71)72{73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);75}76static int nv10Busy77(78 RIVA_HW_INST *chip79)80{81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);83}84 85static void vgaLockUnlock86(87 RIVA_HW_INST *chip,88 int Lock89)90{91 U008 cr11;92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);94 if(Lock) cr11 |= 0x80;95 else cr11 &= ~0x80;96 VGA_WR08(chip->PCIO, 0x3D5, cr11);97}98static void nv3LockUnlock99(100 RIVA_HW_INST *chip,101 int Lock102)103{104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);106 vgaLockUnlock(chip, Lock);107}108static void nv4LockUnlock109(110 RIVA_HW_INST *chip,111 int Lock112)113{114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);116 vgaLockUnlock(chip, Lock);117}118 119static int ShowHideCursor120(121 RIVA_HW_INST *chip,122 int ShowHide123)124{125 int cursor;126 cursor = chip->CurrentState->cursor1;127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |128 (ShowHide & 0x01);129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);131 return (cursor & 0x01);132}133 134/****************************************************************************\135* *136* The video arbitration routines calculate some "magic" numbers. Fixes *137* the snow seen when accessing the framebuffer without it. *138* It just works (I hope). *139* *140\****************************************************************************/141 142#define DEFAULT_GR_LWM 100143#define DEFAULT_VID_LWM 100144#define DEFAULT_GR_BURST_SIZE 256145#define DEFAULT_VID_BURST_SIZE 128146#define VIDEO 0147#define GRAPHICS 1148#define MPORT 2149#define ENGINE 3150#define GFIFO_SIZE 320151#define GFIFO_SIZE_128 256152#define MFIFO_SIZE 120153#define VFIFO_SIZE 256154 155typedef struct {156 int gdrain_rate;157 int vdrain_rate;158 int mdrain_rate;159 int gburst_size;160 int vburst_size;161 char vid_en;162 char gr_en;163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;164 int by_gfacc;165 char vid_only_once;166 char gr_only_once;167 char first_vacc;168 char first_gacc;169 char first_macc;170 int vocc;171 int gocc;172 int mocc;173 char cur;174 char engine_en;175 char converged;176 int priority;177} nv3_arb_info;178typedef struct {179 int graphics_lwm;180 int video_lwm;181 int graphics_burst_size;182 int video_burst_size;183 int graphics_hi_priority;184 int media_hi_priority;185 int rtl_values;186 int valid;187} nv3_fifo_info;188typedef struct {189 char pix_bpp;190 char enable_video;191 char gr_during_vid;192 char enable_mp;193 int memory_width;194 int video_scale;195 int pclk_khz;196 int mclk_khz;197 int mem_page_miss;198 int mem_latency;199 char mem_aligned;200} nv3_sim_state;201typedef struct {202 int graphics_lwm;203 int video_lwm;204 int graphics_burst_size;205 int video_burst_size;206 int valid;207} nv4_fifo_info;208typedef struct {209 int pclk_khz;210 int mclk_khz;211 int nvclk_khz;212 char mem_page_miss;213 char mem_latency;214 int memory_width;215 char enable_video;216 char gr_during_vid;217 char pix_bpp;218 char mem_aligned;219 char enable_mp;220} nv4_sim_state;221typedef struct {222 int graphics_lwm;223 int video_lwm;224 int graphics_burst_size;225 int video_burst_size;226 int valid;227} nv10_fifo_info;228typedef struct {229 int pclk_khz;230 int mclk_khz;231 int nvclk_khz;232 char mem_page_miss;233 char mem_latency;234 u32 memory_type;235 int memory_width;236 char enable_video;237 char gr_during_vid;238 char pix_bpp;239 char mem_aligned;240 char enable_mp;241} nv10_sim_state;242static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)243{244 int iter = 0;245 int tmp;246 int vfsize, mfsize, gfsize;247 int mburst_size = 32;248 int mmisses, gmisses, vmisses;249 int misses;250 int vlwm, glwm;251 int last, next, cur;252 int max_gfsize ;253 long ns;254 255 vlwm = 0;256 glwm = 0;257 vfsize = 0;258 gfsize = 0;259 cur = ainfo->cur;260 mmisses = 2;261 gmisses = 2;262 vmisses = 2;263 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;264 else max_gfsize = GFIFO_SIZE;265 max_gfsize = GFIFO_SIZE;266 while (1)267 {268 if (ainfo->vid_en)269 {270 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;271 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;272 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;273 vfsize = ns * ainfo->vdrain_rate / 1000000;274 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;275 }276 if (state->enable_mp)277 {278 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;279 }280 if (ainfo->gr_en)281 {282 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;283 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;284 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;285 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;286 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;287 }288 mfsize = 0;289 if (!state->gr_during_vid && ainfo->vid_en)290 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)291 next = VIDEO;292 else if (ainfo->mocc < 0)293 next = MPORT;294 else if (ainfo->gocc< ainfo->by_gfacc)295 next = GRAPHICS;296 else return (0);297 else switch (ainfo->priority)298 {299 case VIDEO:300 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)301 next = VIDEO;302 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)303 next = GRAPHICS;304 else if (ainfo->mocc<0)305 next = MPORT;306 else return (0);307 break;308 case GRAPHICS:309 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)310 next = GRAPHICS;311 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)312 next = VIDEO;313 else if (ainfo->mocc<0)314 next = MPORT;315 else return (0);316 break;317 default:318 if (ainfo->mocc<0)319 next = MPORT;320 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)321 next = GRAPHICS;322 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)323 next = VIDEO;324 else return (0);325 break;326 }327 last = cur;328 cur = next;329 iter++;330 switch (cur)331 {332 case VIDEO:333 if (last==cur) misses = 0;334 else if (ainfo->first_vacc) misses = vmisses;335 else misses = 1;336 ainfo->first_vacc = 0;337 if (last!=cur)338 {339 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 340 vlwm = ns * ainfo->vdrain_rate/ 1000000;341 vlwm = ainfo->vocc - vlwm;342 }343 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;344 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;345 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;346 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;347 break;348 case GRAPHICS:349 if (last==cur) misses = 0;350 else if (ainfo->first_gacc) misses = gmisses;351 else misses = 1;352 ainfo->first_gacc = 0;353 if (last!=cur)354 {355 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;356 glwm = ns * ainfo->gdrain_rate/1000000;357 glwm = ainfo->gocc - glwm;358 }359 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;360 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;361 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;362 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;363 break;364 default:365 if (last==cur) misses = 0;366 else if (ainfo->first_macc) misses = mmisses;367 else misses = 1;368 ainfo->first_macc = 0;369 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;370 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;371 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;372 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;373 break;374 }375 if (iter>100)376 {377 ainfo->converged = 0;378 return (1);379 }380 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;381 tmp = ns * ainfo->gdrain_rate/1000000;382 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)383 {384 ainfo->converged = 0;385 return (1);386 }387 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;388 tmp = ns * ainfo->vdrain_rate/1000000;389 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)390 {391 ainfo->converged = 0;392 return (1);393 }394 if (abs(ainfo->gocc) > max_gfsize)395 {396 ainfo->converged = 0;397 return (1);398 }399 if (abs(ainfo->vocc) > VFIFO_SIZE)400 {401 ainfo->converged = 0;402 return (1);403 }404 if (abs(ainfo->mocc) > MFIFO_SIZE)405 {406 ainfo->converged = 0;407 return (1);408 }409 if (abs(vfsize) > VFIFO_SIZE)410 {411 ainfo->converged = 0;412 return (1);413 }414 if (abs(gfsize) > max_gfsize)415 {416 ainfo->converged = 0;417 return (1);418 }419 if (abs(mfsize) > MFIFO_SIZE)420 {421 ainfo->converged = 0;422 return (1);423 }424 }425}426static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 427{428 long ens, vns, mns, gns;429 int mmisses, gmisses, vmisses, eburst_size, mburst_size;430 int refresh_cycle;431 432 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;433 mmisses = 2;434 if (state->mem_aligned) gmisses = 2;435 else gmisses = 3;436 vmisses = 2;437 eburst_size = state->memory_width * 1;438 mburst_size = 32;439 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;440 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;441 ainfo->wcmocc = 0;442 ainfo->wcgocc = 0;443 ainfo->wcvocc = 0;444 ainfo->wcvlwm = 0;445 ainfo->wcglwm = 0;446 ainfo->engine_en = 1;447 ainfo->converged = 1;448 if (ainfo->engine_en)449 {450 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;451 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;452 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;453 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;454 ainfo->cur = ENGINE;455 ainfo->first_vacc = 1;456 ainfo->first_gacc = 1;457 ainfo->first_macc = 1;458 nv3_iterate(res_info, state,ainfo);459 }460 if (state->enable_mp)461 {462 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;463 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;464 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;465 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;466 ainfo->cur = MPORT;467 ainfo->first_vacc = 1;468 ainfo->first_gacc = 1;469 ainfo->first_macc = 0;470 nv3_iterate(res_info, state,ainfo);471 }472 if (ainfo->gr_en)473 {474 ainfo->first_vacc = 1;475 ainfo->first_gacc = 0;476 ainfo->first_macc = 1;477 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;478 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;479 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;480 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;481 ainfo->cur = GRAPHICS;482 nv3_iterate(res_info, state,ainfo);483 }484 if (ainfo->vid_en)485 {486 ainfo->first_vacc = 0;487 ainfo->first_gacc = 1;488 ainfo->first_macc = 1;489 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;490 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;491 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;492 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;493 ainfo->cur = VIDEO;494 nv3_iterate(res_info, state, ainfo);495 }496 if (ainfo->converged)497 {498 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;499 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;500 res_info->graphics_burst_size = ainfo->gburst_size;501 res_info->video_burst_size = ainfo->vburst_size;502 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);503 res_info->media_hi_priority = (ainfo->priority == MPORT);504 if (res_info->video_lwm > 160)505 {506 res_info->graphics_lwm = 256;507 res_info->video_lwm = 128;508 res_info->graphics_burst_size = 64;509 res_info->video_burst_size = 64;510 res_info->graphics_hi_priority = 0;511 res_info->media_hi_priority = 0;512 ainfo->converged = 0;513 return (0);514 }515 if (res_info->video_lwm > 128)516 {517 res_info->video_lwm = 128;518 }519 return (1);520 }521 else522 {523 res_info->graphics_lwm = 256;524 res_info->video_lwm = 128;525 res_info->graphics_burst_size = 64;526 res_info->video_burst_size = 64;527 res_info->graphics_hi_priority = 0;528 res_info->media_hi_priority = 0;529 return (0);530 }531}532static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)533{534 int done, g,v, p;535 536 done = 0;537 for (p=0; p < 2; p++)538 {539 for (g=128 ; g > 32; g= g>> 1)540 {541 for (v=128; v >=32; v = v>> 1)542 {543 ainfo->priority = p;544 ainfo->gburst_size = g; 545 ainfo->vburst_size = v;546 done = nv3_arb(res_info, state,ainfo);547 if (done && (g==128))548 if ((res_info->graphics_lwm + g) > 256)549 done = 0;550 if (done)551 goto Done;552 }553 }554 }555 556 Done:557 return done;558}559static void nv3CalcArbitration 560(561 nv3_fifo_info * res_info,562 nv3_sim_state * state563)564{565 nv3_fifo_info save_info;566 nv3_arb_info ainfo;567 char res_gr, res_vid;568 569 ainfo.gr_en = 1;570 ainfo.vid_en = state->enable_video;571 ainfo.vid_only_once = 0;572 ainfo.gr_only_once = 0;573 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);574 ainfo.vdrain_rate = (int) state->pclk_khz * 2;575 if (state->video_scale != 0)576 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;577 ainfo.mdrain_rate = 33000;578 res_info->rtl_values = 0;579 if (!state->gr_during_vid && state->enable_video)580 {581 ainfo.gr_only_once = 1;582 ainfo.gr_en = 1;583 ainfo.gdrain_rate = 0;584 res_vid = nv3_get_param(res_info, state, &ainfo);585 res_vid = ainfo.converged;586 save_info.video_lwm = res_info->video_lwm;587 save_info.video_burst_size = res_info->video_burst_size;588 ainfo.vid_en = 1;589 ainfo.vid_only_once = 1;590 ainfo.gr_en = 1;591 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);592 ainfo.vdrain_rate = 0;593 res_gr = nv3_get_param(res_info, state, &ainfo);594 res_gr = ainfo.converged;595 res_info->video_lwm = save_info.video_lwm;596 res_info->video_burst_size = save_info.video_burst_size;597 res_info->valid = res_gr & res_vid;598 }599 else600 {601 if (!ainfo.gr_en) ainfo.gdrain_rate = 0;602 if (!ainfo.vid_en) ainfo.vdrain_rate = 0;603 res_gr = nv3_get_param(res_info, state, &ainfo);604 res_info->valid = ainfo.converged;605 }606}607static void nv3UpdateArbitrationSettings608(609 unsigned VClk, 610 unsigned pixelDepth, 611 unsigned *burst,612 unsigned *lwm,613 RIVA_HW_INST *chip614)615{616 nv3_fifo_info fifo_data;617 nv3_sim_state sim_data;618 unsigned int M, N, P, pll, MClk;619 620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);621 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;622 MClk = (N * chip->CrystalFreqKHz / M) >> P;623 sim_data.pix_bpp = (char)pixelDepth;624 sim_data.enable_video = 0;625 sim_data.enable_mp = 0;626 sim_data.video_scale = 1;627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?628 128 : 64;629 sim_data.memory_width = 128;630 631 sim_data.mem_latency = 9;632 sim_data.mem_aligned = 1;633 sim_data.mem_page_miss = 11;634 sim_data.gr_during_vid = 0;635 sim_data.pclk_khz = VClk;636 sim_data.mclk_khz = MClk;637 nv3CalcArbitration(&fifo_data, &sim_data);638 if (fifo_data.valid)639 {640 int b = fifo_data.graphics_burst_size >> 4;641 *burst = 0;642 while (b >>= 1)643 (*burst)++;644 *lwm = fifo_data.graphics_lwm >> 3;645 }646 else647 {648 *lwm = 0x24;649 *burst = 0x2;650 }651}652static void nv4CalcArbitration 653(654 nv4_fifo_info *fifo,655 nv4_sim_state *arb656)657{658 int data, pagemiss, cas,width, video_enable, bpp;659 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;660 int found, mclk_extra, mclk_loop, cbs, m1, p1;661 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;662 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;663 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;664 665 fifo->valid = 1;666 pclk_freq = arb->pclk_khz;667 mclk_freq = arb->mclk_khz;668 nvclk_freq = arb->nvclk_khz;669 pagemiss = arb->mem_page_miss;670 cas = arb->mem_latency;671 width = arb->memory_width >> 6;672 video_enable = arb->enable_video;673 bpp = arb->pix_bpp;674 mp_enable = arb->enable_mp;675 clwm = 0;676 vlwm = 0;677 cbs = 128;678 pclks = 2;679 nvclks = 2;680 nvclks += 2;681 nvclks += 1;682 mclks = 5;683 mclks += 3;684 mclks += 1;685 mclks += cas;686 mclks += 1;687 mclks += 1;688 mclks += 1;689 mclks += 1;690 mclk_extra = 3;691 nvclks += 2;692 nvclks += 1;693 nvclks += 1;694 nvclks += 1;695 if (mp_enable)696 mclks+=4;697 nvclks += 0;698 pclks += 0;699 found = 0;700 vbs = 0;701 while (found != 1)702 {703 fifo->valid = 1;704 found = 1;705 mclk_loop = mclks+mclk_extra;706 us_m = mclk_loop *1000*1000 / mclk_freq;707 us_n = nvclks*1000*1000 / nvclk_freq;708 us_p = nvclks*1000*1000 / pclk_freq;709 if (video_enable)710 {711 video_drain_rate = pclk_freq * 2;712 crtc_drain_rate = pclk_freq * bpp/8;713 vpagemiss = 2;714 vpagemiss += 1;715 crtpagemiss = 2;716 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;717 if (nvclk_freq * 2 > mclk_freq * width)718 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;719 else720 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;721 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;722 vlwm = us_video * video_drain_rate/(1000*1000);723 vlwm++;724 vbs = 128;725 if (vlwm > 128) vbs = 64;726 if (vlwm > (256-64)) vbs = 32;727 if (nvclk_freq * 2 > mclk_freq * width)728 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;729 else730 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;731 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;732 us_crt =733 us_video734 +video_fill_us735 +cpm_us736 +us_m + us_n +us_p737 ;738 clwm = us_crt * crtc_drain_rate/(1000*1000);739 clwm++;740 }741 else742 {743 crtc_drain_rate = pclk_freq * bpp/8;744 crtpagemiss = 2;745 crtpagemiss += 1;746 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;747 us_crt = cpm_us + us_m + us_n + us_p ;748 clwm = us_crt * crtc_drain_rate/(1000*1000);749 clwm++;750 }751 m1 = clwm + cbs - 512;752 p1 = m1 * pclk_freq / mclk_freq;753 p1 = p1 * bpp / 8;754 if ((p1 < m1) && (m1 > 0))755 {756 fifo->valid = 0;757 found = 0;758 if (mclk_extra ==0) found = 1;759 mclk_extra--;760 }761 else if (video_enable)762 {763 if ((clwm > 511) || (vlwm > 255))764 {765 fifo->valid = 0;766 found = 0;767 if (mclk_extra ==0) found = 1;768 mclk_extra--;769 }770 }771 else772 {773 if (clwm > 519)774 {775 fifo->valid = 0;776 found = 0;777 if (mclk_extra ==0) found = 1;778 mclk_extra--;779 }780 }781 if (clwm < 384) clwm = 384;782 if (vlwm < 128) vlwm = 128;783 data = (int)(clwm);784 fifo->graphics_lwm = data;785 fifo->graphics_burst_size = 128;786 data = (int)((vlwm+15));787 fifo->video_lwm = data;788 fifo->video_burst_size = vbs;789 }790}791static void nv4UpdateArbitrationSettings792(793 unsigned VClk, 794 unsigned pixelDepth, 795 unsigned *burst,796 unsigned *lwm,797 RIVA_HW_INST *chip798)799{800 nv4_fifo_info fifo_data;801 nv4_sim_state sim_data;802 unsigned int M, N, P, pll, MClk, NVClk, cfg1;803 804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);805 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;806 MClk = (N * chip->CrystalFreqKHz / M) >> P;807 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);808 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;809 NVClk = (N * chip->CrystalFreqKHz / M) >> P;810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);811 sim_data.pix_bpp = (char)pixelDepth;812 sim_data.enable_video = 0;813 sim_data.enable_mp = 0;814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?815 128 : 64;816 sim_data.mem_latency = (char)cfg1 & 0x0F;817 sim_data.mem_aligned = 1;818 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));819 sim_data.gr_during_vid = 0;820 sim_data.pclk_khz = VClk;821 sim_data.mclk_khz = MClk;822 sim_data.nvclk_khz = NVClk;823 nv4CalcArbitration(&fifo_data, &sim_data);824 if (fifo_data.valid)825 {826 int b = fifo_data.graphics_burst_size >> 4;827 *burst = 0;828 while (b >>= 1)829 (*burst)++;830 *lwm = fifo_data.graphics_lwm >> 3;831 }832}833static void nv10CalcArbitration 834(835 nv10_fifo_info *fifo,836 nv10_sim_state *arb837)838{839 int data, pagemiss, width, video_enable, bpp;840 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;841 int nvclk_fill;842 int found, mclk_extra, mclk_loop, cbs, m1;843 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;844 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;845 int vus_m;846 int vpm_us, us_video, cpm_us, us_crt,clwm;847 int clwm_rnd_down;848 int m2us, us_pipe_min, p1clk, p2;849 int min_mclk_extra;850 int us_min_mclk_extra;851 852 fifo->valid = 1;853 pclk_freq = arb->pclk_khz; /* freq in KHz */854 mclk_freq = arb->mclk_khz;855 nvclk_freq = arb->nvclk_khz;856 pagemiss = arb->mem_page_miss;857 width = arb->memory_width/64;858 video_enable = arb->enable_video;859 bpp = arb->pix_bpp;860 mp_enable = arb->enable_mp;861 clwm = 0;862 863 cbs = 512;864 865 pclks = 4; /* lwm detect. */866 867 nvclks = 3; /* lwm -> sync. */868 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */869 870 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */871 872 mclks += 1; /* arb_hp_req */873 mclks += 5; /* ap_hp_req tiling pipeline */874 875 mclks += 2; /* tc_req latency fifo */876 mclks += 2; /* fb_cas_n_ memory request to fbio block */877 mclks += 7; /* sm_d_rdv data returned from fbio block */878 879 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */880 if (arb->memory_type == 0)881 if (arb->memory_width == 64) /* 64 bit bus */882 mclks += 4;883 else884 mclks += 2;885 else886 if (arb->memory_width == 64) /* 64 bit bus */887 mclks += 2;888 else889 mclks += 1;890 891 if ((!video_enable) && (arb->memory_width == 128))892 { 893 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */894 min_mclk_extra = 17;895 }896 else897 {898 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */899 /* mclk_extra = 4; */ /* Margin of error */900 min_mclk_extra = 18;901 }902 903 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */904 nvclks += 1; /* fbi_d_rdv_n */905 nvclks += 1; /* Fbi_d_rdata */906 nvclks += 1; /* crtfifo load */907 908 if(mp_enable)909 mclks+=4; /* Mp can get in with a burst of 8. */910 /* Extra clocks determined by heuristics */911 912 nvclks += 0;913 pclks += 0;914 found = 0;915 while(found != 1) {916 fifo->valid = 1;917 found = 1;918 mclk_loop = mclks+mclk_extra;919 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */920 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */921 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;922 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */923 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */924 us_pipe_min = us_m_min + us_n + us_p;925 926 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */927 928 if(video_enable) {929 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */930 931 vpagemiss = 1; /* self generating page miss */932 vpagemiss += 1; /* One higher priority before */933 934 crtpagemiss = 2; /* self generating page miss */935 if(mp_enable)936 crtpagemiss += 1; /* if MA0 conflict */937 938 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;939 940 us_video = vpm_us + vus_m; /* Video has separate read return path */941 942 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;943 us_crt =944 us_video /* Wait for video */945 +cpm_us /* CRT Page miss */946 +us_m + us_n +us_p /* other latency */947 ;948 949 clwm = us_crt * crtc_drain_rate/(1000*1000);950 clwm++; /* fixed point <= float_point - 1. Fixes that */951 } else {952 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */953 954 crtpagemiss = 1; /* self generating page miss */955 crtpagemiss += 1; /* MA0 page miss */956 if(mp_enable)957 crtpagemiss += 1; /* if MA0 conflict */958 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;959 us_crt = cpm_us + us_m + us_n + us_p ;960 clwm = us_crt * crtc_drain_rate/(1000*1000);961 clwm++; /* fixed point <= float_point - 1. Fixes that */962 963 /*964 //965 // Another concern, only for high pclks so don't do this966 // with video:967 // What happens if the latency to fetch the cbs is so large that968 // fifo empties. In that case we need to have an alternate clwm value969 // based off the total burst fetch970 //971 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;972 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;973 clwm_mt = us_crt * crtc_drain_rate/(1000*1000);974 clwm_mt ++;975 if(clwm_mt > clwm)976 clwm = clwm_mt;977 */978 /* Finally, a heuristic check when width == 64 bits */979 if(width == 1){980 nvclk_fill = nvclk_freq * 8;981 if(crtc_drain_rate * 100 >= nvclk_fill * 102)982 clwm = 0xfff; /*Large number to fail */983 984 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {985 clwm = 1024;986 cbs = 512;987 }988 }989 }990 991 992 /*993 Overfill check:994 995 */996 997 clwm_rnd_down = ((int)clwm/8)*8;998 if (clwm_rnd_down < clwm)999 clwm += 8;1000 1001 m1 = clwm + cbs - 1024; /* Amount of overfill */1002 m2us = us_pipe_min + us_min_mclk_extra;1003 1004 /* pclk cycles to drain */1005 p1clk = m2us * pclk_freq/(1000*1000); 1006 p2 = p1clk * bpp / 8; /* bytes drained. */1007 1008 if((p2 < m1) && (m1 > 0)) {1009 fifo->valid = 0;1010 found = 0;1011 if(min_mclk_extra == 0) {1012 if(cbs <= 32) {1013 found = 1; /* Can't adjust anymore! */1014 } else {1015 cbs = cbs/2; /* reduce the burst size */1016 }1017 } else {1018 min_mclk_extra--;1019 }1020 } else {1021 if (clwm > 1023){ /* Have some margin */1022 fifo->valid = 0;1023 found = 0;1024 if(min_mclk_extra == 0) 1025 found = 1; /* Can't adjust anymore! */1026 else 1027 min_mclk_extra--;1028 }1029 }1030 1031 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;1032 data = (int)(clwm);1033 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */1034 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;1035 1036 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */1037 fifo->video_lwm = 1024; fifo->video_burst_size = 512;1038 }1039}1040static void nv10UpdateArbitrationSettings1041(1042 unsigned VClk, 1043 unsigned pixelDepth, 1044 unsigned *burst,1045 unsigned *lwm,1046 RIVA_HW_INST *chip1047)1048{1049 nv10_fifo_info fifo_data;1050 nv10_sim_state sim_data;1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1;1052 1053 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);1054 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;1055 MClk = (N * chip->CrystalFreqKHz / M) >> P;1056 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);1057 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;1058 NVClk = (N * chip->CrystalFreqKHz / M) >> P;1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);1060 sim_data.pix_bpp = (char)pixelDepth;1061 sim_data.enable_video = 0;1062 sim_data.enable_mp = 0;1063 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?1064 1 : 0;1065 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?1066 128 : 64;1067 sim_data.mem_latency = (char)cfg1 & 0x0F;1068 sim_data.mem_aligned = 1;1069 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));1070 sim_data.gr_during_vid = 0;1071 sim_data.pclk_khz = VClk;1072 sim_data.mclk_khz = MClk;1073 sim_data.nvclk_khz = NVClk;1074 nv10CalcArbitration(&fifo_data, &sim_data);1075 if (fifo_data.valid)1076 {1077 int b = fifo_data.graphics_burst_size >> 4;1078 *burst = 0;1079 while (b >>= 1)1080 (*burst)++;1081 *lwm = fifo_data.graphics_lwm >> 3;1082 }1083}1084 1085static void nForceUpdateArbitrationSettings1086(1087 unsigned VClk,1088 unsigned pixelDepth,1089 unsigned *burst,1090 unsigned *lwm,1091 RIVA_HW_INST *chip,1092 struct pci_dev *pdev1093)1094{1095 nv10_fifo_info fifo_data;1096 nv10_sim_state sim_data;1097 unsigned int M, N, P, pll, MClk, NVClk;1098 unsigned int uMClkPostDiv;1099 struct pci_dev *dev;1100 int domain = pci_domain_nr(pdev->bus);1101 1102 dev = pci_get_domain_bus_and_slot(domain, 0, 3);1103 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);1104 pci_dev_put(dev);1105 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;1106 1107 if(!uMClkPostDiv) uMClkPostDiv = 4;1108 MClk = 400000 / uMClkPostDiv;1109 1110 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);1111 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;1112 NVClk = (N * chip->CrystalFreqKHz / M) >> P;1113 sim_data.pix_bpp = (char)pixelDepth;1114 sim_data.enable_video = 0;1115 sim_data.enable_mp = 0;1116 1117 dev = pci_get_domain_bus_and_slot(domain, 0, 1);1118 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);1119 pci_dev_put(dev);1120 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;1121 1122 sim_data.memory_width = 64;1123 sim_data.mem_latency = 3;1124 sim_data.mem_aligned = 1;1125 sim_data.mem_page_miss = 10;1126 sim_data.gr_during_vid = 0;1127 sim_data.pclk_khz = VClk;1128 sim_data.mclk_khz = MClk;1129 sim_data.nvclk_khz = NVClk;1130 nv10CalcArbitration(&fifo_data, &sim_data);1131 if (fifo_data.valid)1132 {1133 int b = fifo_data.graphics_burst_size >> 4;1134 *burst = 0;1135 while (b >>= 1)1136 (*burst)++;1137 *lwm = fifo_data.graphics_lwm >> 3;1138 }1139}1140 1141/****************************************************************************\1142* *1143* RIVA Mode State Routines *1144* *1145\****************************************************************************/1146 1147/*1148 * Calculate the Video Clock parameters for the PLL.1149 */1150static int CalcVClock1151(1152 int clockIn,1153 int *clockOut,1154 int *mOut,1155 int *nOut,1156 int *pOut,1157 RIVA_HW_INST *chip1158)1159{1160 unsigned lowM, highM, highP;1161 unsigned DeltaNew, DeltaOld;1162 unsigned VClk, Freq;1163 unsigned M, N, P;1164 1165 DeltaOld = 0xFFFFFFFF;1166 1167 VClk = (unsigned)clockIn;1168 1169 if (chip->CrystalFreqKHz == 13500)1170 {1171 lowM = 7;1172 highM = 13 - (chip->Architecture == NV_ARCH_03);1173 }1174 else1175 {1176 lowM = 8;1177 highM = 14 - (chip->Architecture == NV_ARCH_03);1178 } 1179 1180 highP = 4 - (chip->Architecture == NV_ARCH_03);1181 for (P = 0; P <= highP; P ++)1182 {1183 Freq = VClk << P;1184 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))1185 {1186 for (M = lowM; M <= highM; M++)1187 {1188 N = (VClk << P) * M / chip->CrystalFreqKHz;1189 if(N <= 255) {1190 Freq = (chip->CrystalFreqKHz * N / M) >> P;1191 if (Freq > VClk)1192 DeltaNew = Freq - VClk;1193 else1194 DeltaNew = VClk - Freq;1195 if (DeltaNew < DeltaOld)1196 {1197 *mOut = M;1198 *nOut = N;1199 *pOut = P;1200 *clockOut = Freq;1201 DeltaOld = DeltaNew;1202 }1203 }1204 }1205 }1206 }1207 1208 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */1209 return (DeltaOld != 0xFFFFFFFF);1210}1211/*1212 * Calculate extended mode parameters (SVGA) and save in a 1213 * mode state structure.1214 */1215int CalcStateExt1216(1217 RIVA_HW_INST *chip,1218 RIVA_HW_STATE *state,1219 struct pci_dev *pdev,1220 int bpp,1221 int width,1222 int hDisplaySize,1223 int height,1224 int dotClock1225)1226{1227 int pixelDepth;1228 int VClk, m, n, p;1229 1230 /*1231 * Save mode parameters.1232 */1233 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */1234 state->width = width;1235 state->height = height;1236 /*1237 * Extended RIVA registers.1238 */1239 pixelDepth = (bpp + 1)/8;1240 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))1241 return -EINVAL;1242 1243 switch (chip->Architecture)1244 {1245 case NV_ARCH_03:1246 nv3UpdateArbitrationSettings(VClk, 1247 pixelDepth * 8, 1248 &(state->arbitration0),1249 &(state->arbitration1),1250 chip);1251 state->cursor0 = 0x00;1252 state->cursor1 = 0x78;1253 state->cursor2 = 0x00000000;1254 state->pllsel = 0x10010100;1255 state->config = ((width + 31)/32)1256 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)1257 | 0x1000;1258 state->general = 0x00100100;1259 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;1260 break;1261 case NV_ARCH_04:1262 nv4UpdateArbitrationSettings(VClk, 1263 pixelDepth * 8, 1264 &(state->arbitration0),1265 &(state->arbitration1),1266 chip);1267 state->cursor0 = 0x00;1268 state->cursor1 = 0xFC;1269 state->cursor2 = 0x00000000;1270 state->pllsel = 0x10000700;1271 state->config = 0x00001114;1272 state->general = bpp == 16 ? 0x00101100 : 0x00100100;1273 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;1274 break;1275 case NV_ARCH_10:1276 case NV_ARCH_20:1277 case NV_ARCH_30:1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||1279 (chip->Chipset == NV_CHIP_0x01F0))1280 {1281 nForceUpdateArbitrationSettings(VClk,1282 pixelDepth * 8,1283 &(state->arbitration0),1284 &(state->arbitration1),1285 chip, pdev);1286 } else {1287 nv10UpdateArbitrationSettings(VClk, 1288 pixelDepth * 8, 1289 &(state->arbitration0),1290 &(state->arbitration1),1291 chip);1292 }1293 state->cursor0 = 0x80 | (chip->CursorStart >> 17);1294 state->cursor1 = (chip->CursorStart >> 11) << 2;1295 state->cursor2 = chip->CursorStart >> 24;1296 state->pllsel = 0x10000700;1297 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);1298 state->general = bpp == 16 ? 0x00101100 : 0x00100100;1299 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;1300 break;1301 }1302 1303 /* Paul Richards: below if block borks things in kernel for some reason */1304 /* Tony: Below is needed to set hardware in DirectColor */1305 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))1306 state->general |= 0x00000030;1307 1308 state->vpll = (p << 16) | (n << 8) | m;1309 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;1310 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;1311 state->offset0 =1312 state->offset1 =1313 state->offset2 =1314 state->offset3 = 0;1315 state->pitch0 =1316 state->pitch1 =1317 state->pitch2 =1318 state->pitch3 = pixelDepth * width;1319 1320 return 0;1321}1322/*1323 * Load fixed function state and pre-calculated/stored state.1324 */1325#define LOAD_FIXED_STATE(tbl,dev) \1326 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \1327 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])1328#define LOAD_FIXED_STATE_8BPP(tbl,dev) \1329 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \1330 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])1331#define LOAD_FIXED_STATE_15BPP(tbl,dev) \1332 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \1333 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])1334#define LOAD_FIXED_STATE_16BPP(tbl,dev) \1335 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \1336 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])1337#define LOAD_FIXED_STATE_32BPP(tbl,dev) \1338 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \1339 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])1340 1341static void UpdateFifoState1342(1343 RIVA_HW_INST *chip1344)1345{1346 int i;1347 1348 switch (chip->Architecture)1349 {1350 case NV_ARCH_04:1351 LOAD_FIXED_STATE(nv4,FIFO);1352 chip->Tri03 = NULL;1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);1354 break;1355 case NV_ARCH_10:1356 case NV_ARCH_20:1357 case NV_ARCH_30:1358 /*1359 * Initialize state for the RivaTriangle3D05 routines.1360 */1361 LOAD_FIXED_STATE(nv10tri05,PGRAPH);1362 LOAD_FIXED_STATE(nv10,FIFO);1363 chip->Tri03 = NULL;1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);1365 break;1366 }1367}1368static void LoadStateExt1369(1370 RIVA_HW_INST *chip,1371 RIVA_HW_STATE *state1372)1373{1374 int i;1375 1376 /*1377 * Load HW fixed function state.1378 */1379 LOAD_FIXED_STATE(Riva,PMC);1380 LOAD_FIXED_STATE(Riva,PTIMER);1381 switch (chip->Architecture)1382 {1383 case NV_ARCH_03:1384 /*1385 * Make sure frame buffer config gets set before loading PRAMIN.1386 */1387 NV_WR32(chip->PFB, 0x00000200, state->config);1388 LOAD_FIXED_STATE(nv3,PFIFO);1389 LOAD_FIXED_STATE(nv3,PRAMIN);1390 LOAD_FIXED_STATE(nv3,PGRAPH);1391 switch (state->bpp)1392 {1393 case 15:1394 case 16:1395 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);1396 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);1398 break;1399 case 24:1400 case 32:1401 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);1402 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);1403 chip->Tri03 = NULL;1404 break;1405 case 8:1406 default:1407 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);1408 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);1409 chip->Tri03 = NULL;1410 break;1411 }1412 for (i = 0x00000; i < 0x00800; i++)1413 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);1414 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);1415 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);1416 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);1417 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);1418 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);1419 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);1420 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);1421 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);1422 break;1423 case NV_ARCH_04:1424 /*1425 * Make sure frame buffer config gets set before loading PRAMIN.1426 */1427 NV_WR32(chip->PFB, 0x00000200, state->config);1428 LOAD_FIXED_STATE(nv4,PFIFO);1429 LOAD_FIXED_STATE(nv4,PRAMIN);1430 LOAD_FIXED_STATE(nv4,PGRAPH);1431 switch (state->bpp)1432 {1433 case 15:1434 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);1435 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);1437 break;1438 case 16:1439 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);1440 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);1442 break;1443 case 24:1444 case 32:1445 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);1446 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);1447 chip->Tri03 = NULL;1448 break;1449 case 8:1450 default:1451 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);1452 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);1453 chip->Tri03 = NULL;1454 break;1455 }1456 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);1457 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);1458 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);1459 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);1460 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);1461 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);1462 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);1463 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);1464 break;1465 case NV_ARCH_10:1466 case NV_ARCH_20:1467 case NV_ARCH_30:1468 if(chip->twoHeads) {1469 VGA_WR08(chip->PCIO, 0x03D4, 0x44);1470 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);1471 chip->LockUnlock(chip, 0);1472 }1473 1474 LOAD_FIXED_STATE(nv10,PFIFO);1475 LOAD_FIXED_STATE(nv10,PRAMIN);1476 LOAD_FIXED_STATE(nv10,PGRAPH);1477 switch (state->bpp)1478 {1479 case 15:1480 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);1481 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);1483 break;1484 case 16:1485 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);1486 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);1488 break;1489 case 24:1490 case 32:1491 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);1492 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);1493 chip->Tri03 = NULL;1494 break;1495 case 8:1496 default:1497 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);1498 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);1499 chip->Tri03 = NULL;1500 break;1501 }1502 1503 if(chip->Architecture == NV_ARCH_10) {1504 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);1505 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);1506 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);1507 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);1508 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);1509 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);1510 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);1511 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);1512 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);1513 } else {1514 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);1515 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);1516 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);1517 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);1518 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);1519 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);1520 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);1521 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);1522 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);1523 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);1524 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));1525 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));1526 }1527 if(chip->twoHeads) {1528 NV_WR32(chip->PCRTC0, 0x00000860, state->head);1529 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);1530 }1531 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));1532 1533 NV_WR32(chip->PMC, 0x00008704, 1);1534 NV_WR32(chip->PMC, 0x00008140, 0);1535 NV_WR32(chip->PMC, 0x00008920, 0);1536 NV_WR32(chip->PMC, 0x00008924, 0);1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);1539 NV_WR32(chip->PMC, 0x00001588, 0);1540 1541 NV_WR32(chip->PFB, 0x00000240, 0);1542 NV_WR32(chip->PFB, 0x00000250, 0);1543 NV_WR32(chip->PFB, 0x00000260, 0);1544 NV_WR32(chip->PFB, 0x00000270, 0);1545 NV_WR32(chip->PFB, 0x00000280, 0);1546 NV_WR32(chip->PFB, 0x00000290, 0);1547 NV_WR32(chip->PFB, 0x000002A0, 0);1548 NV_WR32(chip->PFB, 0x000002B0, 0);1549 1550 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));1551 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));1552 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));1553 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));1554 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));1555 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));1556 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));1557 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));1558 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));1559 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));1560 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));1561 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));1562 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));1563 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));1564 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));1565 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));1566 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));1567 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));1568 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));1569 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));1570 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));1571 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));1572 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));1573 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));1574 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));1575 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));1576 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));1577 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));1578 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));1579 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));1580 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));1581 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));1582 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);1583 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);1584 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);1585 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);1586 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);1587 for (i = 0; i < (3*16); i++)1588 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1589 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);1590 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1591 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);1592 for (i = 0; i < (16*16); i++)1593 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1594 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);1595 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);1596 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);1597 for (i = 0; i < (59*4); i++)1598 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1599 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);1600 for (i = 0; i < (47*4); i++)1601 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1602 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);1603 for (i = 0; i < (3*4); i++)1604 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1605 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);1606 for (i = 0; i < (19*4); i++)1607 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);1609 for (i = 0; i < (12*4); i++)1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);1612 for (i = 0; i < (12*4); i++)1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);1615 for (i = 0; i < (8*4); i++)1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);1618 for (i = 0; i < 16; i++)1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);1621 for (i = 0; i < 4; i++)1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);1623 1624 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);1625 1626 if(chip->flatPanel) {1627 if((chip->Chipset & 0x0ff0) == 0x0110) {1628 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);1629 } else 1630 if((chip->Chipset & 0x0ff0) >= 0x0170) {1631 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);1632 }1633 1634 VGA_WR08(chip->PCIO, 0x03D4, 0x53);1635 VGA_WR08(chip->PCIO, 0x03D5, 0);1636 VGA_WR08(chip->PCIO, 0x03D4, 0x54);1637 VGA_WR08(chip->PCIO, 0x03D5, 0);1638 VGA_WR08(chip->PCIO, 0x03D4, 0x21);1639 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);1640 }1641 1642 VGA_WR08(chip->PCIO, 0x03D4, 0x41);1643 VGA_WR08(chip->PCIO, 0x03D5, state->extra);1644 }1645 LOAD_FIXED_STATE(Riva,FIFO);1646 UpdateFifoState(chip);1647 /*1648 * Load HW mode state.1649 */1650 VGA_WR08(chip->PCIO, 0x03D4, 0x19);1651 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);1652 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);1653 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);1654 VGA_WR08(chip->PCIO, 0x03D4, 0x25);1655 VGA_WR08(chip->PCIO, 0x03D5, state->screen);1656 VGA_WR08(chip->PCIO, 0x03D4, 0x28);1657 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);1658 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);1659 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);1660 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);1661 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);1662 VGA_WR08(chip->PCIO, 0x03D4, 0x20);1663 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);1664 VGA_WR08(chip->PCIO, 0x03D4, 0x30);1665 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);1666 VGA_WR08(chip->PCIO, 0x03D4, 0x31);1667 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);1668 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);1669 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);1670 VGA_WR08(chip->PCIO, 0x03D4, 0x39);1671 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);1672 1673 if(!chip->flatPanel) {1674 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);1675 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);1676 if(chip->twoHeads)1677 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);1678 } else {1679 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);1680 } 1681 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);1682 1683 /*1684 * Turn off VBlank enable and reset.1685 */1686 NV_WR32(chip->PCRTC, 0x00000140, 0);1687 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);1688 /*1689 * Set interrupt enable.1690 */ 1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);1692 /*1693 * Set current state pointer.1694 */1695 chip->CurrentState = state;1696 /*1697 * Reset FIFO free and empty counts.1698 */1699 chip->FifoFreeCount = 0;1700 /* Free count from first subchannel */1701 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);1702}1703static void UnloadStateExt1704(1705 RIVA_HW_INST *chip,1706 RIVA_HW_STATE *state1707)1708{1709 /*1710 * Save current HW state.1711 */1712 VGA_WR08(chip->PCIO, 0x03D4, 0x19);1713 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);1714 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);1715 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);1716 VGA_WR08(chip->PCIO, 0x03D4, 0x25);1717 state->screen = VGA_RD08(chip->PCIO, 0x03D5);1718 VGA_WR08(chip->PCIO, 0x03D4, 0x28);1719 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);1720 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);1721 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);1722 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);1723 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);1724 VGA_WR08(chip->PCIO, 0x03D4, 0x20);1725 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);1726 VGA_WR08(chip->PCIO, 0x03D4, 0x30);1727 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);1728 VGA_WR08(chip->PCIO, 0x03D4, 0x31);1729 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);1730 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);1731 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);1732 VGA_WR08(chip->PCIO, 0x03D4, 0x39);1733 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);1734 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);1735 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);1736 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);1737 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);1738 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);1739 state->config = NV_RD32(chip->PFB, 0x00000200);1740 switch (chip->Architecture)1741 {1742 case NV_ARCH_03:1743 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);1744 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);1745 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);1746 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);1747 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);1748 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);1749 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);1750 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);1751 break;1752 case NV_ARCH_04:1753 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);1754 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);1755 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);1756 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);1757 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);1758 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);1759 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);1760 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);1761 break;1762 case NV_ARCH_10:1763 case NV_ARCH_20:1764 case NV_ARCH_30:1765 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);1766 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);1767 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);1768 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);1769 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);1770 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);1771 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);1772 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);1773 if(chip->twoHeads) {1774 state->head = NV_RD32(chip->PCRTC0, 0x00000860);1775 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);1776 VGA_WR08(chip->PCIO, 0x03D4, 0x44);1777 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);1778 }1779 VGA_WR08(chip->PCIO, 0x03D4, 0x41);1780 state->extra = VGA_RD08(chip->PCIO, 0x03D5);1781 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);1782 1783 if((chip->Chipset & 0x0ff0) == 0x0110) {1784 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);1785 } else 1786 if((chip->Chipset & 0x0ff0) >= 0x0170) {1787 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);1788 }1789 break;1790 }1791}1792static void SetStartAddress1793(1794 RIVA_HW_INST *chip,1795 unsigned start1796)1797{1798 NV_WR32(chip->PCRTC, 0x800, start);1799}1800 1801static void SetStartAddress31802(1803 RIVA_HW_INST *chip,1804 unsigned start1805)1806{1807 int offset = start >> 2;1808 int pan = (start & 3) << 1;1809 unsigned char tmp;1810 1811 /*1812 * Unlock extended registers.1813 */1814 chip->LockUnlock(chip, 0);1815 /*1816 * Set start address.1817 */1818 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);1819 offset >>= 8;1820 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);1821 offset >>= 8;1822 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);1823 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));1824 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);1825 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));1826 /*1827 * 4 pixel pan register.1828 */1829 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);1830 VGA_WR08(chip->PCIO, 0x3C0, 0x13);1831 VGA_WR08(chip->PCIO, 0x3C0, pan);1832}1833static void nv3SetSurfaces2D1834(1835 RIVA_HW_INST *chip,1836 unsigned surf0,1837 unsigned surf11838)1839{1840 RivaSurface __iomem *Surface =1841 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);1842 1843 RIVA_FIFO_FREE(*chip,Tri03,5);1844 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);1845 NV_WR32(&Surface->Offset, 0, surf0);1846 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);1847 NV_WR32(&Surface->Offset, 0, surf1);1848 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);1849}1850static void nv4SetSurfaces2D1851(1852 RIVA_HW_INST *chip,1853 unsigned surf0,1854 unsigned surf11855)1856{1857 RivaSurface __iomem *Surface =1858 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);1859 1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);1861 NV_WR32(&Surface->Offset, 0, surf0);1862 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);1863 NV_WR32(&Surface->Offset, 0, surf1);1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);1865}1866static void nv10SetSurfaces2D1867(1868 RIVA_HW_INST *chip,1869 unsigned surf0,1870 unsigned surf11871)1872{1873 RivaSurface __iomem *Surface =1874 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);1875 1876 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);1877 NV_WR32(&Surface->Offset, 0, surf0);1878 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);1879 NV_WR32(&Surface->Offset, 0, surf1);1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);1881}1882static void nv3SetSurfaces3D1883(1884 RIVA_HW_INST *chip,1885 unsigned surf0,1886 unsigned surf11887)1888{1889 RivaSurface __iomem *Surface =1890 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);1891 1892 RIVA_FIFO_FREE(*chip,Tri03,5);1893 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);1894 NV_WR32(&Surface->Offset, 0, surf0);1895 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);1896 NV_WR32(&Surface->Offset, 0, surf1);1897 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);1898}1899static void nv4SetSurfaces3D1900(1901 RIVA_HW_INST *chip,1902 unsigned surf0,1903 unsigned surf11904)1905{1906 RivaSurface __iomem *Surface =1907 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);1908 1909 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);1910 NV_WR32(&Surface->Offset, 0, surf0);1911 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);1912 NV_WR32(&Surface->Offset, 0, surf1);1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);1914}1915static void nv10SetSurfaces3D1916(1917 RIVA_HW_INST *chip,1918 unsigned surf0,1919 unsigned surf11920)1921{1922 RivaSurface3D __iomem *Surfaces3D =1923 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);1924 1925 RIVA_FIFO_FREE(*chip,Tri03,4);1926 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);1927 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0);1928 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1);1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);1930}1931 1932/****************************************************************************\1933* *1934* Probe RIVA Chip Configuration *1935* *1936\****************************************************************************/1937 1938static void nv3GetConfig1939(1940 RIVA_HW_INST *chip1941)1942{1943 /*1944 * Fill in chip configuration.1945 */1946 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)1947 {1948 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)1949 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))1950 { 1951 /*1952 * SDRAM 128 ZX.1953 */1954 chip->RamBandwidthKBytesPerSec = 800000;1955 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)1956 {1957 case 2:1958 chip->RamAmountKBytes = 1024 * 4;1959 break;1960 case 1:1961 chip->RamAmountKBytes = 1024 * 2;1962 break;1963 default:1964 chip->RamAmountKBytes = 1024 * 8;1965 break;1966 }1967 } 1968 else 1969 {1970 chip->RamBandwidthKBytesPerSec = 1000000;1971 chip->RamAmountKBytes = 1024 * 8;1972 } 1973 }1974 else1975 {1976 /*1977 * SGRAM 128.1978 */1979 chip->RamBandwidthKBytesPerSec = 1000000;1980 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)1981 {1982 case 0:1983 chip->RamAmountKBytes = 1024 * 8;1984 break;1985 case 2:1986 chip->RamAmountKBytes = 1024 * 4;1987 break;1988 default:1989 chip->RamAmountKBytes = 1024 * 2;1990 break;1991 }1992 } 1993 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;1994 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);1995 chip->VBlankBit = 0x00000100;1996 chip->MaxVClockFreqKHz = 256000;1997 /*1998 * Set chip functions.1999 */2000 chip->Busy = nv3Busy;2001 chip->ShowHideCursor = ShowHideCursor;2002 chip->LoadStateExt = LoadStateExt;2003 chip->UnloadStateExt = UnloadStateExt;2004 chip->SetStartAddress = SetStartAddress3;2005 chip->SetSurfaces2D = nv3SetSurfaces2D;2006 chip->SetSurfaces3D = nv3SetSurfaces3D;2007 chip->LockUnlock = nv3LockUnlock;2008}2009static void nv4GetConfig2010(2011 RIVA_HW_INST *chip2012)2013{2014 /*2015 * Fill in chip configuration.2016 */2017 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)2018 {2019 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 22020 + 1024 * 2;2021 }2022 else2023 {2024 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)2025 {2026 case 0:2027 chip->RamAmountKBytes = 1024 * 32;2028 break;2029 case 1:2030 chip->RamAmountKBytes = 1024 * 4;2031 break;2032 case 2:2033 chip->RamAmountKBytes = 1024 * 8;2034 break;2035 case 3:2036 default:2037 chip->RamAmountKBytes = 1024 * 16;2038 break;2039 }2040 }2041 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)2042 {2043 case 3:2044 chip->RamBandwidthKBytesPerSec = 800000;2045 break;2046 default:2047 chip->RamBandwidthKBytesPerSec = 1000000;2048 break;2049 }2050 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;2051 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);2052 chip->VBlankBit = 0x00000001;2053 chip->MaxVClockFreqKHz = 350000;2054 /*2055 * Set chip functions.2056 */2057 chip->Busy = nv4Busy;2058 chip->ShowHideCursor = ShowHideCursor;2059 chip->LoadStateExt = LoadStateExt;2060 chip->UnloadStateExt = UnloadStateExt;2061 chip->SetStartAddress = SetStartAddress;2062 chip->SetSurfaces2D = nv4SetSurfaces2D;2063 chip->SetSurfaces3D = nv4SetSurfaces3D;2064 chip->LockUnlock = nv4LockUnlock;2065}2066static void nv10GetConfig2067(2068 RIVA_HW_INST *chip,2069 struct pci_dev *pdev,2070 unsigned int chipset2071)2072{2073 struct pci_dev* dev;2074 int domain = pci_domain_nr(pdev->bus);2075 u32 amt;2076 2077#ifdef __BIG_ENDIAN2078 /* turn on big endian register access */2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))2080 NV_WR32(chip->PMC, 0x00000004, 0x01000001);2081#endif2082 2083 /*2084 * Fill in chip configuration.2085 */2086 if(chipset == NV_CHIP_IGEFORCE2) {2087 dev = pci_get_domain_bus_and_slot(domain, 0, 1);2088 pci_read_config_dword(dev, 0x7C, &amt);2089 pci_dev_put(dev);2090 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;2091 } else if(chipset == NV_CHIP_0x01F0) {2092 dev = pci_get_domain_bus_and_slot(domain, 0, 1);2093 pci_read_config_dword(dev, 0x84, &amt);2094 pci_dev_put(dev);2095 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;2096 } else {2097 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)2098 {2099 case 0x02:2100 chip->RamAmountKBytes = 1024 * 2;2101 break;2102 case 0x04:2103 chip->RamAmountKBytes = 1024 * 4;2104 break;2105 case 0x08:2106 chip->RamAmountKBytes = 1024 * 8;2107 break;2108 case 0x10:2109 chip->RamAmountKBytes = 1024 * 16;2110 break;2111 case 0x20:2112 chip->RamAmountKBytes = 1024 * 32;2113 break;2114 case 0x40:2115 chip->RamAmountKBytes = 1024 * 64;2116 break;2117 case 0x80:2118 chip->RamAmountKBytes = 1024 * 128;2119 break;2120 default:2121 chip->RamAmountKBytes = 1024 * 16;2122 break;2123 }2124 }2125 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)2126 {2127 case 3:2128 chip->RamBandwidthKBytesPerSec = 800000;2129 break;2130 default:2131 chip->RamBandwidthKBytesPerSec = 1000000;2132 break;2133 }2134 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?2135 14318 : 13500;2136 2137 switch (chipset & 0x0ff0) {2138 case 0x0170:2139 case 0x0180:2140 case 0x01F0:2141 case 0x0250:2142 case 0x0280:2143 case 0x0300:2144 case 0x0310:2145 case 0x0320:2146 case 0x0330:2147 case 0x0340:2148 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))2149 chip->CrystalFreqKHz = 27000;2150 break;2151 default:2152 break;2153 }2154 2155 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;2156 chip->CURSOR = NULL; /* can't set this here */2157 chip->VBlankBit = 0x00000001;2158 chip->MaxVClockFreqKHz = 350000;2159 /*2160 * Set chip functions.2161 */2162 chip->Busy = nv10Busy;2163 chip->ShowHideCursor = ShowHideCursor;2164 chip->LoadStateExt = LoadStateExt;2165 chip->UnloadStateExt = UnloadStateExt;2166 chip->SetStartAddress = SetStartAddress;2167 chip->SetSurfaces2D = nv10SetSurfaces2D;2168 chip->SetSurfaces3D = nv10SetSurfaces3D;2169 chip->LockUnlock = nv4LockUnlock;2170 2171 switch(chipset & 0x0ff0) {2172 case 0x0110:2173 case 0x0170:2174 case 0x0180:2175 case 0x01F0:2176 case 0x0250:2177 case 0x0280:2178 case 0x0300:2179 case 0x0310:2180 case 0x0320:2181 case 0x0330:2182 case 0x0340:2183 chip->twoHeads = TRUE;2184 break;2185 default:2186 chip->twoHeads = FALSE;2187 break;2188 }2189}2190int RivaGetConfig2191(2192 RIVA_HW_INST *chip,2193 struct pci_dev *pdev,2194 unsigned int chipset2195)2196{2197 /*2198 * Save this so future SW know whats it's dealing with.2199 */2200 chip->Version = RIVA_SW_VERSION;2201 /*2202 * Chip specific configuration.2203 */2204 switch (chip->Architecture)2205 {2206 case NV_ARCH_03:2207 nv3GetConfig(chip);2208 break;2209 case NV_ARCH_04:2210 nv4GetConfig(chip);2211 break;2212 case NV_ARCH_10:2213 case NV_ARCH_20:2214 case NV_ARCH_30:2215 nv10GetConfig(chip, pdev, chipset);2216 break;2217 default:2218 return (-1);2219 }2220 chip->Chipset = chipset;2221 /*2222 * Fill in FIFO pointers.2223 */2224 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);2225 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);2226 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);2227 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);2228 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);2229 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);2230 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);2231 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);2232 return (0);2233}2234 2235