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1// SPDX-License-Identifier: GPL-2.0-only2/* linux/drivers/video/s3c-fb.c3 *4 * Copyright 2008 Openmoko Inc.5 * Copyright 2008-2010 Simtec Electronics6 * Ben Dooks <ben@simtec.co.uk>7 * http://armlinux.simtec.co.uk/8 *9 * Samsung SoC Framebuffer driver10*/11 12#include <linux/kernel.h>13#include <linux/module.h>14#include <linux/platform_device.h>15#include <linux/dma-mapping.h>16#include <linux/slab.h>17#include <linux/init.h>18#include <linux/clk.h>19#include <linux/fb.h>20#include <linux/io.h>21#include <linux/uaccess.h>22#include <linux/interrupt.h>23#include <linux/pm_runtime.h>24#include <linux/platform_data/video_s3c.h>25 26#include <video/samsung_fimd.h>27 28/* This driver will export a number of framebuffer interfaces depending29 * on the configuration passed in via the platform data. Each fb instance30 * maps to a hardware window. Currently there is no support for runtime31 * setting of the alpha-blending functions that each window has, so only32 * window 0 is actually useful.33 *34 * Window 0 is treated specially, it is used for the basis of the LCD35 * output timings and as the control for the output power-down state.36*/37 38/* note, the previous use of <mach/regs-fb.h> to get platform specific data39 * has been replaced by using the platform device name to pick the correct40 * configuration data for the system.41*/42 43#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE44#undef writel45#define writel(v, r) do { \46 pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \47 __raw_writel(v, r); \48} while (0)49#endif /* FB_S3C_DEBUG_REGWRITE */50 51/* irq_flags bits */52#define S3C_FB_VSYNC_IRQ_EN 053 54#define VSYNC_TIMEOUT_MSEC 5055 56struct s3c_fb;57 58#define VALID_BPP(x) (1 << ((x) - 1))59 60#define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))61#define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)62#define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)63#define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)64#define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)65 66/**67 * struct s3c_fb_variant - fb variant information68 * @is_2443: Set if S3C2443/S3C2416 style hardware.69 * @nr_windows: The number of windows.70 * @vidtcon: The base for the VIDTCONx registers71 * @wincon: The base for the WINxCON registers.72 * @winmap: The base for the WINxMAP registers.73 * @keycon: The abse for the WxKEYCON registers.74 * @buf_start: Offset of buffer start registers.75 * @buf_size: Offset of buffer size registers.76 * @buf_end: Offset of buffer end registers.77 * @osd: The base for the OSD registers.78 * @osd_stride: stride of osd79 * @palette: Address of palette memory, or 0 if none.80 * @has_prtcon: Set if has PRTCON register.81 * @has_shadowcon: Set if has SHADOWCON register.82 * @has_blendcon: Set if has BLENDCON register.83 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.84 * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.85 */86struct s3c_fb_variant {87 unsigned int is_2443:1;88 unsigned short nr_windows;89 unsigned int vidtcon;90 unsigned short wincon;91 unsigned short winmap;92 unsigned short keycon;93 unsigned short buf_start;94 unsigned short buf_end;95 unsigned short buf_size;96 unsigned short osd;97 unsigned short osd_stride;98 unsigned short palette[S3C_FB_MAX_WIN];99 100 unsigned int has_prtcon:1;101 unsigned int has_shadowcon:1;102 unsigned int has_blendcon:1;103 unsigned int has_clksel:1;104 unsigned int has_fixvclk:1;105};106 107/**108 * struct s3c_fb_win_variant109 * @has_osd_c: Set if has OSD C register.110 * @has_osd_d: Set if has OSD D register.111 * @has_osd_alpha: Set if can change alpha transparency for a window.112 * @palette_sz: Size of palette in entries.113 * @palette_16bpp: Set if palette is 16bits wide.114 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate115 * register is located at the given offset from OSD_BASE.116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.117 *118 * valid_bpp bit x is set if (x+1)BPP is supported.119 */120struct s3c_fb_win_variant {121 unsigned int has_osd_c:1;122 unsigned int has_osd_d:1;123 unsigned int has_osd_alpha:1;124 unsigned int palette_16bpp:1;125 unsigned short osd_size_off;126 unsigned short palette_sz;127 u32 valid_bpp;128};129 130/**131 * struct s3c_fb_driverdata - per-device type driver data for init time.132 * @variant: The variant information for this driver.133 * @win: The window information for each window.134 */135struct s3c_fb_driverdata {136 struct s3c_fb_variant variant;137 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];138};139 140/**141 * struct s3c_fb_palette - palette information142 * @r: Red bitfield.143 * @g: Green bitfield.144 * @b: Blue bitfield.145 * @a: Alpha bitfield.146 */147struct s3c_fb_palette {148 struct fb_bitfield r;149 struct fb_bitfield g;150 struct fb_bitfield b;151 struct fb_bitfield a;152};153 154/**155 * struct s3c_fb_win - per window private data for each framebuffer.156 * @windata: The platform data supplied for the window configuration.157 * @parent: The hardware that this window is part of.158 * @fbinfo: Pointer pack to the framebuffer info for this window.159 * @variant: The variant information for this window.160 * @palette_buffer: Buffer/cache to hold palette entries.161 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/162 * @index: The window number of this window.163 * @palette: The bitfields for changing r/g/b into a hardware palette entry.164 */165struct s3c_fb_win {166 struct s3c_fb_pd_win *windata;167 struct s3c_fb *parent;168 struct fb_info *fbinfo;169 struct s3c_fb_palette palette;170 struct s3c_fb_win_variant variant;171 172 u32 *palette_buffer;173 u32 pseudo_palette[16];174 unsigned int index;175};176 177/**178 * struct s3c_fb_vsync - vsync information179 * @wait: a queue for processes waiting for vsync180 * @count: vsync interrupt count181 */182struct s3c_fb_vsync {183 wait_queue_head_t wait;184 unsigned int count;185};186 187/**188 * struct s3c_fb - overall hardware state of the hardware189 * @slock: The spinlock protection for this data structure.190 * @dev: The device that we bound to, for printing, etc.191 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.192 * @lcd_clk: The clk (sclk) feeding pixclk.193 * @regs: The mapped hardware registers.194 * @variant: Variant information for this hardware.195 * @enabled: A bitmask of enabled hardware windows.196 * @output_on: Flag if the physical output is enabled.197 * @pdata: The platform configuration data passed with the device.198 * @windows: The hardware windows that have been claimed.199 * @irq_no: IRQ line number200 * @irq_flags: irq flags201 * @vsync_info: VSYNC-related information (count, queues...)202 */203struct s3c_fb {204 spinlock_t slock;205 struct device *dev;206 struct clk *bus_clk;207 struct clk *lcd_clk;208 void __iomem *regs;209 struct s3c_fb_variant variant;210 211 unsigned char enabled;212 bool output_on;213 214 struct s3c_fb_platdata *pdata;215 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];216 217 int irq_no;218 unsigned long irq_flags;219 struct s3c_fb_vsync vsync_info;220};221 222/**223 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.224 * @win: The device window.225 * @bpp: The bit depth.226 */227static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)228{229 return win->variant.valid_bpp & VALID_BPP(bpp);230}231 232/**233 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.234 * @var: The screen information to verify.235 * @info: The framebuffer device.236 *237 * Framebuffer layer call to verify the given information and allow us to238 * update various information depending on the hardware capabilities.239 */240static int s3c_fb_check_var(struct fb_var_screeninfo *var,241 struct fb_info *info)242{243 struct s3c_fb_win *win = info->par;244 struct s3c_fb *sfb = win->parent;245 246 dev_dbg(sfb->dev, "checking parameters\n");247 248 var->xres_virtual = max(var->xres_virtual, var->xres);249 var->yres_virtual = max(var->yres_virtual, var->yres);250 251 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {252 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",253 win->index, var->bits_per_pixel);254 return -EINVAL;255 }256 257 /* always ensure these are zero, for drop through cases below */258 var->transp.offset = 0;259 var->transp.length = 0;260 261 switch (var->bits_per_pixel) {262 case 1:263 case 2:264 case 4:265 case 8:266 if (sfb->variant.palette[win->index] != 0) {267 /* non palletised, A:1,R:2,G:3,B:2 mode */268 var->red.offset = 5;269 var->green.offset = 2;270 var->blue.offset = 0;271 var->red.length = 2;272 var->green.length = 3;273 var->blue.length = 2;274 var->transp.offset = 7;275 var->transp.length = 1;276 } else {277 var->red.offset = 0;278 var->red.length = var->bits_per_pixel;279 var->green = var->red;280 var->blue = var->red;281 }282 break;283 284 case 19:285 /* 666 with one bit alpha/transparency */286 var->transp.offset = 18;287 var->transp.length = 1;288 fallthrough;289 case 18:290 var->bits_per_pixel = 32;291 292 /* 666 format */293 var->red.offset = 12;294 var->green.offset = 6;295 var->blue.offset = 0;296 var->red.length = 6;297 var->green.length = 6;298 var->blue.length = 6;299 break;300 301 case 16:302 /* 16 bpp, 565 format */303 var->red.offset = 11;304 var->green.offset = 5;305 var->blue.offset = 0;306 var->red.length = 5;307 var->green.length = 6;308 var->blue.length = 5;309 break;310 311 case 32:312 case 28:313 case 25:314 var->transp.length = var->bits_per_pixel - 24;315 var->transp.offset = 24;316 fallthrough;317 case 24:318 /* our 24bpp is unpacked, so 32bpp */319 var->bits_per_pixel = 32;320 var->red.offset = 16;321 var->red.length = 8;322 var->green.offset = 8;323 var->green.length = 8;324 var->blue.offset = 0;325 var->blue.length = 8;326 break;327 328 default:329 dev_err(sfb->dev, "invalid bpp\n");330 return -EINVAL;331 }332 333 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);334 return 0;335}336 337/**338 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.339 * @sfb: The hardware state.340 * @pixclk: The pixel clock wanted, in picoseconds.341 *342 * Given the specified pixel clock, work out the necessary divider to get343 * close to the output frequency.344 */345static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)346{347 unsigned long clk;348 unsigned long long tmp;349 unsigned int result;350 351 if (sfb->variant.has_clksel)352 clk = clk_get_rate(sfb->bus_clk);353 else354 clk = clk_get_rate(sfb->lcd_clk);355 356 tmp = (unsigned long long)clk;357 tmp *= pixclk;358 359 do_div(tmp, 1000000000UL);360 result = (unsigned int)tmp / 1000;361 362 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",363 pixclk, clk, result, result ? clk / result : clk);364 365 return result;366}367 368/**369 * s3c_fb_align_word() - align pixel count to word boundary370 * @bpp: The number of bits per pixel371 * @pix: The value to be aligned.372 *373 * Align the given pixel count so that it will start on an 32bit word374 * boundary.375 */376static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)377{378 int pix_per_word;379 380 if (bpp > 16)381 return pix;382 383 pix_per_word = (8 * 32) / bpp;384 return ALIGN(pix, pix_per_word);385}386 387/**388 * vidosd_set_size() - set OSD size for a window389 *390 * @win: the window to set OSD size for391 * @size: OSD size register value392 */393static void vidosd_set_size(struct s3c_fb_win *win, u32 size)394{395 struct s3c_fb *sfb = win->parent;396 397 /* OSD can be set up if osd_size_off != 0 for this window */398 if (win->variant.osd_size_off)399 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)400 + win->variant.osd_size_off);401}402 403/**404 * vidosd_set_alpha() - set alpha transparency for a window405 *406 * @win: the window to set OSD size for407 * @alpha: alpha register value408 */409static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)410{411 struct s3c_fb *sfb = win->parent;412 413 if (win->variant.has_osd_alpha)414 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));415}416 417/**418 * shadow_protect_win() - disable updating values from shadow registers at vsync419 *420 * @win: window to protect registers for421 * @protect: 1 to protect (disable updates)422 */423static void shadow_protect_win(struct s3c_fb_win *win, bool protect)424{425 struct s3c_fb *sfb = win->parent;426 u32 reg;427 428 if (protect) {429 if (sfb->variant.has_prtcon) {430 writel(PRTCON_PROTECT, sfb->regs + PRTCON);431 } else if (sfb->variant.has_shadowcon) {432 reg = readl(sfb->regs + SHADOWCON);433 writel(reg | SHADOWCON_WINx_PROTECT(win->index),434 sfb->regs + SHADOWCON);435 }436 } else {437 if (sfb->variant.has_prtcon) {438 writel(0, sfb->regs + PRTCON);439 } else if (sfb->variant.has_shadowcon) {440 reg = readl(sfb->regs + SHADOWCON);441 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),442 sfb->regs + SHADOWCON);443 }444 }445}446 447/**448 * s3c_fb_enable() - Set the state of the main LCD output449 * @sfb: The main framebuffer state.450 * @enable: The state to set.451 */452static void s3c_fb_enable(struct s3c_fb *sfb, int enable)453{454 u32 vidcon0 = readl(sfb->regs + VIDCON0);455 456 if (enable && !sfb->output_on)457 pm_runtime_get_sync(sfb->dev);458 459 if (enable) {460 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;461 } else {462 /* see the note in the framebuffer datasheet about463 * why you cannot take both of these bits down at the464 * same time. */465 466 if (vidcon0 & VIDCON0_ENVID) {467 vidcon0 |= VIDCON0_ENVID;468 vidcon0 &= ~VIDCON0_ENVID_F;469 }470 }471 472 writel(vidcon0, sfb->regs + VIDCON0);473 474 if (!enable && sfb->output_on)475 pm_runtime_put_sync(sfb->dev);476 477 sfb->output_on = enable;478}479 480/**481 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.482 * @info: The framebuffer to change.483 *484 * Framebuffer layer request to set a new mode for the specified framebuffer485 */486static int s3c_fb_set_par(struct fb_info *info)487{488 struct fb_var_screeninfo *var = &info->var;489 struct s3c_fb_win *win = info->par;490 struct s3c_fb *sfb = win->parent;491 void __iomem *regs = sfb->regs;492 void __iomem *buf;493 int win_no = win->index;494 u32 alpha = 0;495 u32 data;496 u32 pagewidth;497 498 dev_dbg(sfb->dev, "setting framebuffer parameters\n");499 500 pm_runtime_get_sync(sfb->dev);501 502 shadow_protect_win(win, 1);503 504 switch (var->bits_per_pixel) {505 case 32:506 case 24:507 case 16:508 case 12:509 info->fix.visual = FB_VISUAL_TRUECOLOR;510 break;511 case 8:512 if (win->variant.palette_sz >= 256)513 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;514 else515 info->fix.visual = FB_VISUAL_TRUECOLOR;516 break;517 case 1:518 info->fix.visual = FB_VISUAL_MONO01;519 break;520 default:521 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;522 break;523 }524 525 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;526 527 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;528 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;529 530 /* disable the window whilst we update it */531 writel(0, regs + WINCON(win_no));532 533 if (!sfb->output_on)534 s3c_fb_enable(sfb, 1);535 536 /* write the buffer address */537 538 /* start and end registers stride is 8 */539 buf = regs + win_no * 8;540 541 writel(info->fix.smem_start, buf + sfb->variant.buf_start);542 543 data = info->fix.smem_start + info->fix.line_length * var->yres;544 writel(data, buf + sfb->variant.buf_end);545 546 pagewidth = (var->xres * var->bits_per_pixel) >> 3;547 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |548 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |549 VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |550 VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);551 writel(data, regs + sfb->variant.buf_size + (win_no * 4));552 553 /* write 'OSD' registers to control position of framebuffer */554 555 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |556 VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);557 writel(data, regs + VIDOSD_A(win_no, sfb->variant));558 559 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,560 var->xres - 1)) |561 VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |562 VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,563 var->xres - 1)) |564 VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);565 566 writel(data, regs + VIDOSD_B(win_no, sfb->variant));567 568 data = var->xres * var->yres;569 570 alpha = VIDISD14C_ALPHA1_R(0xf) |571 VIDISD14C_ALPHA1_G(0xf) |572 VIDISD14C_ALPHA1_B(0xf);573 574 vidosd_set_alpha(win, alpha);575 vidosd_set_size(win, data);576 577 /* Enable DMA channel for this window */578 if (sfb->variant.has_shadowcon) {579 data = readl(sfb->regs + SHADOWCON);580 data |= SHADOWCON_CHx_ENABLE(win_no);581 writel(data, sfb->regs + SHADOWCON);582 }583 584 data = WINCONx_ENWIN;585 sfb->enabled |= (1 << win->index);586 587 /* note, since we have to round up the bits-per-pixel, we end up588 * relying on the bitfield information for r/g/b/a to work out589 * exactly which mode of operation is intended. */590 591 switch (var->bits_per_pixel) {592 case 1:593 data |= WINCON0_BPPMODE_1BPP;594 data |= WINCONx_BITSWP;595 data |= WINCONx_BURSTLEN_4WORD;596 break;597 case 2:598 data |= WINCON0_BPPMODE_2BPP;599 data |= WINCONx_BITSWP;600 data |= WINCONx_BURSTLEN_8WORD;601 break;602 case 4:603 data |= WINCON0_BPPMODE_4BPP;604 data |= WINCONx_BITSWP;605 data |= WINCONx_BURSTLEN_8WORD;606 break;607 case 8:608 if (var->transp.length != 0)609 data |= WINCON1_BPPMODE_8BPP_1232;610 else611 data |= WINCON0_BPPMODE_8BPP_PALETTE;612 data |= WINCONx_BURSTLEN_8WORD;613 data |= WINCONx_BYTSWP;614 break;615 case 16:616 if (var->transp.length != 0)617 data |= WINCON1_BPPMODE_16BPP_A1555;618 else619 data |= WINCON0_BPPMODE_16BPP_565;620 data |= WINCONx_HAWSWP;621 data |= WINCONx_BURSTLEN_16WORD;622 break;623 case 24:624 case 32:625 if (var->red.length == 6) {626 if (var->transp.length != 0)627 data |= WINCON1_BPPMODE_19BPP_A1666;628 else629 data |= WINCON1_BPPMODE_18BPP_666;630 } else if (var->transp.length == 1)631 data |= WINCON1_BPPMODE_25BPP_A1888632 | WINCON1_BLD_PIX;633 else if ((var->transp.length == 4) ||634 (var->transp.length == 8))635 data |= WINCON1_BPPMODE_28BPP_A4888636 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;637 else638 data |= WINCON0_BPPMODE_24BPP_888;639 640 data |= WINCONx_WSWP;641 data |= WINCONx_BURSTLEN_16WORD;642 break;643 }644 645 /* Enable the colour keying for the window below this one */646 if (win_no > 0) {647 u32 keycon0_data = 0, keycon1_data = 0;648 void __iomem *keycon = regs + sfb->variant.keycon;649 650 keycon0_data = ~(WxKEYCON0_KEYBL_EN |651 WxKEYCON0_KEYEN_F |652 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);653 654 keycon1_data = WxKEYCON1_COLVAL(0xffffff);655 656 keycon += (win_no - 1) * 8;657 658 writel(keycon0_data, keycon + WKEYCON0);659 writel(keycon1_data, keycon + WKEYCON1);660 }661 662 writel(data, regs + sfb->variant.wincon + (win_no * 4));663 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));664 665 /* Set alpha value width */666 if (sfb->variant.has_blendcon) {667 data = readl(sfb->regs + BLENDCON);668 data &= ~BLENDCON_NEW_MASK;669 if (var->transp.length > 4)670 data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;671 else672 data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;673 writel(data, sfb->regs + BLENDCON);674 }675 676 shadow_protect_win(win, 0);677 678 pm_runtime_put_sync(sfb->dev);679 680 return 0;681}682 683/**684 * s3c_fb_update_palette() - set or schedule a palette update.685 * @sfb: The hardware information.686 * @win: The window being updated.687 * @reg: The palette index being changed.688 * @value: The computed palette value.689 *690 * Change the value of a palette register, either by directly writing to691 * the palette (this requires the palette RAM to be disconnected from the692 * hardware whilst this is in progress) or schedule the update for later.693 *694 * At the moment, since we have no VSYNC interrupt support, we simply set695 * the palette entry directly.696 */697static void s3c_fb_update_palette(struct s3c_fb *sfb,698 struct s3c_fb_win *win,699 unsigned int reg,700 u32 value)701{702 void __iomem *palreg;703 u32 palcon;704 705 palreg = sfb->regs + sfb->variant.palette[win->index];706 707 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",708 __func__, win->index, reg, palreg, value);709 710 win->palette_buffer[reg] = value;711 712 palcon = readl(sfb->regs + WPALCON);713 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);714 715 if (win->variant.palette_16bpp)716 writew(value, palreg + (reg * 2));717 else718 writel(value, palreg + (reg * 4));719 720 writel(palcon, sfb->regs + WPALCON);721}722 723static inline unsigned int chan_to_field(unsigned int chan,724 struct fb_bitfield *bf)725{726 chan &= 0xffff;727 chan >>= 16 - bf->length;728 return chan << bf->offset;729}730 731/**732 * s3c_fb_setcolreg() - framebuffer layer request to change palette.733 * @regno: The palette index to change.734 * @red: The red field for the palette data.735 * @green: The green field for the palette data.736 * @blue: The blue field for the palette data.737 * @transp: The transparency (alpha) field for the palette data.738 * @info: The framebuffer being changed.739 */740static int s3c_fb_setcolreg(unsigned regno,741 unsigned red, unsigned green, unsigned blue,742 unsigned transp, struct fb_info *info)743{744 struct s3c_fb_win *win = info->par;745 struct s3c_fb *sfb = win->parent;746 unsigned int val;747 748 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",749 __func__, win->index, regno, red, green, blue);750 751 pm_runtime_get_sync(sfb->dev);752 753 switch (info->fix.visual) {754 case FB_VISUAL_TRUECOLOR:755 /* true-colour, use pseudo-palette */756 757 if (regno < 16) {758 u32 *pal = info->pseudo_palette;759 760 val = chan_to_field(red, &info->var.red);761 val |= chan_to_field(green, &info->var.green);762 val |= chan_to_field(blue, &info->var.blue);763 764 pal[regno] = val;765 }766 break;767 768 case FB_VISUAL_PSEUDOCOLOR:769 if (regno < win->variant.palette_sz) {770 val = chan_to_field(red, &win->palette.r);771 val |= chan_to_field(green, &win->palette.g);772 val |= chan_to_field(blue, &win->palette.b);773 774 s3c_fb_update_palette(sfb, win, regno, val);775 }776 777 break;778 779 default:780 pm_runtime_put_sync(sfb->dev);781 return 1; /* unknown type */782 }783 784 pm_runtime_put_sync(sfb->dev);785 return 0;786}787 788/**789 * s3c_fb_blank() - blank or unblank the given window790 * @blank_mode: The blank state from FB_BLANK_*791 * @info: The framebuffer to blank.792 *793 * Framebuffer layer request to change the power state.794 */795static int s3c_fb_blank(int blank_mode, struct fb_info *info)796{797 struct s3c_fb_win *win = info->par;798 struct s3c_fb *sfb = win->parent;799 unsigned int index = win->index;800 u32 wincon;801 u32 output_on = sfb->output_on;802 803 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);804 805 pm_runtime_get_sync(sfb->dev);806 807 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));808 809 switch (blank_mode) {810 case FB_BLANK_POWERDOWN:811 wincon &= ~WINCONx_ENWIN;812 sfb->enabled &= ~(1 << index);813 fallthrough; /* to FB_BLANK_NORMAL */814 815 case FB_BLANK_NORMAL:816 /* disable the DMA and display 0x0 (black) */817 shadow_protect_win(win, 1);818 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),819 sfb->regs + sfb->variant.winmap + (index * 4));820 shadow_protect_win(win, 0);821 break;822 823 case FB_BLANK_UNBLANK:824 shadow_protect_win(win, 1);825 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));826 shadow_protect_win(win, 0);827 wincon |= WINCONx_ENWIN;828 sfb->enabled |= (1 << index);829 break;830 831 case FB_BLANK_VSYNC_SUSPEND:832 case FB_BLANK_HSYNC_SUSPEND:833 default:834 pm_runtime_put_sync(sfb->dev);835 return 1;836 }837 838 shadow_protect_win(win, 1);839 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));840 841 /* Check the enabled state to see if we need to be running the842 * main LCD interface, as if there are no active windows then843 * it is highly likely that we also do not need to output844 * anything.845 */846 s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);847 shadow_protect_win(win, 0);848 849 pm_runtime_put_sync(sfb->dev);850 851 return output_on == sfb->output_on;852}853 854/**855 * s3c_fb_pan_display() - Pan the display.856 *857 * Note that the offsets can be written to the device at any time, as their858 * values are latched at each vsync automatically. This also means that only859 * the last call to this function will have any effect on next vsync, but860 * there is no need to sleep waiting for it to prevent tearing.861 *862 * @var: The screen information to verify.863 * @info: The framebuffer device.864 */865static int s3c_fb_pan_display(struct fb_var_screeninfo *var,866 struct fb_info *info)867{868 struct s3c_fb_win *win = info->par;869 struct s3c_fb *sfb = win->parent;870 void __iomem *buf = sfb->regs + win->index * 8;871 unsigned int start_boff, end_boff;872 873 pm_runtime_get_sync(sfb->dev);874 875 /* Offset in bytes to the start of the displayed area */876 start_boff = var->yoffset * info->fix.line_length;877 /* X offset depends on the current bpp */878 if (info->var.bits_per_pixel >= 8) {879 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);880 } else {881 switch (info->var.bits_per_pixel) {882 case 4:883 start_boff += var->xoffset >> 1;884 break;885 case 2:886 start_boff += var->xoffset >> 2;887 break;888 case 1:889 start_boff += var->xoffset >> 3;890 break;891 default:892 dev_err(sfb->dev, "invalid bpp\n");893 pm_runtime_put_sync(sfb->dev);894 return -EINVAL;895 }896 }897 /* Offset in bytes to the end of the displayed area */898 end_boff = start_boff + info->var.yres * info->fix.line_length;899 900 /* Temporarily turn off per-vsync update from shadow registers until901 * both start and end addresses are updated to prevent corruption */902 shadow_protect_win(win, 1);903 904 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);905 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);906 907 shadow_protect_win(win, 0);908 909 pm_runtime_put_sync(sfb->dev);910 return 0;911}912 913/**914 * s3c_fb_enable_irq() - enable framebuffer interrupts915 * @sfb: main hardware state916 */917static void s3c_fb_enable_irq(struct s3c_fb *sfb)918{919 void __iomem *regs = sfb->regs;920 u32 irq_ctrl_reg;921 922 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {923 /* IRQ disabled, enable it */924 irq_ctrl_reg = readl(regs + VIDINTCON0);925 926 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;927 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;928 929 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;930 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;931 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;932 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;933 934 writel(irq_ctrl_reg, regs + VIDINTCON0);935 }936}937 938/**939 * s3c_fb_disable_irq() - disable framebuffer interrupts940 * @sfb: main hardware state941 */942static void s3c_fb_disable_irq(struct s3c_fb *sfb)943{944 void __iomem *regs = sfb->regs;945 u32 irq_ctrl_reg;946 947 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {948 /* IRQ enabled, disable it */949 irq_ctrl_reg = readl(regs + VIDINTCON0);950 951 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;952 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;953 954 writel(irq_ctrl_reg, regs + VIDINTCON0);955 }956}957 958static irqreturn_t s3c_fb_irq(int irq, void *dev_id)959{960 struct s3c_fb *sfb = dev_id;961 void __iomem *regs = sfb->regs;962 u32 irq_sts_reg;963 964 spin_lock(&sfb->slock);965 966 irq_sts_reg = readl(regs + VIDINTCON1);967 968 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {969 970 /* VSYNC interrupt, accept it */971 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);972 973 sfb->vsync_info.count++;974 wake_up_interruptible(&sfb->vsync_info.wait);975 }976 977 /* We only support waiting for VSYNC for now, so it's safe978 * to always disable irqs here.979 */980 s3c_fb_disable_irq(sfb);981 982 spin_unlock(&sfb->slock);983 return IRQ_HANDLED;984}985 986/**987 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout988 * @sfb: main hardware state989 * @crtc: head index.990 */991static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)992{993 unsigned long count;994 int ret;995 996 if (crtc != 0)997 return -ENODEV;998 999 pm_runtime_get_sync(sfb->dev);1000 1001 count = sfb->vsync_info.count;1002 s3c_fb_enable_irq(sfb);1003 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,1004 count != sfb->vsync_info.count,1005 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));1006 1007 pm_runtime_put_sync(sfb->dev);1008 1009 if (ret == 0)1010 return -ETIMEDOUT;1011 1012 return 0;1013}1014 1015static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,1016 unsigned long arg)1017{1018 struct s3c_fb_win *win = info->par;1019 struct s3c_fb *sfb = win->parent;1020 int ret;1021 u32 crtc;1022 1023 switch (cmd) {1024 case FBIO_WAITFORVSYNC:1025 if (get_user(crtc, (u32 __user *)arg)) {1026 ret = -EFAULT;1027 break;1028 }1029 1030 ret = s3c_fb_wait_for_vsync(sfb, crtc);1031 break;1032 default:1033 ret = -ENOTTY;1034 }1035 1036 return ret;1037}1038 1039static const struct fb_ops s3c_fb_ops = {1040 .owner = THIS_MODULE,1041 FB_DEFAULT_IOMEM_OPS,1042 .fb_check_var = s3c_fb_check_var,1043 .fb_set_par = s3c_fb_set_par,1044 .fb_blank = s3c_fb_blank,1045 .fb_setcolreg = s3c_fb_setcolreg,1046 .fb_pan_display = s3c_fb_pan_display,1047 .fb_ioctl = s3c_fb_ioctl,1048};1049 1050/**1051 * s3c_fb_missing_pixclock() - calculates pixel clock1052 * @mode: The video mode to change.1053 *1054 * Calculate the pixel clock when none has been given through platform data.1055 */1056static void s3c_fb_missing_pixclock(struct fb_videomode *mode)1057{1058 u64 pixclk = 1000000000000ULL;1059 u32 div;1060 1061 div = mode->left_margin + mode->hsync_len + mode->right_margin +1062 mode->xres;1063 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +1064 mode->yres;1065 div *= mode->refresh ? : 60;1066 1067 do_div(pixclk, div);1068 1069 mode->pixclock = pixclk;1070}1071 1072/**1073 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window1074 * @sfb: The base resources for the hardware.1075 * @win: The window to initialise memory for.1076 *1077 * Allocate memory for the given framebuffer.1078 */1079static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)1080{1081 struct s3c_fb_pd_win *windata = win->windata;1082 unsigned int real_size, virt_size, size;1083 struct fb_info *fbi = win->fbinfo;1084 dma_addr_t map_dma;1085 1086 dev_dbg(sfb->dev, "allocating memory for display\n");1087 1088 real_size = windata->xres * windata->yres;1089 virt_size = windata->virtual_x * windata->virtual_y;1090 1091 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",1092 real_size, windata->xres, windata->yres,1093 virt_size, windata->virtual_x, windata->virtual_y);1094 1095 size = (real_size > virt_size) ? real_size : virt_size;1096 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;1097 size /= 8;1098 1099 fbi->fix.smem_len = size;1100 size = PAGE_ALIGN(size);1101 1102 dev_dbg(sfb->dev, "want %u bytes for window\n", size);1103 1104 fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);1105 if (!fbi->screen_buffer)1106 return -ENOMEM;1107 1108 dev_dbg(sfb->dev, "mapped %x to %p\n",1109 (unsigned int)map_dma, fbi->screen_buffer);1110 1111 memset(fbi->screen_buffer, 0x0, size);1112 fbi->fix.smem_start = map_dma;1113 1114 return 0;1115}1116 1117/**1118 * s3c_fb_free_memory() - free the display memory for the given window1119 * @sfb: The base resources for the hardware.1120 * @win: The window to free the display memory for.1121 *1122 * Free the display memory allocated by s3c_fb_alloc_memory().1123 */1124static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)1125{1126 struct fb_info *fbi = win->fbinfo;1127 1128 if (fbi->screen_buffer)1129 dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),1130 fbi->screen_buffer, fbi->fix.smem_start);1131}1132 1133/**1134 * s3c_fb_release_win() - release resources for a framebuffer window.1135 * @sfb: The base resources for the hardware.1136 * @win: The window to cleanup the resources for.1137 *1138 * Release the resources that where claimed for the hardware window,1139 * such as the framebuffer instance and any memory claimed for it.1140 */1141static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)1142{1143 u32 data;1144 1145 if (win->fbinfo) {1146 if (sfb->variant.has_shadowcon) {1147 data = readl(sfb->regs + SHADOWCON);1148 data &= ~SHADOWCON_CHx_ENABLE(win->index);1149 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);1150 writel(data, sfb->regs + SHADOWCON);1151 }1152 unregister_framebuffer(win->fbinfo);1153 if (win->fbinfo->cmap.len)1154 fb_dealloc_cmap(&win->fbinfo->cmap);1155 s3c_fb_free_memory(sfb, win);1156 framebuffer_release(win->fbinfo);1157 }1158}1159 1160/**1161 * s3c_fb_probe_win() - register an hardware window1162 * @sfb: The base resources for the hardware1163 * @win_no: The window number1164 * @variant: The variant information for this window.1165 * @res: Pointer to where to place the resultant window.1166 *1167 * Allocate and do the basic initialisation for one of the hardware's graphics1168 * windows.1169 */1170static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,1171 struct s3c_fb_win_variant *variant,1172 struct s3c_fb_win **res)1173{1174 struct fb_videomode initmode;1175 struct s3c_fb_pd_win *windata;1176 struct s3c_fb_win *win;1177 struct fb_info *fbinfo;1178 int palette_size;1179 int ret;1180 1181 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);1182 1183 init_waitqueue_head(&sfb->vsync_info.wait);1184 1185 palette_size = variant->palette_sz * 4;1186 1187 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +1188 palette_size * sizeof(u32), sfb->dev);1189 if (!fbinfo)1190 return -ENOMEM;1191 1192 windata = sfb->pdata->win[win_no];1193 initmode = *sfb->pdata->vtiming;1194 1195 WARN_ON(windata->max_bpp == 0);1196 WARN_ON(windata->xres == 0);1197 WARN_ON(windata->yres == 0);1198 1199 win = fbinfo->par;1200 *res = win;1201 win->variant = *variant;1202 win->fbinfo = fbinfo;1203 win->parent = sfb;1204 win->windata = windata;1205 win->index = win_no;1206 win->palette_buffer = (u32 *)(win + 1);1207 1208 ret = s3c_fb_alloc_memory(sfb, win);1209 if (ret) {1210 dev_err(sfb->dev, "failed to allocate display memory\n");1211 return ret;1212 }1213 1214 /* setup the r/b/g positions for the window's palette */1215 if (win->variant.palette_16bpp) {1216 /* Set RGB 5:6:5 as default */1217 win->palette.r.offset = 11;1218 win->palette.r.length = 5;1219 win->palette.g.offset = 5;1220 win->palette.g.length = 6;1221 win->palette.b.offset = 0;1222 win->palette.b.length = 5;1223 1224 } else {1225 /* Set 8bpp or 8bpp and 1bit alpha */1226 win->palette.r.offset = 16;1227 win->palette.r.length = 8;1228 win->palette.g.offset = 8;1229 win->palette.g.length = 8;1230 win->palette.b.offset = 0;1231 win->palette.b.length = 8;1232 }1233 1234 /* setup the initial video mode from the window */1235 initmode.xres = windata->xres;1236 initmode.yres = windata->yres;1237 fb_videomode_to_var(&fbinfo->var, &initmode);1238 1239 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;1240 fbinfo->fix.accel = FB_ACCEL_NONE;1241 fbinfo->var.activate = FB_ACTIVATE_NOW;1242 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;1243 fbinfo->var.bits_per_pixel = windata->default_bpp;1244 fbinfo->fbops = &s3c_fb_ops;1245 fbinfo->pseudo_palette = &win->pseudo_palette;1246 1247 /* prepare to actually start the framebuffer */1248 1249 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);1250 if (ret < 0) {1251 dev_err(sfb->dev, "check_var failed on initial video params\n");1252 return ret;1253 }1254 1255 /* create initial colour map */1256 1257 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);1258 if (ret == 0)1259 fb_set_cmap(&fbinfo->cmap, fbinfo);1260 else1261 dev_err(sfb->dev, "failed to allocate fb cmap\n");1262 1263 s3c_fb_set_par(fbinfo);1264 1265 dev_dbg(sfb->dev, "about to register framebuffer\n");1266 1267 /* run the check_var and set_par on our configuration. */1268 1269 ret = register_framebuffer(fbinfo);1270 if (ret < 0) {1271 dev_err(sfb->dev, "failed to register framebuffer\n");1272 return ret;1273 }1274 1275 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);1276 1277 return 0;1278}1279 1280/**1281 * s3c_fb_set_rgb_timing() - set video timing for rgb interface.1282 * @sfb: The base resources for the hardware.1283 *1284 * Set horizontal and vertical lcd rgb interface timing.1285 */1286static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)1287{1288 struct fb_videomode *vmode = sfb->pdata->vtiming;1289 void __iomem *regs = sfb->regs;1290 int clkdiv;1291 u32 data;1292 1293 if (!vmode->pixclock)1294 s3c_fb_missing_pixclock(vmode);1295 1296 clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);1297 1298 data = sfb->pdata->vidcon0;1299 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);1300 1301 if (clkdiv > 1)1302 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;1303 else1304 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */1305 1306 if (sfb->variant.is_2443)1307 data |= (1 << 5);1308 writel(data, regs + VIDCON0);1309 1310 data = VIDTCON0_VBPD(vmode->upper_margin - 1) |1311 VIDTCON0_VFPD(vmode->lower_margin - 1) |1312 VIDTCON0_VSPW(vmode->vsync_len - 1);1313 writel(data, regs + sfb->variant.vidtcon);1314 1315 data = VIDTCON1_HBPD(vmode->left_margin - 1) |1316 VIDTCON1_HFPD(vmode->right_margin - 1) |1317 VIDTCON1_HSPW(vmode->hsync_len - 1);1318 writel(data, regs + sfb->variant.vidtcon + 4);1319 1320 data = VIDTCON2_LINEVAL(vmode->yres - 1) |1321 VIDTCON2_HOZVAL(vmode->xres - 1) |1322 VIDTCON2_LINEVAL_E(vmode->yres - 1) |1323 VIDTCON2_HOZVAL_E(vmode->xres - 1);1324 writel(data, regs + sfb->variant.vidtcon + 8);1325}1326 1327/**1328 * s3c_fb_clear_win() - clear hardware window registers.1329 * @sfb: The base resources for the hardware.1330 * @win: The window to process.1331 *1332 * Reset the specific window registers to a known state.1333 */1334static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)1335{1336 void __iomem *regs = sfb->regs;1337 u32 reg;1338 1339 writel(0, regs + sfb->variant.wincon + (win * 4));1340 writel(0, regs + VIDOSD_A(win, sfb->variant));1341 writel(0, regs + VIDOSD_B(win, sfb->variant));1342 writel(0, regs + VIDOSD_C(win, sfb->variant));1343 1344 if (sfb->variant.has_shadowcon) {1345 reg = readl(sfb->regs + SHADOWCON);1346 reg &= ~(SHADOWCON_WINx_PROTECT(win) |1347 SHADOWCON_CHx_ENABLE(win) |1348 SHADOWCON_CHx_LOCAL_ENABLE(win));1349 writel(reg, sfb->regs + SHADOWCON);1350 }1351}1352 1353static int s3c_fb_probe(struct platform_device *pdev)1354{1355 const struct platform_device_id *platid;1356 struct s3c_fb_driverdata *fbdrv;1357 struct device *dev = &pdev->dev;1358 struct s3c_fb_platdata *pd;1359 struct s3c_fb *sfb;1360 int win;1361 int ret = 0;1362 u32 reg;1363 1364 platid = platform_get_device_id(pdev);1365 fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;1366 1367 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {1368 dev_err(dev, "too many windows, cannot attach\n");1369 return -EINVAL;1370 }1371 1372 pd = dev_get_platdata(&pdev->dev);1373 if (!pd) {1374 dev_err(dev, "no platform data specified\n");1375 return -EINVAL;1376 }1377 1378 sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);1379 if (!sfb)1380 return -ENOMEM;1381 1382 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);1383 1384 sfb->dev = dev;1385 sfb->pdata = pd;1386 sfb->variant = fbdrv->variant;1387 1388 spin_lock_init(&sfb->slock);1389 1390 sfb->bus_clk = devm_clk_get(dev, "lcd");1391 if (IS_ERR(sfb->bus_clk))1392 return dev_err_probe(dev, PTR_ERR(sfb->bus_clk),1393 "failed to get bus clock\n");1394 1395 clk_prepare_enable(sfb->bus_clk);1396 1397 if (!sfb->variant.has_clksel) {1398 sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");1399 if (IS_ERR(sfb->lcd_clk)) {1400 ret = dev_err_probe(dev, PTR_ERR(sfb->lcd_clk),1401 "failed to get lcd clock\n");1402 goto err_bus_clk;1403 }1404 1405 clk_prepare_enable(sfb->lcd_clk);1406 }1407 1408 pm_runtime_enable(sfb->dev);1409 1410 sfb->regs = devm_platform_ioremap_resource(pdev, 0);1411 if (IS_ERR(sfb->regs)) {1412 ret = PTR_ERR(sfb->regs);1413 goto err_lcd_clk;1414 }1415 1416 sfb->irq_no = platform_get_irq(pdev, 0);1417 if (sfb->irq_no < 0) {1418 ret = -ENOENT;1419 goto err_lcd_clk;1420 }1421 1422 ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,1423 0, "s3c_fb", sfb);1424 if (ret) {1425 dev_err(dev, "irq request failed\n");1426 goto err_lcd_clk;1427 }1428 1429 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);1430 1431 platform_set_drvdata(pdev, sfb);1432 pm_runtime_get_sync(sfb->dev);1433 1434 /* setup gpio and output polarity controls */1435 1436 pd->setup_gpio();1437 1438 writel(pd->vidcon1, sfb->regs + VIDCON1);1439 1440 /* set video clock running at under-run */1441 if (sfb->variant.has_fixvclk) {1442 reg = readl(sfb->regs + VIDCON1);1443 reg &= ~VIDCON1_VCLK_MASK;1444 reg |= VIDCON1_VCLK_RUN;1445 writel(reg, sfb->regs + VIDCON1);1446 }1447 1448 /* zero all windows before we do anything */1449 1450 for (win = 0; win < fbdrv->variant.nr_windows; win++)1451 s3c_fb_clear_win(sfb, win);1452 1453 /* initialise colour key controls */1454 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {1455 void __iomem *regs = sfb->regs + sfb->variant.keycon;1456 1457 regs += (win * 8);1458 writel(0xffffff, regs + WKEYCON0);1459 writel(0xffffff, regs + WKEYCON1);1460 }1461 1462 s3c_fb_set_rgb_timing(sfb);1463 1464 /* we have the register setup, start allocating framebuffers */1465 1466 for (win = 0; win < fbdrv->variant.nr_windows; win++) {1467 if (!pd->win[win])1468 continue;1469 1470 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],1471 &sfb->windows[win]);1472 if (ret < 0) {1473 dev_err(dev, "failed to create window %d\n", win);1474 for (; win >= 0; win--)1475 s3c_fb_release_win(sfb, sfb->windows[win]);1476 goto err_pm_runtime;1477 }1478 }1479 1480 platform_set_drvdata(pdev, sfb);1481 pm_runtime_put_sync(sfb->dev);1482 1483 return 0;1484 1485err_pm_runtime:1486 pm_runtime_put_sync(sfb->dev);1487 1488err_lcd_clk:1489 pm_runtime_disable(sfb->dev);1490 1491 if (!sfb->variant.has_clksel)1492 clk_disable_unprepare(sfb->lcd_clk);1493 1494err_bus_clk:1495 clk_disable_unprepare(sfb->bus_clk);1496 1497 return ret;1498}1499 1500/**1501 * s3c_fb_remove() - Cleanup on module finalisation1502 * @pdev: The platform device we are bound to.1503 *1504 * Shutdown and then release all the resources that the driver allocated1505 * on initialisation.1506 */1507static void s3c_fb_remove(struct platform_device *pdev)1508{1509 struct s3c_fb *sfb = platform_get_drvdata(pdev);1510 int win;1511 1512 pm_runtime_get_sync(sfb->dev);1513 1514 for (win = 0; win < S3C_FB_MAX_WIN; win++)1515 if (sfb->windows[win])1516 s3c_fb_release_win(sfb, sfb->windows[win]);1517 1518 if (!sfb->variant.has_clksel)1519 clk_disable_unprepare(sfb->lcd_clk);1520 1521 clk_disable_unprepare(sfb->bus_clk);1522 1523 pm_runtime_put_sync(sfb->dev);1524 pm_runtime_disable(sfb->dev);1525}1526 1527#ifdef CONFIG_PM_SLEEP1528static int s3c_fb_suspend(struct device *dev)1529{1530 struct s3c_fb *sfb = dev_get_drvdata(dev);1531 struct s3c_fb_win *win;1532 int win_no;1533 1534 pm_runtime_get_sync(sfb->dev);1535 1536 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {1537 win = sfb->windows[win_no];1538 if (!win)1539 continue;1540 1541 /* use the blank function to push into power-down */1542 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);1543 }1544 1545 if (!sfb->variant.has_clksel)1546 clk_disable_unprepare(sfb->lcd_clk);1547 1548 clk_disable_unprepare(sfb->bus_clk);1549 1550 pm_runtime_put_sync(sfb->dev);1551 1552 return 0;1553}1554 1555static int s3c_fb_resume(struct device *dev)1556{1557 struct s3c_fb *sfb = dev_get_drvdata(dev);1558 struct s3c_fb_platdata *pd = sfb->pdata;1559 struct s3c_fb_win *win;1560 int win_no;1561 u32 reg;1562 1563 pm_runtime_get_sync(sfb->dev);1564 1565 clk_prepare_enable(sfb->bus_clk);1566 1567 if (!sfb->variant.has_clksel)1568 clk_prepare_enable(sfb->lcd_clk);1569 1570 /* setup gpio and output polarity controls */1571 pd->setup_gpio();1572 writel(pd->vidcon1, sfb->regs + VIDCON1);1573 1574 /* set video clock running at under-run */1575 if (sfb->variant.has_fixvclk) {1576 reg = readl(sfb->regs + VIDCON1);1577 reg &= ~VIDCON1_VCLK_MASK;1578 reg |= VIDCON1_VCLK_RUN;1579 writel(reg, sfb->regs + VIDCON1);1580 }1581 1582 /* zero all windows before we do anything */1583 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)1584 s3c_fb_clear_win(sfb, win_no);1585 1586 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {1587 void __iomem *regs = sfb->regs + sfb->variant.keycon;1588 win = sfb->windows[win_no];1589 if (!win)1590 continue;1591 1592 shadow_protect_win(win, 1);1593 regs += (win_no * 8);1594 writel(0xffffff, regs + WKEYCON0);1595 writel(0xffffff, regs + WKEYCON1);1596 shadow_protect_win(win, 0);1597 }1598 1599 s3c_fb_set_rgb_timing(sfb);1600 1601 /* restore framebuffers */1602 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {1603 win = sfb->windows[win_no];1604 if (!win)1605 continue;1606 1607 dev_dbg(dev, "resuming window %d\n", win_no);1608 s3c_fb_set_par(win->fbinfo);1609 }1610 1611 pm_runtime_put_sync(sfb->dev);1612 1613 return 0;1614}1615#endif1616 1617#ifdef CONFIG_PM1618static int s3c_fb_runtime_suspend(struct device *dev)1619{1620 struct s3c_fb *sfb = dev_get_drvdata(dev);1621 1622 if (!sfb->variant.has_clksel)1623 clk_disable_unprepare(sfb->lcd_clk);1624 1625 clk_disable_unprepare(sfb->bus_clk);1626 1627 return 0;1628}1629 1630static int s3c_fb_runtime_resume(struct device *dev)1631{1632 struct s3c_fb *sfb = dev_get_drvdata(dev);1633 struct s3c_fb_platdata *pd = sfb->pdata;1634 1635 clk_prepare_enable(sfb->bus_clk);1636 1637 if (!sfb->variant.has_clksel)1638 clk_prepare_enable(sfb->lcd_clk);1639 1640 /* setup gpio and output polarity controls */1641 pd->setup_gpio();1642 writel(pd->vidcon1, sfb->regs + VIDCON1);1643 1644 return 0;1645}1646#endif1647 1648#define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))1649#define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))1650 1651static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {1652 [0] = {1653 .has_osd_c = 1,1654 .osd_size_off = 0x8,1655 .palette_sz = 256,1656 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |1657 VALID_BPP(18) | VALID_BPP(24)),1658 },1659 [1] = {1660 .has_osd_c = 1,1661 .has_osd_d = 1,1662 .osd_size_off = 0xc,1663 .has_osd_alpha = 1,1664 .palette_sz = 256,1665 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |1666 VALID_BPP(18) | VALID_BPP(19) |1667 VALID_BPP(24) | VALID_BPP(25) |1668 VALID_BPP(28)),1669 },1670 [2] = {1671 .has_osd_c = 1,1672 .has_osd_d = 1,1673 .osd_size_off = 0xc,1674 .has_osd_alpha = 1,1675 .palette_sz = 16,1676 .palette_16bpp = 1,1677 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |1678 VALID_BPP(18) | VALID_BPP(19) |1679 VALID_BPP(24) | VALID_BPP(25) |1680 VALID_BPP(28)),1681 },1682 [3] = {1683 .has_osd_c = 1,1684 .has_osd_alpha = 1,1685 .palette_sz = 16,1686 .palette_16bpp = 1,1687 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |1688 VALID_BPP(18) | VALID_BPP(19) |1689 VALID_BPP(24) | VALID_BPP(25) |1690 VALID_BPP(28)),1691 },1692 [4] = {1693 .has_osd_c = 1,1694 .has_osd_alpha = 1,1695 .palette_sz = 4,1696 .palette_16bpp = 1,1697 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |1698 VALID_BPP(16) | VALID_BPP(18) |1699 VALID_BPP(19) | VALID_BPP(24) |1700 VALID_BPP(25) | VALID_BPP(28)),1701 },1702};1703 1704static struct s3c_fb_driverdata s3c_fb_data_64xx = {1705 .variant = {1706 .nr_windows = 5,1707 .vidtcon = VIDTCON0,1708 .wincon = WINCON(0),1709 .winmap = WINxMAP(0),1710 .keycon = WKEYCON,1711 .osd = VIDOSD_BASE,1712 .osd_stride = 16,1713 .buf_start = VIDW_BUF_START(0),1714 .buf_size = VIDW_BUF_SIZE(0),1715 .buf_end = VIDW_BUF_END(0),1716 1717 .palette = {1718 [0] = 0x400,1719 [1] = 0x800,1720 [2] = 0x300,1721 [3] = 0x320,1722 [4] = 0x340,1723 },1724 1725 .has_prtcon = 1,1726 .has_clksel = 1,1727 },1728 .win[0] = &s3c_fb_data_64xx_wins[0],1729 .win[1] = &s3c_fb_data_64xx_wins[1],1730 .win[2] = &s3c_fb_data_64xx_wins[2],1731 .win[3] = &s3c_fb_data_64xx_wins[3],1732 .win[4] = &s3c_fb_data_64xx_wins[4],1733};1734 1735/* S3C2443/S3C2416 style hardware */1736static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {1737 .variant = {1738 .nr_windows = 2,1739 .is_2443 = 1,1740 1741 .vidtcon = 0x08,1742 .wincon = 0x14,1743 .winmap = 0xd0,1744 .keycon = 0xb0,1745 .osd = 0x28,1746 .osd_stride = 12,1747 .buf_start = 0x64,1748 .buf_size = 0x94,1749 .buf_end = 0x7c,1750 1751 .palette = {1752 [0] = 0x400,1753 [1] = 0x800,1754 },1755 .has_clksel = 1,1756 },1757 .win[0] = &(struct s3c_fb_win_variant) {1758 .palette_sz = 256,1759 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),1760 },1761 .win[1] = &(struct s3c_fb_win_variant) {1762 .has_osd_c = 1,1763 .has_osd_alpha = 1,1764 .palette_sz = 256,1765 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |1766 VALID_BPP(18) | VALID_BPP(19) |1767 VALID_BPP(24) | VALID_BPP(25) |1768 VALID_BPP(28)),1769 },1770};1771 1772static const struct platform_device_id s3c_fb_driver_ids[] = {1773 {1774 .name = "s3c-fb",1775 .driver_data = (unsigned long)&s3c_fb_data_64xx,1776 }, {1777 .name = "s3c2443-fb",1778 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,1779 },1780 {},1781};1782MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);1783 1784static const struct dev_pm_ops s3cfb_pm_ops = {1785 SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)1786 SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,1787 NULL)1788};1789 1790static struct platform_driver s3c_fb_driver = {1791 .probe = s3c_fb_probe,1792 .remove = s3c_fb_remove,1793 .id_table = s3c_fb_driver_ids,1794 .driver = {1795 .name = "s3c-fb",1796 .pm = &s3cfb_pm_ops,1797 },1798};1799 1800module_platform_driver(s3c_fb_driver);1801 1802MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");1803MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");1804MODULE_LICENSE("GPL");1805