198 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.5 6 */7 8#ifndef __ACCEL_H__9#define __ACCEL_H__10 11#define FB_ACCEL_VIA_UNICHROME 5012 13/* MMIO Base Address Definition */14#define MMIO_VGABASE 0x800015#define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)16#define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)17#define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)18#define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)19 20/* HW Cursor Status Define */21#define HW_Cursor_ON 022#define HW_Cursor_OFF 123 24#define CURSOR_SIZE (8 * 1024)25#define VQ_SIZE (256 * 1024)26 27#define VIA_MMIO_BLTBASE 0x20000028#define VIA_MMIO_BLTSIZE 0x20000029 30/* Defines for 2D registers */31#define VIA_REG_GECMD 0x00032#define VIA_REG_GEMODE 0x00433#define VIA_REG_SRCPOS 0x00834#define VIA_REG_DSTPOS 0x00C35/* width and height */36#define VIA_REG_DIMENSION 0x01037#define VIA_REG_PATADDR 0x01438#define VIA_REG_FGCOLOR 0x01839#define VIA_REG_BGCOLOR 0x01C40/* top and left of clipping */41#define VIA_REG_CLIPTL 0x02042/* bottom and right of clipping */43#define VIA_REG_CLIPBR 0x02444#define VIA_REG_OFFSET 0x02845/* color key control */46#define VIA_REG_KEYCONTROL 0x02C47#define VIA_REG_SRCBASE 0x03048#define VIA_REG_DSTBASE 0x03449/* pitch of src and dst */50#define VIA_REG_PITCH 0x03851#define VIA_REG_MONOPAT0 0x03C52#define VIA_REG_MONOPAT1 0x04053/* from 0x100 to 0x1ff */54#define VIA_REG_COLORPAT 0x10055 56/* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/57#define VIA_REG_GECMD_M1 0x00058#define VIA_REG_GEMODE_M1 0x00459#define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */60#define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */61#define VIA_REG_DIMENSION_M1 0x00C /* width and height */62#define VIA_REG_DSTPOS_M1 0x01063#define VIA_REG_LINE_XY_M1 0x01064#define VIA_REG_DSTBASE_M1 0x01465#define VIA_REG_SRCPOS_M1 0x01866#define VIA_REG_LINE_K1K2_M1 0x01867#define VIA_REG_SRCBASE_M1 0x01C68#define VIA_REG_PATADDR_M1 0x02069#define VIA_REG_MONOPAT0_M1 0x02470#define VIA_REG_MONOPAT1_M1 0x02871#define VIA_REG_OFFSET_M1 0x02C72#define VIA_REG_LINE_ERROR_M1 0x02C73#define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */74#define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */75#define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */76#define VIA_REG_FGCOLOR_M1 0x04C77#define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */78#define VIA_REG_BGCOLOR_M1 0x05079#define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */80#define VIA_REG_MONOPATFGC_M1 0x058 /* Add BG color of Pattern. */81#define VIA_REG_MONOPATBGC_M1 0x05C /* Add FG color of Pattern. */82#define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */83 84/* VIA_REG_PITCH(0x38): Pitch Setting */85#define VIA_PITCH_ENABLE 0x8000000086 87/* defines for VIA HW cursor registers */88#define VIA_REG_CURSOR_MODE 0x2D089#define VIA_REG_CURSOR_POS 0x2D490#define VIA_REG_CURSOR_ORG 0x2D891#define VIA_REG_CURSOR_BG 0x2DC92#define VIA_REG_CURSOR_FG 0x2E093 94/* VIA_REG_GEMODE(0x04): GE mode */95#define VIA_GEM_8bpp 0x0000000096#define VIA_GEM_16bpp 0x0000010097#define VIA_GEM_32bpp 0x0000030098 99/* VIA_REG_GECMD(0x00): 2D Engine Command */100#define VIA_GEC_NOOP 0x00000000101#define VIA_GEC_BLT 0x00000001102#define VIA_GEC_LINE 0x00000005103 104/* Rotate Command */105#define VIA_GEC_ROT 0x00000008106 107#define VIA_GEC_SRC_XY 0x00000000108#define VIA_GEC_SRC_LINEAR 0x00000010109#define VIA_GEC_DST_XY 0x00000000110#define VIA_GEC_DST_LINRAT 0x00000020111 112#define VIA_GEC_SRC_FB 0x00000000113#define VIA_GEC_SRC_SYS 0x00000040114#define VIA_GEC_DST_FB 0x00000000115#define VIA_GEC_DST_SYS 0x00000080116 117/* source is mono */118#define VIA_GEC_SRC_MONO 0x00000100119/* pattern is mono */120#define VIA_GEC_PAT_MONO 0x00000200121/* mono src is opaque */122#define VIA_GEC_MSRC_OPAQUE 0x00000000123/* mono src is transparent */124#define VIA_GEC_MSRC_TRANS 0x00000400125/* pattern is in frame buffer */126#define VIA_GEC_PAT_FB 0x00000000127/* pattern is from reg setting */128#define VIA_GEC_PAT_REG 0x00000800129 130#define VIA_GEC_CLIP_DISABLE 0x00000000131#define VIA_GEC_CLIP_ENABLE 0x00001000132 133#define VIA_GEC_FIXCOLOR_PAT 0x00002000134 135#define VIA_GEC_INCX 0x00000000136#define VIA_GEC_DECY 0x00004000137#define VIA_GEC_INCY 0x00000000138#define VIA_GEC_DECX 0x00008000139/* mono pattern is opaque */140#define VIA_GEC_MPAT_OPAQUE 0x00000000141/* mono pattern is transparent */142#define VIA_GEC_MPAT_TRANS 0x00010000143 144#define VIA_GEC_MONO_UNPACK 0x00000000145#define VIA_GEC_MONO_PACK 0x00020000146#define VIA_GEC_MONO_DWORD 0x00000000147#define VIA_GEC_MONO_WORD 0x00040000148#define VIA_GEC_MONO_BYTE 0x00080000149 150#define VIA_GEC_LASTPIXEL_ON 0x00000000151#define VIA_GEC_LASTPIXEL_OFF 0x00100000152#define VIA_GEC_X_MAJOR 0x00000000153#define VIA_GEC_Y_MAJOR 0x00200000154#define VIA_GEC_QUICK_START 0x00800000155 156/* defines for VIA 3D registers */157#define VIA_REG_STATUS 0x400158#define VIA_REG_CR_TRANSET 0x41C159#define VIA_REG_CR_TRANSPACE 0x420160#define VIA_REG_TRANSET 0x43C161#define VIA_REG_TRANSPACE 0x440162 163/* VIA_REG_STATUS(0x400): Engine Status */164 165/* Command Regulator is busy */166#define VIA_CMD_RGTR_BUSY 0x00000080167/* 2D Engine is busy */168#define VIA_2D_ENG_BUSY 0x00000002169/* 3D Engine is busy */170#define VIA_3D_ENG_BUSY 0x00000001171/* Virtual Queue is busy */172#define VIA_VR_QUEUE_BUSY 0x00020000173 174/* VIA_REG_STATUS(0x400): Engine Status for H5 */175#define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */176#define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */177#define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */178#define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */179 180/* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */181#define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */182#define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */183#define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */184#define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */185 186#define MAXLOOP 0xFFFFFF187 188#define VIA_BITBLT_COLOR 1189#define VIA_BITBLT_MONO 2190#define VIA_BITBLT_FILL 3191 192int viafb_setup_engine(struct fb_info *info);193void viafb_reset_engine(struct viafb_par *viapar);194void viafb_show_hw_cursor(struct fb_info *info, int Status);195void viafb_wait_engine_idle(struct fb_info *info);196 197#endif /* __ACCEL_H__ */198