319 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.5 6 */7 8#ifndef __SHARE_H__9#define __SHARE_H__10 11#include "via_modesetting.h"12 13/* Define Bit Field */14#define BIT0 0x0115#define BIT1 0x0216#define BIT2 0x0417#define BIT3 0x0818#define BIT4 0x1019#define BIT5 0x2020#define BIT6 0x4021#define BIT7 0x8022 23/* Video Memory Size */24#define VIDEO_MEMORY_SIZE_16M 0x100000025 26/*27 * Lengths of the VPIT structure arrays.28 */29#define StdCR 0x1930#define StdSR 0x0431#define StdGR 0x0932#define StdAR 0x1433 34#define PatchCR 1135 36/* Display path */37#define IGA1 138#define IGA2 239 40/* Define Color Depth */41#define MODE_8BPP 142#define MODE_16BPP 243#define MODE_32BPP 444 45#define GR20 0x2046#define GR21 0x2147#define GR22 0x2248 49/* Sequencer Registers */50#define SR01 0x0151#define SR10 0x1052#define SR12 0x1253#define SR15 0x1554#define SR16 0x1655#define SR17 0x1756#define SR18 0x1857#define SR1B 0x1B58#define SR1A 0x1A59#define SR1C 0x1C60#define SR1D 0x1D61#define SR1E 0x1E62#define SR1F 0x1F63#define SR20 0x2064#define SR21 0x2165#define SR22 0x2266#define SR2A 0x2A67#define SR2D 0x2D68#define SR2E 0x2E69 70#define SR30 0x3071#define SR39 0x3972#define SR3D 0x3D73#define SR3E 0x3E74#define SR3F 0x3F75#define SR40 0x4076#define SR43 0x4377#define SR44 0x4478#define SR45 0x4579#define SR46 0x4680#define SR47 0x4781#define SR48 0x4882#define SR49 0x4983#define SR4A 0x4A84#define SR4B 0x4B85#define SR4C 0x4C86#define SR52 0x5287#define SR57 0x5788#define SR58 0x5889#define SR59 0x5990#define SR5D 0x5D91#define SR5E 0x5E92#define SR65 0x6593 94/* CRT Controller Registers */95#define CR00 0x0096#define CR01 0x0197#define CR02 0x0298#define CR03 0x0399#define CR04 0x04100#define CR05 0x05101#define CR06 0x06102#define CR07 0x07103#define CR08 0x08104#define CR09 0x09105#define CR0A 0x0A106#define CR0B 0x0B107#define CR0C 0x0C108#define CR0D 0x0D109#define CR0E 0x0E110#define CR0F 0x0F111#define CR10 0x10112#define CR11 0x11113#define CR12 0x12114#define CR13 0x13115#define CR14 0x14116#define CR15 0x15117#define CR16 0x16118#define CR17 0x17119#define CR18 0x18120 121/* Extend CRT Controller Registers */122#define CR30 0x30123#define CR31 0x31124#define CR32 0x32125#define CR33 0x33126#define CR34 0x34127#define CR35 0x35128#define CR36 0x36129#define CR37 0x37130#define CR38 0x38131#define CR39 0x39132#define CR3A 0x3A133#define CR3B 0x3B134#define CR3C 0x3C135#define CR3D 0x3D136#define CR3E 0x3E137#define CR3F 0x3F138#define CR40 0x40139#define CR41 0x41140#define CR42 0x42141#define CR43 0x43142#define CR44 0x44143#define CR45 0x45144#define CR46 0x46145#define CR47 0x47146#define CR48 0x48147#define CR49 0x49148#define CR4A 0x4A149#define CR4B 0x4B150#define CR4C 0x4C151#define CR4D 0x4D152#define CR4E 0x4E153#define CR4F 0x4F154#define CR50 0x50155#define CR51 0x51156#define CR52 0x52157#define CR53 0x53158#define CR54 0x54159#define CR55 0x55160#define CR56 0x56161#define CR57 0x57162#define CR58 0x58163#define CR59 0x59164#define CR5A 0x5A165#define CR5B 0x5B166#define CR5C 0x5C167#define CR5D 0x5D168#define CR5E 0x5E169#define CR5F 0x5F170#define CR60 0x60171#define CR61 0x61172#define CR62 0x62173#define CR63 0x63174#define CR64 0x64175#define CR65 0x65176#define CR66 0x66177#define CR67 0x67178#define CR68 0x68179#define CR69 0x69180#define CR6A 0x6A181#define CR6B 0x6B182#define CR6C 0x6C183#define CR6D 0x6D184#define CR6E 0x6E185#define CR6F 0x6F186#define CR70 0x70187#define CR71 0x71188#define CR72 0x72189#define CR73 0x73190#define CR74 0x74191#define CR75 0x75192#define CR76 0x76193#define CR77 0x77194#define CR78 0x78195#define CR79 0x79196#define CR7A 0x7A197#define CR7B 0x7B198#define CR7C 0x7C199#define CR7D 0x7D200#define CR7E 0x7E201#define CR7F 0x7F202#define CR80 0x80203#define CR81 0x81204#define CR82 0x82205#define CR83 0x83206#define CR84 0x84207#define CR85 0x85208#define CR86 0x86209#define CR87 0x87210#define CR88 0x88211#define CR89 0x89212#define CR8A 0x8A213#define CR8B 0x8B214#define CR8C 0x8C215#define CR8D 0x8D216#define CR8E 0x8E217#define CR8F 0x8F218#define CR90 0x90219#define CR91 0x91220#define CR92 0x92221#define CR93 0x93222#define CR94 0x94223#define CR95 0x95224#define CR96 0x96225#define CR97 0x97226#define CR98 0x98227#define CR99 0x99228#define CR9A 0x9A229#define CR9B 0x9B230#define CR9C 0x9C231#define CR9D 0x9D232#define CR9E 0x9E233#define CR9F 0x9F234#define CRA0 0xA0235#define CRA1 0xA1236#define CRA2 0xA2237#define CRA3 0xA3238#define CRD2 0xD2239#define CRD3 0xD3240#define CRD4 0xD4241 242/* LUT Table*/243#define LUT_DATA 0x3C9 /* DACDATA */244#define LUT_INDEX_READ 0x3C7 /* DACRX */245#define LUT_INDEX_WRITE 0x3C8 /* DACWX */246#define DACMASK 0x3C6247 248/* Definition Device */249#define DEVICE_CRT 0x01250#define DEVICE_DVI 0x03251#define DEVICE_LCD 0x04252 253/* Device output interface */254#define INTERFACE_NONE 0x00255#define INTERFACE_ANALOG_RGB 0x01256#define INTERFACE_DVP0 0x02257#define INTERFACE_DVP1 0x03258#define INTERFACE_DFP_HIGH 0x04259#define INTERFACE_DFP_LOW 0x05260#define INTERFACE_DFP 0x06261#define INTERFACE_LVDS0 0x07262#define INTERFACE_LVDS1 0x08263#define INTERFACE_LVDS0LVDS1 0x09264#define INTERFACE_TMDS 0x0A265 266#define HW_LAYOUT_LCD_ONLY 0x01267#define HW_LAYOUT_DVI_ONLY 0x02268#define HW_LAYOUT_LCD_DVI 0x03269#define HW_LAYOUT_LCD1_LCD2 0x04270#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10271 272/* Definition CRTC Timing Index */273#define H_TOTAL_INDEX 0274#define H_ADDR_INDEX 1275#define H_BLANK_START_INDEX 2276#define H_BLANK_END_INDEX 3277#define H_SYNC_START_INDEX 4278#define H_SYNC_END_INDEX 5279#define V_TOTAL_INDEX 6280#define V_ADDR_INDEX 7281#define V_BLANK_START_INDEX 8282#define V_BLANK_END_INDEX 9283#define V_SYNC_START_INDEX 10284#define V_SYNC_END_INDEX 11285#define H_TOTAL_SHADOW_INDEX 12286#define H_BLANK_END_SHADOW_INDEX 13287#define V_TOTAL_SHADOW_INDEX 14288#define V_ADDR_SHADOW_INDEX 15289#define V_BLANK_SATRT_SHADOW_INDEX 16290#define V_BLANK_END_SHADOW_INDEX 17291#define V_SYNC_SATRT_SHADOW_INDEX 18292#define V_SYNC_END_SHADOW_INDEX 19293 294/* LCD display method295*/296#define LCD_EXPANDSION 0x00297#define LCD_CENTERING 0x01298 299/* LCD mode300*/301#define LCD_OPENLDI 0x00302#define LCD_SPWG 0x01303 304struct crt_mode_table {305 int refresh_rate;306 int h_sync_polarity;307 int v_sync_polarity;308 struct via_display_timing crtc;309};310 311struct io_reg {312 int port;313 u8 index;314 u8 mask;315 u8 value;316};317 318#endif /* __SHARE_H__ */319