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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * 1-Wire implementation for the ds2780 chip4 *5 * Copyright (C) 2010 Indesign, LLC6 *7 * Author: Clifton Barnes <cabarnes@indesign-llc.com>8 *9 * Based on w1-ds2760 driver10 */11 12#ifndef _W1_DS2780_H13#define _W1_DS2780_H14 15/* Function commands */16#define W1_DS2780_READ_DATA 0x6917#define W1_DS2780_WRITE_DATA 0x6C18#define W1_DS2780_COPY_DATA 0x4819#define W1_DS2780_RECALL_DATA 0xB820#define W1_DS2780_LOCK 0x6A21 22/* Register map */23/* Register 0x00 Reserved */24#define DS2780_STATUS_REG 0x0125#define DS2780_RAAC_MSB_REG 0x0226#define DS2780_RAAC_LSB_REG 0x0327#define DS2780_RSAC_MSB_REG 0x0428#define DS2780_RSAC_LSB_REG 0x0529#define DS2780_RARC_REG 0x0630#define DS2780_RSRC_REG 0x0731#define DS2780_IAVG_MSB_REG 0x0832#define DS2780_IAVG_LSB_REG 0x0933#define DS2780_TEMP_MSB_REG 0x0A34#define DS2780_TEMP_LSB_REG 0x0B35#define DS2780_VOLT_MSB_REG 0x0C36#define DS2780_VOLT_LSB_REG 0x0D37#define DS2780_CURRENT_MSB_REG 0x0E38#define DS2780_CURRENT_LSB_REG 0x0F39#define DS2780_ACR_MSB_REG 0x1040#define DS2780_ACR_LSB_REG 0x1141#define DS2780_ACRL_MSB_REG 0x1242#define DS2780_ACRL_LSB_REG 0x1343#define DS2780_AS_REG 0x1444#define DS2780_SFR_REG 0x1545#define DS2780_FULL_MSB_REG 0x1646#define DS2780_FULL_LSB_REG 0x1747#define DS2780_AE_MSB_REG 0x1848#define DS2780_AE_LSB_REG 0x1949#define DS2780_SE_MSB_REG 0x1A50#define DS2780_SE_LSB_REG 0x1B51/* Register 0x1C - 0x1E Reserved */52#define DS2780_EEPROM_REG 0x1F53#define DS2780_EEPROM_BLOCK0_START 0x2054/* Register 0x20 - 0x2F User EEPROM */55#define DS2780_EEPROM_BLOCK0_END 0x2F56/* Register 0x30 - 0x5F Reserved */57#define DS2780_EEPROM_BLOCK1_START 0x6058#define DS2780_CONTROL_REG 0x6059#define DS2780_AB_REG 0x6160#define DS2780_AC_MSB_REG 0x6261#define DS2780_AC_LSB_REG 0x6362#define DS2780_VCHG_REG 0x6463#define DS2780_IMIN_REG 0x6564#define DS2780_VAE_REG 0x6665#define DS2780_IAE_REG 0x6766#define DS2780_AE_40_REG 0x6867#define DS2780_RSNSP_REG 0x6968#define DS2780_FULL_40_MSB_REG 0x6A69#define DS2780_FULL_40_LSB_REG 0x6B70#define DS2780_FULL_3040_SLOPE_REG 0x6C71#define DS2780_FULL_2030_SLOPE_REG 0x6D72#define DS2780_FULL_1020_SLOPE_REG 0x6E73#define DS2780_FULL_0010_SLOPE_REG 0x6F74#define DS2780_AE_3040_SLOPE_REG 0x7075#define DS2780_AE_2030_SLOPE_REG 0x7176#define DS2780_AE_1020_SLOPE_REG 0x7277#define DS2780_AE_0010_SLOPE_REG 0x7378#define DS2780_SE_3040_SLOPE_REG 0x7479#define DS2780_SE_2030_SLOPE_REG 0x7580#define DS2780_SE_1020_SLOPE_REG 0x7681#define DS2780_SE_0010_SLOPE_REG 0x7782#define DS2780_RSGAIN_MSB_REG 0x7883#define DS2780_RSGAIN_LSB_REG 0x7984#define DS2780_RSTC_REG 0x7A85#define DS2780_FRSGAIN_MSB_REG 0x7B86#define DS2780_FRSGAIN_LSB_REG 0x7C87#define DS2780_EEPROM_BLOCK1_END 0x7C88/* Register 0x7D - 0xFF Reserved */89 90/* Number of valid register addresses */91#define DS2780_DATA_SIZE 0x8092 93/* Status register bits */94#define DS2780_STATUS_REG_CHGTF (1 << 7)95#define DS2780_STATUS_REG_AEF (1 << 6)96#define DS2780_STATUS_REG_SEF (1 << 5)97#define DS2780_STATUS_REG_LEARNF (1 << 4)98/* Bit 3 Reserved */99#define DS2780_STATUS_REG_UVF (1 << 2)100#define DS2780_STATUS_REG_PORF (1 << 1)101/* Bit 0 Reserved */102 103/* Control register bits */104/* Bit 7 Reserved */105#define DS2780_CONTROL_REG_UVEN (1 << 6)106#define DS2780_CONTROL_REG_PMOD (1 << 5)107#define DS2780_CONTROL_REG_RNAOP (1 << 4)108/* Bit 0 - 3 Reserved */109 110/* Special feature register bits */111/* Bit 1 - 7 Reserved */112#define DS2780_SFR_REG_PIOSC (1 << 0)113 114/* EEPROM register bits */115#define DS2780_EEPROM_REG_EEC (1 << 7)116#define DS2780_EEPROM_REG_LOCK (1 << 6)117/* Bit 2 - 6 Reserved */118#define DS2780_EEPROM_REG_BL1 (1 << 1)119#define DS2780_EEPROM_REG_BL0 (1 << 0)120 121extern int w1_ds2780_io(struct device *dev, char *buf, int addr, size_t count,122 int io);123extern int w1_ds2780_eeprom_cmd(struct device *dev, int addr, int cmd);124 125#endif /* !_W1_DS2780_H */126