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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2007-2017 Cavium, Inc.4 */5#include <asm/asm.h>6#include <asm/regdef.h>7 8#define CVMSEG_BASE -327689#define CVMSEG_SIZE 691210#define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0)11 12 NESTED(octeon_wdt_nmi_stage2, 0, sp)13 .set push14 .set noreorder15 .set noat16 /* Clear Dcache so cvmseg works right. */17 cache 1,0($0)18 /* Use K0 to do a read/modify/write of CVMMEMCTL */19 dmfc0 k0, $11, 720 /* Clear out the size of CVMSEG */21 dins k0, $0, 0, 622 /* Set CVMSEG to its largest value */23 ori k0, k0, 0x1c0 | 5424 /* Store the CVMMEMCTL value */25 dmtc0 k0, $11, 726 /*27 * Restore K0 from the debug scratch register, it was saved in28 * the boot-vector code.29 */30 dmfc0 k0, $3131 32 /*33 * Save all registers to the top CVMSEG. This shouldn't34 * corrupt any state used by the kernel. Also all registers35 * should have the value right before the NMI.36 */37 SAVE_REG(0)38 SAVE_REG(1)39 SAVE_REG(2)40 SAVE_REG(3)41 SAVE_REG(4)42 SAVE_REG(5)43 SAVE_REG(6)44 SAVE_REG(7)45 SAVE_REG(8)46 SAVE_REG(9)47 SAVE_REG(10)48 SAVE_REG(11)49 SAVE_REG(12)50 SAVE_REG(13)51 SAVE_REG(14)52 SAVE_REG(15)53 SAVE_REG(16)54 SAVE_REG(17)55 SAVE_REG(18)56 SAVE_REG(19)57 SAVE_REG(20)58 SAVE_REG(21)59 SAVE_REG(22)60 SAVE_REG(23)61 SAVE_REG(24)62 SAVE_REG(25)63 SAVE_REG(26)64 SAVE_REG(27)65 SAVE_REG(28)66 SAVE_REG(29)67 SAVE_REG(30)68 SAVE_REG(31)69 /* Write zero to all CVMSEG locations per Core-15169 */70 dli a0, CVMSEG_SIZE - (33 * 8)711: sd zero, CVMSEG_BASE(a0)72 daddiu a0, a0, -873 bgez a0, 1b74 nop75 /* Set the stack to begin right below the registers */76 dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8)77 /* Load the address of the third stage handler */78 dla $25, octeon_wdt_nmi_stage379 /* Call the third stage handler */80 jal $2581 /* a0 is the address of the saved registers */82 move a0, sp83 /* Loop forvever if we get here. */842: b 2b85 nop86 .set pop87 END(octeon_wdt_nmi_stage2)88