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1// SPDX-License-Identifier: GPL-2.02/*3 * omap_wdt.c4 *5 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog6 *7 * Author: MontaVista Software, Inc.8 * <gdavis@mvista.com> or <source@mvista.com>9 *10 * 2003 (c) MontaVista Software, Inc.11 *12 * History:13 *14 * 20030527: George G. Davis <gdavis@mvista.com>15 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c16 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>17 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>18 *19 * Copyright (c) 2004 Texas Instruments.20 * 1. Modified to support OMAP1610 32-KHz watchdog timer21 * 2. Ported to 2.6 kernel22 *23 * Copyright (c) 2005 David Brownell24 * Use the driver model and standard identifiers; handle bigger timeouts.25 */26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt28 29#include <linux/module.h>30#include <linux/mod_devicetable.h>31#include <linux/types.h>32#include <linux/kernel.h>33#include <linux/mm.h>34#include <linux/watchdog.h>35#include <linux/reboot.h>36#include <linux/err.h>37#include <linux/platform_device.h>38#include <linux/moduleparam.h>39#include <linux/io.h>40#include <linux/slab.h>41#include <linux/pm_runtime.h>42#include <linux/platform_data/omap-wd-timer.h>43 44#include "omap_wdt.h"45 46static bool nowayout = WATCHDOG_NOWAYOUT;47module_param(nowayout, bool, 0);48MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "49 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");50 51static unsigned timer_margin;52module_param(timer_margin, uint, 0);53MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");54 55#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)56 57static bool early_enable;58module_param(early_enable, bool, 0);59MODULE_PARM_DESC(early_enable,60 "Watchdog is started on module insertion (default=0)");61 62struct omap_wdt_dev {63 struct watchdog_device wdog;64 void __iomem *base; /* physical */65 struct device *dev;66 bool omap_wdt_users;67 int wdt_trgr_pattern;68 struct mutex lock; /* to avoid races with PM */69};70 71static void omap_wdt_reload(struct omap_wdt_dev *wdev)72{73 void __iomem *base = wdev->base;74 75 /* wait for posted write to complete */76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)77 cpu_relax();78 79 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;80 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));81 82 /* wait for posted write to complete */83 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)84 cpu_relax();85 /* reloaded WCRR from WLDR */86}87 88static void omap_wdt_enable(struct omap_wdt_dev *wdev)89{90 void __iomem *base = wdev->base;91 92 /* Sequence to enable the watchdog */93 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);94 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)95 cpu_relax();96 97 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);98 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)99 cpu_relax();100}101 102static void omap_wdt_disable(struct omap_wdt_dev *wdev)103{104 void __iomem *base = wdev->base;105 106 /* sequence required to disable watchdog */107 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */108 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)109 cpu_relax();110 111 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */112 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)113 cpu_relax();114}115 116static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,117 unsigned int timeout)118{119 u32 pre_margin = GET_WLDR_VAL(timeout);120 void __iomem *base = wdev->base;121 122 /* just count up at 32 KHz */123 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)124 cpu_relax();125 126 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);127 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)128 cpu_relax();129}130 131static int omap_wdt_start(struct watchdog_device *wdog)132{133 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);134 void __iomem *base = wdev->base;135 136 mutex_lock(&wdev->lock);137 138 wdev->omap_wdt_users = true;139 140 pm_runtime_get_sync(wdev->dev);141 142 /*143 * Make sure the watchdog is disabled. This is unfortunately required144 * because writing to various registers with the watchdog running has no145 * effect.146 */147 omap_wdt_disable(wdev);148 149 /* initialize prescaler */150 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)151 cpu_relax();152 153 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);154 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)155 cpu_relax();156 157 omap_wdt_set_timer(wdev, wdog->timeout);158 omap_wdt_reload(wdev); /* trigger loading of new timeout value */159 omap_wdt_enable(wdev);160 161 mutex_unlock(&wdev->lock);162 163 return 0;164}165 166static int omap_wdt_stop(struct watchdog_device *wdog)167{168 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);169 170 mutex_lock(&wdev->lock);171 omap_wdt_disable(wdev);172 pm_runtime_put_sync(wdev->dev);173 wdev->omap_wdt_users = false;174 mutex_unlock(&wdev->lock);175 return 0;176}177 178static int omap_wdt_ping(struct watchdog_device *wdog)179{180 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);181 182 mutex_lock(&wdev->lock);183 omap_wdt_reload(wdev);184 mutex_unlock(&wdev->lock);185 186 return 0;187}188 189static int omap_wdt_set_timeout(struct watchdog_device *wdog,190 unsigned int timeout)191{192 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);193 194 mutex_lock(&wdev->lock);195 omap_wdt_disable(wdev);196 omap_wdt_set_timer(wdev, timeout);197 omap_wdt_enable(wdev);198 omap_wdt_reload(wdev);199 wdog->timeout = timeout;200 mutex_unlock(&wdev->lock);201 202 return 0;203}204 205static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)206{207 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);208 void __iomem *base = wdev->base;209 u32 value;210 211 value = readl_relaxed(base + OMAP_WATCHDOG_CRR);212 return GET_WCCR_SECS(value);213}214 215static const struct watchdog_info omap_wdt_info = {216 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,217 .identity = "OMAP Watchdog",218};219 220static const struct watchdog_ops omap_wdt_ops = {221 .owner = THIS_MODULE,222 .start = omap_wdt_start,223 .stop = omap_wdt_stop,224 .ping = omap_wdt_ping,225 .set_timeout = omap_wdt_set_timeout,226 .get_timeleft = omap_wdt_get_timeleft,227};228 229static int omap_wdt_probe(struct platform_device *pdev)230{231 struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);232 struct omap_wdt_dev *wdev;233 int ret;234 235 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);236 if (!wdev)237 return -ENOMEM;238 239 wdev->omap_wdt_users = false;240 wdev->dev = &pdev->dev;241 wdev->wdt_trgr_pattern = 0x1234;242 mutex_init(&wdev->lock);243 244 /* reserve static register mappings */245 wdev->base = devm_platform_ioremap_resource(pdev, 0);246 if (IS_ERR(wdev->base))247 return PTR_ERR(wdev->base);248 249 wdev->wdog.info = &omap_wdt_info;250 wdev->wdog.ops = &omap_wdt_ops;251 wdev->wdog.min_timeout = TIMER_MARGIN_MIN;252 wdev->wdog.max_timeout = TIMER_MARGIN_MAX;253 wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;254 wdev->wdog.parent = &pdev->dev;255 256 watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);257 258 watchdog_set_nowayout(&wdev->wdog, nowayout);259 260 platform_set_drvdata(pdev, wdev);261 262 pm_runtime_enable(wdev->dev);263 pm_runtime_get_sync(wdev->dev);264 265 if (pdata && pdata->read_reset_sources) {266 u32 rs = pdata->read_reset_sources();267 if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))268 wdev->wdog.bootstatus = WDIOF_CARDRESET;269 }270 271 if (early_enable) {272 omap_wdt_start(&wdev->wdog);273 set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);274 } else {275 omap_wdt_disable(wdev);276 }277 278 ret = watchdog_register_device(&wdev->wdog);279 if (ret) {280 pm_runtime_put(wdev->dev);281 pm_runtime_disable(wdev->dev);282 return ret;283 }284 285 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",286 readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,287 wdev->wdog.timeout);288 289 if (early_enable)290 omap_wdt_start(&wdev->wdog);291 292 pm_runtime_put(wdev->dev);293 294 return 0;295}296 297static void omap_wdt_shutdown(struct platform_device *pdev)298{299 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);300 301 mutex_lock(&wdev->lock);302 if (wdev->omap_wdt_users) {303 omap_wdt_disable(wdev);304 pm_runtime_put_sync(wdev->dev);305 }306 mutex_unlock(&wdev->lock);307}308 309static void omap_wdt_remove(struct platform_device *pdev)310{311 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);312 313 pm_runtime_disable(wdev->dev);314 watchdog_unregister_device(&wdev->wdog);315}316 317/* REVISIT ... not clear this is the best way to handle system suspend; and318 * it's very inappropriate for selective device suspend (e.g. suspending this319 * through sysfs rather than by stopping the watchdog daemon). Also, this320 * may not play well enough with NOWAYOUT...321 */322 323static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)324{325 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);326 327 mutex_lock(&wdev->lock);328 if (wdev->omap_wdt_users) {329 omap_wdt_disable(wdev);330 pm_runtime_put_sync(wdev->dev);331 }332 mutex_unlock(&wdev->lock);333 334 return 0;335}336 337static int omap_wdt_resume(struct platform_device *pdev)338{339 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);340 341 mutex_lock(&wdev->lock);342 if (wdev->omap_wdt_users) {343 pm_runtime_get_sync(wdev->dev);344 omap_wdt_enable(wdev);345 omap_wdt_reload(wdev);346 }347 mutex_unlock(&wdev->lock);348 349 return 0;350}351 352static const struct of_device_id omap_wdt_of_match[] = {353 { .compatible = "ti,omap3-wdt", },354 {},355};356MODULE_DEVICE_TABLE(of, omap_wdt_of_match);357 358static struct platform_driver omap_wdt_driver = {359 .probe = omap_wdt_probe,360 .remove_new = omap_wdt_remove,361 .shutdown = omap_wdt_shutdown,362 .suspend = pm_ptr(omap_wdt_suspend),363 .resume = pm_ptr(omap_wdt_resume),364 .driver = {365 .name = "omap_wdt",366 .of_match_table = omap_wdt_of_match,367 },368};369 370module_platform_driver(omap_wdt_driver);371 372MODULE_AUTHOR("George G. Davis");373MODULE_DESCRIPTION("Driver for the TI OMAP 16xx/24xx/34xx 32KHz (non-secure) watchdog");374MODULE_LICENSE("GPL");375MODULE_ALIAS("platform:omap_wdt");376