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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * sp5100_tco: TCO timer driver for sp5100 chipsets.4 *5 * (c) Copyright 2009 Google Inc., All Rights Reserved.6 *7 * TCO timer driver for sp5100 chipsets8 */9 10#include <linux/bitops.h>11 12/*13 * Some address definitions for the Watchdog14 */15#define SP5100_WDT_MEM_MAP_SIZE 0x0816#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */17#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */18 19#define SP5100_WDT_START_STOP_BIT BIT(0)20#define SP5100_WDT_FIRED BIT(1)21#define SP5100_WDT_ACTION_RESET BIT(2)22#define SP5100_WDT_DISABLED BIT(3)23#define SP5100_WDT_TRIGGER_BIT BIT(7)24 25#define SP5100_PM_IOPORTS_SIZE 0x0226 27/*28 * These two IO registers are hardcoded and there doesn't seem to be a way to29 * read them from a register.30 */31 32/* For SP5100/SB7x0/SB8x0 chipset */33#define SP5100_IO_PM_INDEX_REG 0xCD634#define SP5100_IO_PM_DATA_REG 0xCD735 36/* For SP5100/SB7x0 chipset */37#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C38 39#define SP5100_PM_WATCHDOG_CONTROL 0x6940#define SP5100_PM_WATCHDOG_BASE 0x6C41 42#define SP5100_PCI_WATCHDOG_MISC_REG 0x4143#define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3)44 45#define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0))46#define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1)47 48#define SP5100_DEVNAME "SP5100 TCO"49 50/* For SB8x0(or later) chipset */51#define SB800_PM_ACPI_MMIO_EN 0x2452#define SB800_PM_WATCHDOG_CONTROL 0x4853#define SB800_PM_WATCHDOG_BASE 0x4854#define SB800_PM_WATCHDOG_CONFIG 0x4C55 56#define SB800_PCI_WATCHDOG_DECODE_EN BIT(0)57#define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1))58#define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0)59#define SB800_ACPI_MMIO_DECODE_EN BIT(0)60#define SB800_ACPI_MMIO_SEL BIT(1)61#define SB800_ACPI_MMIO_MASK GENMASK(1, 0)62 63#define SB800_PM_WDT_MMIO_OFFSET 0xB0064 65#define SB800_DEVNAME "SB800 TCO"66 67/* For recent chips with embedded FCH (rev 40+) */68 69#define EFCH_PM_DECODEEN 0x0070 71#define EFCH_PM_DECODEEN_WDT_TMREN BIT(7)72 73 74#define EFCH_PM_DECODEEN3 0x0375#define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)76#define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))77 78/* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */79#define EFCH_PM_WDT_ADDR 0xfeb0000080 81#define EFCH_PM_ISACONTROL 0x0482 83#define EFCH_PM_ISACONTROL_MMIOEN BIT(1)84 85#define EFCH_PM_ACPI_MMIO_ADDR 0xfed8000086#define EFCH_PM_ACPI_MMIO_PM_OFFSET 0x0000030087#define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b0088 89#define EFCH_PM_ACPI_MMIO_PM_ADDR (EFCH_PM_ACPI_MMIO_ADDR + \90 EFCH_PM_ACPI_MMIO_PM_OFFSET)91#define EFCH_PM_ACPI_MMIO_PM_SIZE 892#define AMD_ZEN_SMBUS_PCI_REV 0x5193