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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * sunplus Watchdog Driver4 *5 * Copyright (C) 2021 Sunplus Technology Co., Ltd.6 *7 */8 9#include <linux/clk.h>10#include <linux/io.h>11#include <linux/module.h>12#include <linux/mod_devicetable.h>13#include <linux/platform_device.h>14#include <linux/reset.h>15#include <linux/watchdog.h>16 17#define WDT_CTRL 0x0018#define WDT_CNT 0x0419 20#define WDT_STOP 0x387721#define WDT_RESUME 0x4A4B22#define WDT_CLRIRQ 0x748223#define WDT_UNLOCK 0xAB0024#define WDT_LOCK 0xAB0125#define WDT_CONMAX 0xDEAF26 27/* TIMEOUT_MAX = ffff0/90kHz =11.65, so longer than 11 seconds will time out. */28#define SP_WDT_MAX_TIMEOUT 11U29#define SP_WDT_DEFAULT_TIMEOUT 1030 31#define STC_CLK 9000032 33#define DEVICE_NAME "sunplus-wdt"34 35static unsigned int timeout;36module_param(timeout, int, 0);37MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");38 39static bool nowayout = WATCHDOG_NOWAYOUT;40module_param(nowayout, bool, 0);41MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="42 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");43 44struct sp_wdt_priv {45 struct watchdog_device wdev;46 void __iomem *base;47 struct clk *clk;48 struct reset_control *rstc;49};50 51static int sp_wdt_restart(struct watchdog_device *wdev,52 unsigned long action, void *data)53{54 struct sp_wdt_priv *priv = watchdog_get_drvdata(wdev);55 void __iomem *base = priv->base;56 57 writel(WDT_STOP, base + WDT_CTRL);58 writel(WDT_UNLOCK, base + WDT_CTRL);59 writel(0x0001, base + WDT_CNT);60 writel(WDT_LOCK, base + WDT_CTRL);61 writel(WDT_RESUME, base + WDT_CTRL);62 63 return 0;64}65 66static int sp_wdt_ping(struct watchdog_device *wdev)67{68 struct sp_wdt_priv *priv = watchdog_get_drvdata(wdev);69 void __iomem *base = priv->base;70 u32 count;71 72 if (wdev->timeout > SP_WDT_MAX_TIMEOUT) {73 /* WDT_CONMAX sets the count to the maximum (down-counting). */74 writel(WDT_CONMAX, base + WDT_CTRL);75 } else {76 writel(WDT_UNLOCK, base + WDT_CTRL);77 /*78 * Watchdog timer is a 20-bit down-counting based on STC_CLK.79 * This register bits[16:0] is from bit[19:4] of the watchdog80 * timer counter.81 */82 count = (wdev->timeout * STC_CLK) >> 4;83 writel(count, base + WDT_CNT);84 writel(WDT_LOCK, base + WDT_CTRL);85 }86 87 return 0;88}89 90static int sp_wdt_stop(struct watchdog_device *wdev)91{92 struct sp_wdt_priv *priv = watchdog_get_drvdata(wdev);93 void __iomem *base = priv->base;94 95 writel(WDT_STOP, base + WDT_CTRL);96 97 return 0;98}99 100static int sp_wdt_start(struct watchdog_device *wdev)101{102 struct sp_wdt_priv *priv = watchdog_get_drvdata(wdev);103 void __iomem *base = priv->base;104 105 writel(WDT_RESUME, base + WDT_CTRL);106 107 return 0;108}109 110static unsigned int sp_wdt_get_timeleft(struct watchdog_device *wdev)111{112 struct sp_wdt_priv *priv = watchdog_get_drvdata(wdev);113 void __iomem *base = priv->base;114 u32 val;115 116 val = readl(base + WDT_CNT);117 val &= 0xffff;118 val = val << 4;119 120 return val;121}122 123static const struct watchdog_info sp_wdt_info = {124 .identity = DEVICE_NAME,125 .options = WDIOF_SETTIMEOUT |126 WDIOF_MAGICCLOSE |127 WDIOF_KEEPALIVEPING,128};129 130static const struct watchdog_ops sp_wdt_ops = {131 .owner = THIS_MODULE,132 .start = sp_wdt_start,133 .stop = sp_wdt_stop,134 .ping = sp_wdt_ping,135 .get_timeleft = sp_wdt_get_timeleft,136 .restart = sp_wdt_restart,137};138 139static void sp_reset_control_assert(void *data)140{141 reset_control_assert(data);142}143 144static int sp_wdt_probe(struct platform_device *pdev)145{146 struct device *dev = &pdev->dev;147 struct sp_wdt_priv *priv;148 int ret;149 150 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);151 if (!priv)152 return -ENOMEM;153 154 priv->clk = devm_clk_get_enabled(dev, NULL);155 if (IS_ERR(priv->clk))156 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to enable clock\n");157 158 /* The timer and watchdog shared the STC reset */159 priv->rstc = devm_reset_control_get_shared(dev, NULL);160 if (IS_ERR(priv->rstc))161 return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get reset\n");162 163 reset_control_deassert(priv->rstc);164 165 ret = devm_add_action_or_reset(dev, sp_reset_control_assert, priv->rstc);166 if (ret)167 return ret;168 169 priv->base = devm_platform_ioremap_resource(pdev, 0);170 if (IS_ERR(priv->base))171 return PTR_ERR(priv->base);172 173 priv->wdev.info = &sp_wdt_info;174 priv->wdev.ops = &sp_wdt_ops;175 priv->wdev.timeout = SP_WDT_DEFAULT_TIMEOUT;176 priv->wdev.max_hw_heartbeat_ms = SP_WDT_MAX_TIMEOUT * 1000;177 priv->wdev.min_timeout = 1;178 priv->wdev.parent = dev;179 180 watchdog_set_drvdata(&priv->wdev, priv);181 watchdog_init_timeout(&priv->wdev, timeout, dev);182 watchdog_set_nowayout(&priv->wdev, nowayout);183 watchdog_stop_on_reboot(&priv->wdev);184 watchdog_set_restart_priority(&priv->wdev, 128);185 186 return devm_watchdog_register_device(dev, &priv->wdev);187}188 189static const struct of_device_id sp_wdt_of_match[] = {190 {.compatible = "sunplus,sp7021-wdt", },191 { /* sentinel */ }192};193MODULE_DEVICE_TABLE(of, sp_wdt_of_match);194 195static struct platform_driver sp_wdt_driver = {196 .probe = sp_wdt_probe,197 .driver = {198 .name = DEVICE_NAME,199 .of_match_table = sp_wdt_of_match,200 },201};202 203module_platform_driver(sp_wdt_driver);204 205MODULE_AUTHOR("Xiantao Hu <xt.hu@cqplus1.com>");206MODULE_DESCRIPTION("Sunplus Watchdog Timer Driver");207MODULE_LICENSE("GPL");208