1210 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* Generic I/O port emulation.3 *4 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.5 * Written by David Howells (dhowells@redhat.com)6 */7#ifndef __ASM_GENERIC_IO_H8#define __ASM_GENERIC_IO_H9 10#include <asm/page.h> /* I/O is all done through memory accesses */11#include <linux/string.h> /* for memset() and memcpy() */12#include <linux/sizes.h>13#include <linux/types.h>14#include <linux/instruction_pointer.h>15 16#ifdef CONFIG_GENERIC_IOMAP17#include <asm-generic/iomap.h>18#endif19 20#include <asm/mmiowb.h>21#include <asm-generic/pci_iomap.h>22 23#ifndef __io_br24#define __io_br() barrier()25#endif26 27/* prevent prefetching of coherent DMA data ahead of a dma-complete */28#ifndef __io_ar29#ifdef rmb30#define __io_ar(v) rmb()31#else32#define __io_ar(v) barrier()33#endif34#endif35 36/* flush writes to coherent DMA data before possibly triggering a DMA read */37#ifndef __io_bw38#ifdef wmb39#define __io_bw() wmb()40#else41#define __io_bw() barrier()42#endif43#endif44 45/* serialize device access against a spin_unlock, usually handled there. */46#ifndef __io_aw47#define __io_aw() mmiowb_set_pending()48#endif49 50#ifndef __io_pbw51#define __io_pbw() __io_bw()52#endif53 54#ifndef __io_paw55#define __io_paw() __io_aw()56#endif57 58#ifndef __io_pbr59#define __io_pbr() __io_br()60#endif61 62#ifndef __io_par63#define __io_par(v) __io_ar(v)64#endif65 66/*67 * "__DISABLE_TRACE_MMIO__" flag can be used to disable MMIO tracing for68 * specific kernel drivers in case of excessive/unwanted logging.69 *70 * Usage: Add a #define flag at the beginning of the driver file.71 * Ex: #define __DISABLE_TRACE_MMIO__72 * #include <...>73 * ...74 */75#if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))76#include <linux/tracepoint-defs.h>77 78DECLARE_TRACEPOINT(rwmmio_write);79DECLARE_TRACEPOINT(rwmmio_post_write);80DECLARE_TRACEPOINT(rwmmio_read);81DECLARE_TRACEPOINT(rwmmio_post_read);82 83void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,84 unsigned long caller_addr, unsigned long caller_addr0);85void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,86 unsigned long caller_addr, unsigned long caller_addr0);87void log_read_mmio(u8 width, const volatile void __iomem *addr,88 unsigned long caller_addr, unsigned long caller_addr0);89void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,90 unsigned long caller_addr, unsigned long caller_addr0);91 92#else93 94static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,95 unsigned long caller_addr, unsigned long caller_addr0) {}96static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,97 unsigned long caller_addr, unsigned long caller_addr0) {}98static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,99 unsigned long caller_addr, unsigned long caller_addr0) {}100static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,101 unsigned long caller_addr, unsigned long caller_addr0) {}102 103#endif /* CONFIG_TRACE_MMIO_ACCESS */104 105/*106 * __raw_{read,write}{b,w,l,q}() access memory in native endianness.107 *108 * On some architectures memory mapped IO needs to be accessed differently.109 * On the simple architectures, we just read/write the memory location110 * directly.111 */112 113#ifndef __raw_readb114#define __raw_readb __raw_readb115static inline u8 __raw_readb(const volatile void __iomem *addr)116{117 return *(const volatile u8 __force *)addr;118}119#endif120 121#ifndef __raw_readw122#define __raw_readw __raw_readw123static inline u16 __raw_readw(const volatile void __iomem *addr)124{125 return *(const volatile u16 __force *)addr;126}127#endif128 129#ifndef __raw_readl130#define __raw_readl __raw_readl131static inline u32 __raw_readl(const volatile void __iomem *addr)132{133 return *(const volatile u32 __force *)addr;134}135#endif136 137#ifdef CONFIG_64BIT138#ifndef __raw_readq139#define __raw_readq __raw_readq140static inline u64 __raw_readq(const volatile void __iomem *addr)141{142 return *(const volatile u64 __force *)addr;143}144#endif145#endif /* CONFIG_64BIT */146 147#ifndef __raw_writeb148#define __raw_writeb __raw_writeb149static inline void __raw_writeb(u8 value, volatile void __iomem *addr)150{151 *(volatile u8 __force *)addr = value;152}153#endif154 155#ifndef __raw_writew156#define __raw_writew __raw_writew157static inline void __raw_writew(u16 value, volatile void __iomem *addr)158{159 *(volatile u16 __force *)addr = value;160}161#endif162 163#ifndef __raw_writel164#define __raw_writel __raw_writel165static inline void __raw_writel(u32 value, volatile void __iomem *addr)166{167 *(volatile u32 __force *)addr = value;168}169#endif170 171#ifdef CONFIG_64BIT172#ifndef __raw_writeq173#define __raw_writeq __raw_writeq174static inline void __raw_writeq(u64 value, volatile void __iomem *addr)175{176 *(volatile u64 __force *)addr = value;177}178#endif179#endif /* CONFIG_64BIT */180 181/*182 * {read,write}{b,w,l,q}() access little endian memory and return result in183 * native endianness.184 */185 186#ifndef readb187#define readb readb188static inline u8 readb(const volatile void __iomem *addr)189{190 u8 val;191 192 log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);193 __io_br();194 val = __raw_readb(addr);195 __io_ar(val);196 log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);197 return val;198}199#endif200 201#ifndef readw202#define readw readw203static inline u16 readw(const volatile void __iomem *addr)204{205 u16 val;206 207 log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);208 __io_br();209 val = __le16_to_cpu((__le16 __force)__raw_readw(addr));210 __io_ar(val);211 log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);212 return val;213}214#endif215 216#ifndef readl217#define readl readl218static inline u32 readl(const volatile void __iomem *addr)219{220 u32 val;221 222 log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);223 __io_br();224 val = __le32_to_cpu((__le32 __force)__raw_readl(addr));225 __io_ar(val);226 log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);227 return val;228}229#endif230 231#ifdef CONFIG_64BIT232#ifndef readq233#define readq readq234static inline u64 readq(const volatile void __iomem *addr)235{236 u64 val;237 238 log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);239 __io_br();240 val = __le64_to_cpu((__le64 __force)__raw_readq(addr));241 __io_ar(val);242 log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);243 return val;244}245#endif246#endif /* CONFIG_64BIT */247 248#ifndef writeb249#define writeb writeb250static inline void writeb(u8 value, volatile void __iomem *addr)251{252 log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);253 __io_bw();254 __raw_writeb(value, addr);255 __io_aw();256 log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);257}258#endif259 260#ifndef writew261#define writew writew262static inline void writew(u16 value, volatile void __iomem *addr)263{264 log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);265 __io_bw();266 __raw_writew((u16 __force)cpu_to_le16(value), addr);267 __io_aw();268 log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);269}270#endif271 272#ifndef writel273#define writel writel274static inline void writel(u32 value, volatile void __iomem *addr)275{276 log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);277 __io_bw();278 __raw_writel((u32 __force)__cpu_to_le32(value), addr);279 __io_aw();280 log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);281}282#endif283 284#ifdef CONFIG_64BIT285#ifndef writeq286#define writeq writeq287static inline void writeq(u64 value, volatile void __iomem *addr)288{289 log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);290 __io_bw();291 __raw_writeq((u64 __force)__cpu_to_le64(value), addr);292 __io_aw();293 log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);294}295#endif296#endif /* CONFIG_64BIT */297 298/*299 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but300 * are not guaranteed to provide ordering against spinlocks or memory301 * accesses.302 */303#ifndef readb_relaxed304#define readb_relaxed readb_relaxed305static inline u8 readb_relaxed(const volatile void __iomem *addr)306{307 u8 val;308 309 log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);310 val = __raw_readb(addr);311 log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);312 return val;313}314#endif315 316#ifndef readw_relaxed317#define readw_relaxed readw_relaxed318static inline u16 readw_relaxed(const volatile void __iomem *addr)319{320 u16 val;321 322 log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);323 val = __le16_to_cpu((__le16 __force)__raw_readw(addr));324 log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);325 return val;326}327#endif328 329#ifndef readl_relaxed330#define readl_relaxed readl_relaxed331static inline u32 readl_relaxed(const volatile void __iomem *addr)332{333 u32 val;334 335 log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);336 val = __le32_to_cpu((__le32 __force)__raw_readl(addr));337 log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);338 return val;339}340#endif341 342#if defined(readq) && !defined(readq_relaxed)343#define readq_relaxed readq_relaxed344static inline u64 readq_relaxed(const volatile void __iomem *addr)345{346 u64 val;347 348 log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);349 val = __le64_to_cpu((__le64 __force)__raw_readq(addr));350 log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);351 return val;352}353#endif354 355#ifndef writeb_relaxed356#define writeb_relaxed writeb_relaxed357static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)358{359 log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);360 __raw_writeb(value, addr);361 log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);362}363#endif364 365#ifndef writew_relaxed366#define writew_relaxed writew_relaxed367static inline void writew_relaxed(u16 value, volatile void __iomem *addr)368{369 log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);370 __raw_writew((u16 __force)cpu_to_le16(value), addr);371 log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);372}373#endif374 375#ifndef writel_relaxed376#define writel_relaxed writel_relaxed377static inline void writel_relaxed(u32 value, volatile void __iomem *addr)378{379 log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);380 __raw_writel((u32 __force)__cpu_to_le32(value), addr);381 log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);382}383#endif384 385#if defined(writeq) && !defined(writeq_relaxed)386#define writeq_relaxed writeq_relaxed387static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)388{389 log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);390 __raw_writeq((u64 __force)__cpu_to_le64(value), addr);391 log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);392}393#endif394 395/*396 * {read,write}s{b,w,l,q}() repeatedly access the same memory address in397 * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).398 */399#ifndef readsb400#define readsb readsb401static inline void readsb(const volatile void __iomem *addr, void *buffer,402 unsigned int count)403{404 if (count) {405 u8 *buf = buffer;406 407 do {408 u8 x = __raw_readb(addr);409 *buf++ = x;410 } while (--count);411 }412}413#endif414 415#ifndef readsw416#define readsw readsw417static inline void readsw(const volatile void __iomem *addr, void *buffer,418 unsigned int count)419{420 if (count) {421 u16 *buf = buffer;422 423 do {424 u16 x = __raw_readw(addr);425 *buf++ = x;426 } while (--count);427 }428}429#endif430 431#ifndef readsl432#define readsl readsl433static inline void readsl(const volatile void __iomem *addr, void *buffer,434 unsigned int count)435{436 if (count) {437 u32 *buf = buffer;438 439 do {440 u32 x = __raw_readl(addr);441 *buf++ = x;442 } while (--count);443 }444}445#endif446 447#ifdef CONFIG_64BIT448#ifndef readsq449#define readsq readsq450static inline void readsq(const volatile void __iomem *addr, void *buffer,451 unsigned int count)452{453 if (count) {454 u64 *buf = buffer;455 456 do {457 u64 x = __raw_readq(addr);458 *buf++ = x;459 } while (--count);460 }461}462#endif463#endif /* CONFIG_64BIT */464 465#ifndef writesb466#define writesb writesb467static inline void writesb(volatile void __iomem *addr, const void *buffer,468 unsigned int count)469{470 if (count) {471 const u8 *buf = buffer;472 473 do {474 __raw_writeb(*buf++, addr);475 } while (--count);476 }477}478#endif479 480#ifndef writesw481#define writesw writesw482static inline void writesw(volatile void __iomem *addr, const void *buffer,483 unsigned int count)484{485 if (count) {486 const u16 *buf = buffer;487 488 do {489 __raw_writew(*buf++, addr);490 } while (--count);491 }492}493#endif494 495#ifndef writesl496#define writesl writesl497static inline void writesl(volatile void __iomem *addr, const void *buffer,498 unsigned int count)499{500 if (count) {501 const u32 *buf = buffer;502 503 do {504 __raw_writel(*buf++, addr);505 } while (--count);506 }507}508#endif509 510#ifdef CONFIG_64BIT511#ifndef writesq512#define writesq writesq513static inline void writesq(volatile void __iomem *addr, const void *buffer,514 unsigned int count)515{516 if (count) {517 const u64 *buf = buffer;518 519 do {520 __raw_writeq(*buf++, addr);521 } while (--count);522 }523}524#endif525#endif /* CONFIG_64BIT */526 527#ifndef PCI_IOBASE528#define PCI_IOBASE ((void __iomem *)0)529#endif530 531#ifndef IO_SPACE_LIMIT532#define IO_SPACE_LIMIT 0xffff533#endif534 535/*536 * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be537 * implemented on hardware that needs an additional delay for I/O accesses to538 * take effect.539 */540 541#if !defined(inb) && !defined(_inb)542#define _inb _inb543static inline u8 _inb(unsigned long addr)544{545 u8 val;546 547 __io_pbr();548 val = __raw_readb(PCI_IOBASE + addr);549 __io_par(val);550 return val;551}552#endif553 554#if !defined(inw) && !defined(_inw)555#define _inw _inw556static inline u16 _inw(unsigned long addr)557{558 u16 val;559 560 __io_pbr();561 val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));562 __io_par(val);563 return val;564}565#endif566 567#if !defined(inl) && !defined(_inl)568#define _inl _inl569static inline u32 _inl(unsigned long addr)570{571 u32 val;572 573 __io_pbr();574 val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));575 __io_par(val);576 return val;577}578#endif579 580#if !defined(outb) && !defined(_outb)581#define _outb _outb582static inline void _outb(u8 value, unsigned long addr)583{584 __io_pbw();585 __raw_writeb(value, PCI_IOBASE + addr);586 __io_paw();587}588#endif589 590#if !defined(outw) && !defined(_outw)591#define _outw _outw592static inline void _outw(u16 value, unsigned long addr)593{594 __io_pbw();595 __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);596 __io_paw();597}598#endif599 600#if !defined(outl) && !defined(_outl)601#define _outl _outl602static inline void _outl(u32 value, unsigned long addr)603{604 __io_pbw();605 __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);606 __io_paw();607}608#endif609 610#include <linux/logic_pio.h>611 612#ifndef inb613#define inb _inb614#endif615 616#ifndef inw617#define inw _inw618#endif619 620#ifndef inl621#define inl _inl622#endif623 624#ifndef outb625#define outb _outb626#endif627 628#ifndef outw629#define outw _outw630#endif631 632#ifndef outl633#define outl _outl634#endif635 636#ifndef inb_p637#define inb_p inb_p638static inline u8 inb_p(unsigned long addr)639{640 return inb(addr);641}642#endif643 644#ifndef inw_p645#define inw_p inw_p646static inline u16 inw_p(unsigned long addr)647{648 return inw(addr);649}650#endif651 652#ifndef inl_p653#define inl_p inl_p654static inline u32 inl_p(unsigned long addr)655{656 return inl(addr);657}658#endif659 660#ifndef outb_p661#define outb_p outb_p662static inline void outb_p(u8 value, unsigned long addr)663{664 outb(value, addr);665}666#endif667 668#ifndef outw_p669#define outw_p outw_p670static inline void outw_p(u16 value, unsigned long addr)671{672 outw(value, addr);673}674#endif675 676#ifndef outl_p677#define outl_p outl_p678static inline void outl_p(u32 value, unsigned long addr)679{680 outl(value, addr);681}682#endif683 684/*685 * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a686 * single I/O port multiple times.687 */688 689#ifndef insb690#define insb insb691static inline void insb(unsigned long addr, void *buffer, unsigned int count)692{693 readsb(PCI_IOBASE + addr, buffer, count);694}695#endif696 697#ifndef insw698#define insw insw699static inline void insw(unsigned long addr, void *buffer, unsigned int count)700{701 readsw(PCI_IOBASE + addr, buffer, count);702}703#endif704 705#ifndef insl706#define insl insl707static inline void insl(unsigned long addr, void *buffer, unsigned int count)708{709 readsl(PCI_IOBASE + addr, buffer, count);710}711#endif712 713#ifndef outsb714#define outsb outsb715static inline void outsb(unsigned long addr, const void *buffer,716 unsigned int count)717{718 writesb(PCI_IOBASE + addr, buffer, count);719}720#endif721 722#ifndef outsw723#define outsw outsw724static inline void outsw(unsigned long addr, const void *buffer,725 unsigned int count)726{727 writesw(PCI_IOBASE + addr, buffer, count);728}729#endif730 731#ifndef outsl732#define outsl outsl733static inline void outsl(unsigned long addr, const void *buffer,734 unsigned int count)735{736 writesl(PCI_IOBASE + addr, buffer, count);737}738#endif739 740#ifndef insb_p741#define insb_p insb_p742static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)743{744 insb(addr, buffer, count);745}746#endif747 748#ifndef insw_p749#define insw_p insw_p750static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)751{752 insw(addr, buffer, count);753}754#endif755 756#ifndef insl_p757#define insl_p insl_p758static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)759{760 insl(addr, buffer, count);761}762#endif763 764#ifndef outsb_p765#define outsb_p outsb_p766static inline void outsb_p(unsigned long addr, const void *buffer,767 unsigned int count)768{769 outsb(addr, buffer, count);770}771#endif772 773#ifndef outsw_p774#define outsw_p outsw_p775static inline void outsw_p(unsigned long addr, const void *buffer,776 unsigned int count)777{778 outsw(addr, buffer, count);779}780#endif781 782#ifndef outsl_p783#define outsl_p outsl_p784static inline void outsl_p(unsigned long addr, const void *buffer,785 unsigned int count)786{787 outsl(addr, buffer, count);788}789#endif790 791#ifndef CONFIG_GENERIC_IOMAP792#ifndef ioread8793#define ioread8 ioread8794static inline u8 ioread8(const volatile void __iomem *addr)795{796 return readb(addr);797}798#endif799 800#ifndef ioread16801#define ioread16 ioread16802static inline u16 ioread16(const volatile void __iomem *addr)803{804 return readw(addr);805}806#endif807 808#ifndef ioread32809#define ioread32 ioread32810static inline u32 ioread32(const volatile void __iomem *addr)811{812 return readl(addr);813}814#endif815 816#ifdef CONFIG_64BIT817#ifndef ioread64818#define ioread64 ioread64819static inline u64 ioread64(const volatile void __iomem *addr)820{821 return readq(addr);822}823#endif824#endif /* CONFIG_64BIT */825 826#ifndef iowrite8827#define iowrite8 iowrite8828static inline void iowrite8(u8 value, volatile void __iomem *addr)829{830 writeb(value, addr);831}832#endif833 834#ifndef iowrite16835#define iowrite16 iowrite16836static inline void iowrite16(u16 value, volatile void __iomem *addr)837{838 writew(value, addr);839}840#endif841 842#ifndef iowrite32843#define iowrite32 iowrite32844static inline void iowrite32(u32 value, volatile void __iomem *addr)845{846 writel(value, addr);847}848#endif849 850#ifdef CONFIG_64BIT851#ifndef iowrite64852#define iowrite64 iowrite64853static inline void iowrite64(u64 value, volatile void __iomem *addr)854{855 writeq(value, addr);856}857#endif858#endif /* CONFIG_64BIT */859 860#ifndef ioread16be861#define ioread16be ioread16be862static inline u16 ioread16be(const volatile void __iomem *addr)863{864 return swab16(readw(addr));865}866#endif867 868#ifndef ioread32be869#define ioread32be ioread32be870static inline u32 ioread32be(const volatile void __iomem *addr)871{872 return swab32(readl(addr));873}874#endif875 876#ifdef CONFIG_64BIT877#ifndef ioread64be878#define ioread64be ioread64be879static inline u64 ioread64be(const volatile void __iomem *addr)880{881 return swab64(readq(addr));882}883#endif884#endif /* CONFIG_64BIT */885 886#ifndef iowrite16be887#define iowrite16be iowrite16be888static inline void iowrite16be(u16 value, void volatile __iomem *addr)889{890 writew(swab16(value), addr);891}892#endif893 894#ifndef iowrite32be895#define iowrite32be iowrite32be896static inline void iowrite32be(u32 value, volatile void __iomem *addr)897{898 writel(swab32(value), addr);899}900#endif901 902#ifdef CONFIG_64BIT903#ifndef iowrite64be904#define iowrite64be iowrite64be905static inline void iowrite64be(u64 value, volatile void __iomem *addr)906{907 writeq(swab64(value), addr);908}909#endif910#endif /* CONFIG_64BIT */911 912#ifndef ioread8_rep913#define ioread8_rep ioread8_rep914static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,915 unsigned int count)916{917 readsb(addr, buffer, count);918}919#endif920 921#ifndef ioread16_rep922#define ioread16_rep ioread16_rep923static inline void ioread16_rep(const volatile void __iomem *addr,924 void *buffer, unsigned int count)925{926 readsw(addr, buffer, count);927}928#endif929 930#ifndef ioread32_rep931#define ioread32_rep ioread32_rep932static inline void ioread32_rep(const volatile void __iomem *addr,933 void *buffer, unsigned int count)934{935 readsl(addr, buffer, count);936}937#endif938 939#ifdef CONFIG_64BIT940#ifndef ioread64_rep941#define ioread64_rep ioread64_rep942static inline void ioread64_rep(const volatile void __iomem *addr,943 void *buffer, unsigned int count)944{945 readsq(addr, buffer, count);946}947#endif948#endif /* CONFIG_64BIT */949 950#ifndef iowrite8_rep951#define iowrite8_rep iowrite8_rep952static inline void iowrite8_rep(volatile void __iomem *addr,953 const void *buffer,954 unsigned int count)955{956 writesb(addr, buffer, count);957}958#endif959 960#ifndef iowrite16_rep961#define iowrite16_rep iowrite16_rep962static inline void iowrite16_rep(volatile void __iomem *addr,963 const void *buffer,964 unsigned int count)965{966 writesw(addr, buffer, count);967}968#endif969 970#ifndef iowrite32_rep971#define iowrite32_rep iowrite32_rep972static inline void iowrite32_rep(volatile void __iomem *addr,973 const void *buffer,974 unsigned int count)975{976 writesl(addr, buffer, count);977}978#endif979 980#ifdef CONFIG_64BIT981#ifndef iowrite64_rep982#define iowrite64_rep iowrite64_rep983static inline void iowrite64_rep(volatile void __iomem *addr,984 const void *buffer,985 unsigned int count)986{987 writesq(addr, buffer, count);988}989#endif990#endif /* CONFIG_64BIT */991#endif /* CONFIG_GENERIC_IOMAP */992 993#ifdef __KERNEL__994 995#define __io_virt(x) ((void __force *)(x))996 997/*998 * Change virtual addresses to physical addresses and vv.999 * These are pretty trivial1000 */1001#ifndef virt_to_phys1002#define virt_to_phys virt_to_phys1003static inline unsigned long virt_to_phys(volatile void *address)1004{1005 return __pa((unsigned long)address);1006}1007#endif1008 1009#ifndef phys_to_virt1010#define phys_to_virt phys_to_virt1011static inline void *phys_to_virt(unsigned long address)1012{1013 return __va(address);1014}1015#endif1016 1017/**1018 * DOC: ioremap() and ioremap_*() variants1019 *1020 * Architectures with an MMU are expected to provide ioremap() and iounmap()1021 * themselves or rely on GENERIC_IOREMAP. For NOMMU architectures we provide1022 * a default nop-op implementation that expect that the physical address used1023 * for MMIO are already marked as uncached, and can be used as kernel virtual1024 * addresses.1025 *1026 * ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes1027 * for specific drivers if the architecture choses to implement them. If they1028 * are not implemented we fall back to plain ioremap. Conversely, ioremap_np()1029 * can provide stricter non-posted write semantics if the architecture1030 * implements them.1031 */1032#ifndef CONFIG_MMU1033#ifndef ioremap1034#define ioremap ioremap1035static inline void __iomem *ioremap(phys_addr_t offset, size_t size)1036{1037 return (void __iomem *)(unsigned long)offset;1038}1039#endif1040 1041#ifndef iounmap1042#define iounmap iounmap1043static inline void iounmap(volatile void __iomem *addr)1044{1045}1046#endif1047#elif defined(CONFIG_GENERIC_IOREMAP)1048#include <linux/pgtable.h>1049 1050void __iomem *generic_ioremap_prot(phys_addr_t phys_addr, size_t size,1051 pgprot_t prot);1052 1053void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size,1054 unsigned long prot);1055void iounmap(volatile void __iomem *addr);1056void generic_iounmap(volatile void __iomem *addr);1057 1058#ifndef ioremap1059#define ioremap ioremap1060static inline void __iomem *ioremap(phys_addr_t addr, size_t size)1061{1062 /* _PAGE_IOREMAP needs to be supplied by the architecture */1063 return ioremap_prot(addr, size, _PAGE_IOREMAP);1064}1065#endif1066#endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */1067 1068#ifndef ioremap_wc1069#define ioremap_wc ioremap1070#endif1071 1072#ifndef ioremap_wt1073#define ioremap_wt ioremap1074#endif1075 1076/*1077 * ioremap_uc is special in that we do require an explicit architecture1078 * implementation. In general you do not want to use this function in a1079 * driver and use plain ioremap, which is uncached by default. Similarly1080 * architectures should not implement it unless they have a very good1081 * reason.1082 */1083#ifndef ioremap_uc1084#define ioremap_uc ioremap_uc1085static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)1086{1087 return NULL;1088}1089#endif1090 1091/*1092 * ioremap_np needs an explicit architecture implementation, as it1093 * requests stronger semantics than regular ioremap(). Portable drivers1094 * should instead use one of the higher-level abstractions, like1095 * devm_ioremap_resource(), to choose the correct variant for any given1096 * device and bus. Portable drivers with a good reason to want non-posted1097 * write semantics should always provide an ioremap() fallback in case1098 * ioremap_np() is not available.1099 */1100#ifndef ioremap_np1101#define ioremap_np ioremap_np1102static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)1103{1104 return NULL;1105}1106#endif1107 1108#ifdef CONFIG_HAS_IOPORT_MAP1109#ifndef CONFIG_GENERIC_IOMAP1110#ifndef ioport_map1111#define ioport_map ioport_map1112static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)1113{1114 port &= IO_SPACE_LIMIT;1115 return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;1116}1117#define ARCH_HAS_GENERIC_IOPORT_MAP1118#endif1119 1120#ifndef ioport_unmap1121#define ioport_unmap ioport_unmap1122static inline void ioport_unmap(void __iomem *p)1123{1124}1125#endif1126#else /* CONFIG_GENERIC_IOMAP */1127extern void __iomem *ioport_map(unsigned long port, unsigned int nr);1128extern void ioport_unmap(void __iomem *p);1129#endif /* CONFIG_GENERIC_IOMAP */1130#endif /* CONFIG_HAS_IOPORT_MAP */1131 1132#ifndef CONFIG_GENERIC_IOMAP1133#ifndef pci_iounmap1134#define ARCH_WANTS_GENERIC_PCI_IOUNMAP1135#endif1136#endif1137 1138#ifndef xlate_dev_mem_ptr1139#define xlate_dev_mem_ptr xlate_dev_mem_ptr1140static inline void *xlate_dev_mem_ptr(phys_addr_t addr)1141{1142 return __va(addr);1143}1144#endif1145 1146#ifndef unxlate_dev_mem_ptr1147#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr1148static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)1149{1150}1151#endif1152 1153#ifndef memset_io1154#define memset_io memset_io1155/**1156 * memset_io Set a range of I/O memory to a constant value1157 * @addr: The beginning of the I/O-memory range to set1158 * @val: The value to set the memory to1159 * @count: The number of bytes to set1160 *1161 * Set a range of I/O memory to a given value.1162 */1163static inline void memset_io(volatile void __iomem *addr, int value,1164 size_t size)1165{1166 memset(__io_virt(addr), value, size);1167}1168#endif1169 1170#ifndef memcpy_fromio1171#define memcpy_fromio memcpy_fromio1172/**1173 * memcpy_fromio Copy a block of data from I/O memory1174 * @dst: The (RAM) destination for the copy1175 * @src: The (I/O memory) source for the data1176 * @count: The number of bytes to copy1177 *1178 * Copy a block of data from I/O memory.1179 */1180static inline void memcpy_fromio(void *buffer,1181 const volatile void __iomem *addr,1182 size_t size)1183{1184 memcpy(buffer, __io_virt(addr), size);1185}1186#endif1187 1188#ifndef memcpy_toio1189#define memcpy_toio memcpy_toio1190/**1191 * memcpy_toio Copy a block of data into I/O memory1192 * @dst: The (I/O memory) destination for the copy1193 * @src: The (RAM) source for the data1194 * @count: The number of bytes to copy1195 *1196 * Copy a block of data to I/O memory.1197 */1198static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,1199 size_t size)1200{1201 memcpy(__io_virt(addr), buffer, size);1202}1203#endif1204 1205extern int devmem_is_allowed(unsigned long pfn);1206 1207#endif /* __KERNEL__ */1208 1209#endif /* __ASM_GENERIC_IO_H */1210