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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __GENERIC_IO_H3#define __GENERIC_IO_H4 5#include <linux/linkage.h>6#include <asm/byteorder.h>7 8/*9 * These are the "generic" interfaces for doing new-style10 * memory-mapped or PIO accesses. Architectures may do11 * their own arch-optimized versions, these just act as12 * wrappers around the old-style IO register access functions:13 * read[bwl]/write[bwl]/in[bwl]/out[bwl]14 *15 * Don't include this directly, include it from <asm/io.h>.16 */17 18/*19 * Read/write from/to an (offsettable) iomem cookie. It might be a PIO20 * access or a MMIO access, these functions don't care. The info is21 * encoded in the hardware mapping set up by the mapping functions22 * (or the cookie itself, depending on implementation and hw).23 *24 * The generic routines just encode the PIO/MMIO as part of the25 * cookie, and coldly assume that the MMIO IO mappings are not26 * in the low address range. Architectures for which this is not27 * true can't use this generic implementation.28 */29extern unsigned int ioread8(const void __iomem *);30extern unsigned int ioread16(const void __iomem *);31extern unsigned int ioread16be(const void __iomem *);32extern unsigned int ioread32(const void __iomem *);33extern unsigned int ioread32be(const void __iomem *);34#ifdef CONFIG_64BIT35extern u64 ioread64(const void __iomem *);36extern u64 ioread64be(const void __iomem *);37#endif38 39#ifdef readq40#define ioread64_lo_hi ioread64_lo_hi41#define ioread64_hi_lo ioread64_hi_lo42#define ioread64be_lo_hi ioread64be_lo_hi43#define ioread64be_hi_lo ioread64be_hi_lo44extern u64 ioread64_lo_hi(const void __iomem *addr);45extern u64 ioread64_hi_lo(const void __iomem *addr);46extern u64 ioread64be_lo_hi(const void __iomem *addr);47extern u64 ioread64be_hi_lo(const void __iomem *addr);48#endif49 50extern void iowrite8(u8, void __iomem *);51extern void iowrite16(u16, void __iomem *);52extern void iowrite16be(u16, void __iomem *);53extern void iowrite32(u32, void __iomem *);54extern void iowrite32be(u32, void __iomem *);55#ifdef CONFIG_64BIT56extern void iowrite64(u64, void __iomem *);57extern void iowrite64be(u64, void __iomem *);58#endif59 60#ifdef writeq61#define iowrite64_lo_hi iowrite64_lo_hi62#define iowrite64_hi_lo iowrite64_hi_lo63#define iowrite64be_lo_hi iowrite64be_lo_hi64#define iowrite64be_hi_lo iowrite64be_hi_lo65extern void iowrite64_lo_hi(u64 val, void __iomem *addr);66extern void iowrite64_hi_lo(u64 val, void __iomem *addr);67extern void iowrite64be_lo_hi(u64 val, void __iomem *addr);68extern void iowrite64be_hi_lo(u64 val, void __iomem *addr);69#endif70 71/*72 * "string" versions of the above. Note that they73 * use native byte ordering for the accesses (on74 * the assumption that IO and memory agree on a75 * byte order, and CPU byteorder is irrelevant).76 *77 * They do _not_ update the port address. If you78 * want MMIO that copies stuff laid out in MMIO79 * memory across multiple ports, use "memcpy_toio()"80 * and friends.81 */82extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count);83extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count);84extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count);85 86extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);87extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);88extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);89 90#ifdef CONFIG_HAS_IOPORT_MAP91/* Create a virtual mapping cookie for an IO port range */92extern void __iomem *ioport_map(unsigned long port, unsigned int nr);93extern void ioport_unmap(void __iomem *);94#endif95 96#ifndef ioremap_wc97#define ioremap_wc ioremap98#endif99 100#ifndef ioremap_wt101#define ioremap_wt ioremap102#endif103 104#ifndef ioremap_np105/* See the comment in asm-generic/io.h about ioremap_np(). */106#define ioremap_np ioremap_np107static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)108{109 return NULL;110}111#endif112 113#include <asm-generic/pci_iomap.h>114 115#endif116